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German ba4a3cd9f4 SWDEV-439241 - Keep direct map for MGPU
Single OCL context with multiple devices should use direct map
even with persistent memory, because cache coherency layer.

Change-Id: I02a48830440203a1dea176acd4dff4452b70f133


[ROCm/clr commit: 49037b9762]
2024-01-08 18:14:15 -05:00
German 5718f13901 SWDEV-438958 - Calculate persistent memory stored in the cache
- Make sure persistent memory from resource cache is properly adjusted
in free memory calculation.

Change-Id: I74ef68975ccde4694fb1cb904617c418e85dfc9f


[ROCm/clr commit: 85c15d720d]
2024-01-08 10:11:52 -05:00
Rahul Garg 0589a9f7dd SWDEV-439426 - Update HIP patch version reported through CMake
Change-Id: I2b32edfa18d85d49a4b96ff80ea8f60e1df5d517


[ROCm/clr commit: 956cc463bf]
2024-01-08 03:43:01 -05:00
ksankisa 82fd83009c SWDEV-404921 - Add dynamic LDS size hidden kernel argument
Change-Id: If99019058e4bfdc988ef5fc4cef001b772380453


[ROCm/clr commit: f554a075c7]
2024-01-06 08:46:55 +05:30
Satyanvesh Dittakavi 57184d5aac SWDEV-432977 - Set the correct device id in hipIpcOpenMemHandle
hipIpcOpenMemHandle can be used to open memory handle and fetch
  a device pointer on a different device than the actual device
  where the memory was allocated. The device Id must be set to
  the current device in such cases and not the original device.

Change-Id: Ie1c7eada928d02124a41125876876f96015552e5


[ROCm/clr commit: c398c75512]
2024-01-05 00:28:59 -05:00
Saleel Kudchadker 8d5fa39c5b SWDEV-365820 - Refactor build path
This is an initial change before we refactor the build/link paths for
kernel launches for HIP. This current change is needed as compiler was
setting some dump file which needed fs access which has slowdowns for
NFS mounted file systems

Change-Id: I828f9bb04d789b4f8c05c1ed08767f325efeb47c


[ROCm/clr commit: 3f2f7252aa]
2024-01-04 14:20:59 -05:00
David Salinas ecc933301a Enable support for roc-obj tools on Windows
SWDEV-301785 - roc-obj - support for Windows COFF

Change-Id: I20d53196e2d126391934351cb824b7bc926fb1ce


[ROCm/clr commit: 9fa8dcd1d1]
2024-01-04 10:31:02 -05:00
Ioannis Assiouras 30471a9fd9 SWDEV-438299 - Simplified the code in ExtractFatBinaryUsingCOMGR
Change-Id: Ic15f2b71ae87ab3ca36ed5af2c816d57d09b3e70


[ROCm/clr commit: 411bccff5b]
2024-01-04 04:01:58 -05:00
Ioannis Assiouras 1c3e482bd4 SWDEV-438531 - Fixed hipGraphExecMemcpyNodeSetParams for H2H kind
The function erroneously returns hipErrorInvalidValue when kind
is set to hipMemcpyHostToHost

Change-Id: I6810b9f04f3218e517fd2f96410d1375e6ac6ff0


[ROCm/clr commit: af86c1b8a2]
2024-01-04 03:47:39 -05:00
Satyanvesh Dittakavi d1901f2017 SWDEV-434846 - Limit the gpu single allocation percentage for all MI300 versions
Change-Id: I33dea3eaab249ce3f9a624d38267489f99cd530c


[ROCm/clr commit: 755eb2962c]
2024-01-03 23:47:44 -05:00
German Andryeyev b8e7a858a5 SWDEV-311271 - Switch to sorted map for pool allocations
Sorted map can work much faster for many allocations and a low reuse frequency

Change-Id: I6dba29ebc8bfacdf34307149b6a2b194890b2932


[ROCm/clr commit: a1fffac595]
2024-01-03 17:36:05 -05:00
shadi f318f0f7e6 SWDEV-388256 - correct API name
Signed-off-by: shadi <shadi.dashmiz@amd.com>
Change-Id: Icbf79613268fe0737a8033abfbcc9f33d785bc12


[ROCm/clr commit: a071c4d2fc]
2024-01-03 15:06:41 -05:00
Saleel Kudchadker dfb1087c3e SWDEV-422207 - Tag captured kernel names for graphs
Change-Id: I9540daa4abf9c340541a681037e2dca4eec821ed


[ROCm/clr commit: dfd4635f91]
2024-01-03 11:50:05 -05:00
Konstantin Zhuravlyov 326372ce2d Don't pass -fsc-use-buffer-for-hsa-global option in OCLPerfUncoalescedRead test
- This is an SC-only option

Change-Id: If9afe5f8e4ec6dbcf6ce1ca4406131ef92669f84


[ROCm/clr commit: 55e5b3d07a]
2024-01-02 23:13:45 -05:00
Jatin Chaudhary 937678b4f6 SWDEV-436233 - fix the cumode in hiprtc
cumode should be active when wgp mode is off

Change-Id: I12f2e55d942ddeb0fb4470de7abc3caff1f430f7


[ROCm/clr commit: 49369f0851]
2024-01-02 17:43:32 -05:00
German 4750a76899 SWDEV-404889 - Enable debugger interface in PAL
Add GPU_DEBUG_ENABLE to control ttpm behavior. If enabled,
then HW will collect more debug info at some perf cost

Change-Id: Icee0686b903a7b1bd483710b9d611877cd43c6aa


[ROCm/clr commit: 7d661bc7df]
2024-01-02 11:51:42 -05:00
Satyanvesh Dittakavi f423584145 SWDEV-379212 - Handle template kernels with hiprtc lowered names
Change-Id: Ib8e6493a1f342f92a35031d5ee39b2e22132b56a


[ROCm/clr commit: dc8f66b86f]
2024-01-02 03:28:28 -05:00
Jaydeep Patel 5f13c16039 SWDEV-437440 - Specify which defination to use at compile time.
Change-Id: Ibeee914f293d26fa68ab793cac8b662aa34e8df3


[ROCm/clr commit: c3fc607e7d]
2023-12-21 19:59:39 -05:00
Konstantin Zhuravlyov 4abdfe5489 Removed some options
-xnack, -force-wgp-mode, -force-wave-size-32, -round-trip-spirv,
-fe-gen-spirv, -lower-pipe-builtins=0|1, -lower-atomics=0|1,
-set-lds=<value>, -set-scalar-registers=<value>,
-set-vector-registers=<value>, -limit-scalar-registers=<value>,
-limit-vector-registers=<value>, -sc-xnack-iommu,
-faa-for-barrier/-fno-a-for-barrier, -sc-dev-format, -verify-lwspir,
-verify-hwspir, -ffma-enable/-fno-fma-enable,
-fmad-enable/-fno-mad-enable, -fdisable-avx/-fno-disable-avx,
-fforce-llvm/-fno-force-llvm, -print-compile-phases,
-kernel-cache-enforce-miss, -kernel-cache-wipe, -kernel-cache,
-sc[=<filename>]/--load-sc-dll[=<filename>],
-be[=<filename>]/--load-be-dll[=<filename>],
-cg[=<filename>]/--load-cg-dll[=<filename>],
-link[=<filename>]/--load-link-dll[=<filename>],
-opt[=<filename>]/--load-opt-dll[=<filename>],
-fe[=<filename>]/--load-fe-dll[=<filename>],
-cl[=<filename>]/--load-cl-dll[=<filename>], -just-kernel=<kernel-name>,
-use-debugil, -fmulti-level-call/-fno-multi-level-call,
-fdebug-call/-fno-debug-call, -fmacro-call/-fno-macro-call,
-fstack-uav/-fno-stack-uav, -fdef-res-id/-fno-def-res-id,
-wokth=int/--waves-opt-kernel-threshold,
-ilkth=int/--inline-kernel-size-threshold,
-ilsth=int/--inline-size-threshold, -ilcth=int/--inline-cost-threshold,
-scopt=int/--sc-opt-level, -flib-no-inline/-fno-lib-no-inline,
-fuser-no-inline/-fno-user-no-inline,
-scras=int/--sc-si-opt-reg-alloc-strategy, -fsc-post-ra-sched,
-fsc-live-sched/-fno-sc-live-sched, -fsc-use-buffer-for-hsa-global,
-fsc-schedule-no-reorder, -fsc-min-reg-schedule,
-fsc-bias-schedule-to-minimize-insts,
-fsc-bias-schedule-to-minimize-regs, -fsc-disable-merge-memory,
-fsc-disable-loop-unroll, -fsc-use-mubuf/-fno-sc-use-mubuf,
-fsc-selective-inline/-fno-sc-selective-inline,
-fsc-keep-calls/-fno-sc-keep-calls, -slc=0|1/--simplifylibcall,
-stack-alignment=<n>, -fdiv2fmul=0|1, -prt-opt-liveness=0|1,
-liveness=0|1, -SRAE-threshold=<value>, -memcombine-max-vec-gen=<value>,
-small-global-objects, -fast-fmaf, -fast-fma, -bfo=0|1, -ebb=0|1, -aa,
-mem2reg=0|1, -licm=0|1, -unroll-allow-partial,
-unroll-threshold=<positive integer>, -unroll-count=<positive integer>,
-apt/--ap-threshold=<positive integer>, -srt/--sr-threshold=<positive
integer>, -fdebug-linker/-fno-debug-linker, -fbin-gpu64/-fno-bin-gpu64,
-fbin-disasm/-fno-bin-disasm, -fbin-bif30, -fbin-hsail/-fno-bin-hsail,
-fbin-amdil/-fno-bin-amdil, -fbin-spir/-fno-bin-spir, -fonly-bin-source,
-fper-pointer-uav/-fno-per-pointer-uav

Change-Id: I1af5b0a11b55bf75b727057143159fbbf1bb8f0e


[ROCm/clr commit: 15b8cf911a]
2023-12-21 10:18:37 -05:00
Anusha GodavarthySurya 67bb022698 SWDEV-422207 - Fix simple graph test when DEBUG_CLR_GRAPH_PACKET_CAPTURE flag is enabled
- For new AccumulateCommand we enqueue nop barrier packet. So during stream sync we need system flush.

Change-Id: I0b97b626bcdae582ef95e7c95030d78df1fa5a54


[ROCm/clr commit: 748c6b3520]
2023-12-20 22:50:36 -05:00
Anusha GodavarthySurya b10799a7e7 SWDEV-351966 - Rename hip::__hipExtModuleLaunchKernel to hip::hipExtModuleLaunchKernel
Change-Id: Ie922760f37bf0c9abf2653d36e32705a12ab5a90


[ROCm/clr commit: 9b6cf0f74b]
2023-12-20 22:50:01 -05:00
kjayapra-amd 30d6b89d6f SWDEV-413997 - Enable Virtual Mem support by default.
Change-Id: Ia3db3919701708cf95574692e1d47375ca99d7fd


[ROCm/clr commit: e05923b139]
2023-12-20 12:49:16 -05:00
Alex Xie 15756659d0 SWDEV-438177 - move ldconfig to amd opencl package instead of icd
Change-Id: I2486f38d398a508ead7d24f03d4cf7816d5c157c


[ROCm/clr commit: 06ff62da61]
2023-12-20 10:04:58 -05:00
Ioannis Assiouras 7c08efde2a SWDEV-438299 - Fixed out of bounds memory access in ExtractFatBinaryUsingCOMGR
Change-Id: Ib1c6a38da0b81b78d250d7fb88d1194864a0251d


[ROCm/clr commit: 5158ec1c00]
2023-12-20 04:17:40 -05:00
German Andryeyev 3a4261966c SWDEV-311271 - Release freed memory from MemPools
Runtime has to release extra memory, held by the pools,
in synchronization points for event, stream or device.

Change-Id: Id533a5e1d137812aa72bdfe101b4b333c6a43d66


[ROCm/clr commit: 3fa4e31180]
2023-12-19 13:47:04 -05:00
German e6578eda9c SWDEV-1 - Promote PAL verison to 843
Change-Id: I2b8d2fd1df61b376598da53bef530243f8d6e757


[ROCm/clr commit: adf9406a16]
2023-12-19 10:25:32 -05:00
Rahul Garg 0051334261 SWDEV-388256 - Add support of hipExtGetLastError
Change-Id: Ie119d5ea611019996b8a80f7b820ca6a160496a6


[ROCm/clr commit: 92aa9d0fba]
2023-12-18 22:03:22 -05:00
Ioannis Assiouras e51c2f6097 SWDEV-437817 - Fix hipMemCpy2D case that erroneously fails with invalid argument error
When an offset is applied to the source or destination pointers plus the kind is set to
hipMemcpyDefault and the source or destination is allocated with hipMallocManaged
hipMemCpy2D erroneously fails with hipErrorInvalidValue.

Change-Id: I0db4c17514f743652d8f9a2691da6601a2abb2a1


[ROCm/clr commit: d3bfb55d7a]
2023-12-18 07:31:56 -05:00
Anusha GodavarthySurya 5355857116 SWDEV-436405 - Move hipChooseDevice out of hip namespace
Change-Id: I47a3cc5e5409f418b282d1a2e250128c769f4778


[ROCm/clr commit: 4a7291ded8]
2023-12-18 04:37:39 -05:00
taosang2 75b68c4989 SWDEV-435296 - Fix sporatic segment fault
Fix sporatic segment fault in texture test
via retaining image in texture object which
references the image.
The image will be released when the texture
object is destroyed.

Change-Id: Ic3fefa2d5dda6afebd1acd4d41ad310b138af6dd


[ROCm/clr commit: d6d235a111]
2023-12-15 21:06:20 -05:00
Ioannis Assiouras d45267dd2a SWDEV-433745 - Added demangled symbol for hipExtModuleLaunchKernel
Change-Id: Ib8051fcbdf0c8c99e97c845b777d6562220701a0


[ROCm/clr commit: fe739047e5]
2023-12-15 16:59:40 -05:00
German Andryeyev 67597f4901 SWDEV-436869 - Destroy host memory
Recent changes disabled system memory allocation
in the abstraciton layer. That requires memory
allocation/destruction in ROCR. Add destruction logic.

Change-Id: I68fe6b0a620ca743fe5850052ea0efa8bb7931c2


[ROCm/clr commit: a6d480e098]
2023-12-15 16:39:41 -05:00
kjayapra-amd 6a36bf3b30 SWDEV-413997 - Alignment should be a multiple of device granularity.
Change-Id: Ie9c636385bbe3139c2dc24c16f31c9d5e2d56b95


[ROCm/clr commit: f9fd5f4049]
2023-12-15 13:27:23 -05:00
German cba839f38d SWDEV-436796 - Enable device memory for kernel arguments
Extra CPU read back will be performed before every submission to make sure
previous writes over PCIE reached GPU. HDP flush is done by CP.

Change-Id: I402d28ca26c8cee4a3920feb3599af8c285d0889


[ROCm/clr commit: cfc07c88ee]
2023-12-15 13:11:50 -05:00
German fa8e88b108 SWDEV-432575 - Disable direct map for persistent memory
Persistent memory should use direct access for write map and
indirect for read map.

Change-Id: I9fc84836d60088b24012ed25f7ef8c16e33796a3


[ROCm/clr commit: c8b3253a24]
2023-12-15 10:59:01 -05:00
Rahul Garg a7971d31f9 SWDEV-422771 - Update links of ROCm projects
Change-Id: I211308814adce86549ce327ed0a823f799b3de03


[ROCm/clr commit: 35ce9f81d8]
2023-12-15 08:09:21 -05:00
Anusha GodavarthySurya 01c89b94cd SWDEV-436405 - Add hipGetDevicePropertiesR0000 and hipChooseDeviceR0000 to hip dispatch table
Change-Id: I5b373ac030502eb88477d20a1d216bc48369b51d


[ROCm/clr commit: 3e72b8d1e1]
2023-12-15 06:26:52 -05:00
Jaydeep Patel 526e60cb70 SWDEV-411343 - Import VK buffer memory exported by name.
Change-Id: Idc7c840fcd6bf758ecc29ffd6558d24e5bd0a25b


[ROCm/clr commit: 9551d48e7f]
2023-12-14 22:16:11 -05:00
jiabaxie 32b402f11a SWDEV-435477 - correct MACH IDs and add strx1/halo and krackan support for hip
Change-Id: I5b7ed449f4755d69f10677b90ab2b0ceae050b3d


[ROCm/clr commit: f80985f6a1]
2023-12-14 13:07:03 -05:00
kjayapra-amd 9a53a2bec3 SWDEV-413997 - Fixing MGPU cases on PAL side by passing Global Context to virtual alloc.
Change-Id: I6614058d1456d199d710b12acd95160a79aa48c8


[ROCm/clr commit: ec010e4d2d]
2023-12-14 11:34:32 -05:00
German 7883f1e6f7 SWDEV-430809 - Replace hipErrorSharedObjectInitFailed vs hipErrorNoBinaryForGpu
hipErrorSharedObjectInitFailed should be used for interop objects.

Change-Id: Id3bcffaac3b511021f2fd57e9b156a897b646db0


[ROCm/clr commit: 68d442f29a]
2023-12-14 10:35:10 -05:00
sdashmiz 25a8281952 SWDEV-421021 - move new fn pointers to end of the file
Signed-off-by: sdashmiz <shadi.dashmiz@amd.com>
Change-Id: I98d2379b3ef90282de64b22138b1dedcc3586a1b


[ROCm/clr commit: 3a6e1b8fc5]
2023-12-14 09:15:07 -05:00
Sameer Sahasrabuddhe 4cf2b1cfd1 SWDEV-437090: move the __hip_assert macro to a common place
It cannot be moved to amd_device_functions.h because that causes circular
dependences when trying to use the macro in other files. So we create a new
header and move all assert/abort macros to that common header.

As a side-effect, also fix the macro to correctly expand the entire condition
argument, and also consume the trailing semicolon.

Change-Id: I43688c8e61183503a3a1a039b91321a3779152af


[ROCm/clr commit: 7137a296dd]
2023-12-14 09:03:14 -05:00
Anusha GodavarthySurya 3789c40cb5 SWDEV-422207 - Fix graph catch tests with graph optimizations(DEBUG_CLR_GRAPH_PACKET_CAPTURE enabled)
Change-Id: I16297e0ddde286bf1798c90f2bf846e69819010d


[ROCm/clr commit: 2bb2446d8f]
2023-12-14 01:27:08 -05:00
German Andryeyev 7130b87d5c SWDEV-436859 - Enable pitch for COPY_HOST_PTR
Original logic didn't use pitch because, abstraction layer had
a sysmem copy without pitch. Since extra sysmem copy was
disabled, the code has to accept pitch values from the app.

Change-Id: Ia9fba7b33ddff4e9109b4e63d0d6afa52f501c8f


[ROCm/clr commit: fb3dfcf889]
2023-12-13 16:50:16 -05:00
Mark Searles 8b94eaf0a6 SWDEV-435276 - Use -mllvm=<option> syntax rather than -mllvm <option> syntax
Separating -mllvm from its option can cause, in rare circumstances,
the option to be dropped. Or the mllvm to be dropped. Either of which
can cause a compilation error. This issue was exposed investigating
SWDEV-435276

Change-Id: Ie665d49183b55a57c9b58619cad525e44f3be8a5


[ROCm/clr commit: 704d5df91b]
2023-12-13 13:32:51 -05:00
sdashmiz 5e1985996c SWDEV-421021 - Add hipDrvmemsetnode for graph
Signed-off-by: sdashmiz <shadi.dashmiz@amd.com>
Change-Id: I0240a162a16e61549d46b5d086c831404550e833


[ROCm/clr commit: b8e820f835]
2023-12-13 09:30:36 -05:00
Jatin Chaudhary 7fb95958d9 SWDEV-434226 - populate correct output in mempool supported handle type query
Change-Id: Iabbf9c0b54d9978671e3492f13660917499a03fa


[ROCm/clr commit: d5e596c975]
2023-12-13 04:40:41 -05:00
Satyanvesh Dittakavi 542044aadc SWDEV-434846 - Correct the vgprs per simd for MI300
Change-Id: Id4862da7611f64392bfc1538fb644801ec0a9e7f


[ROCm/clr commit: b2102fe939]
2023-12-13 03:06:21 -05:00
Jatin Chaudhary 1114efcc0d SWDEV-431399 - use x86 intrinsics only x86 platforms
This was highlighted by github issue:
https://github.com/ROCm-Developer-Tools/clr/issues/32
On RISC-V platforms this header might not be present.

Change-Id: I5f0959a7b281c760802e76541d50693d1a3902be


[ROCm/clr commit: 12461dbd6a]
2023-12-12 19:10:50 -05:00