Because hipRTC is now using the newer
AMD_COMGR_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC, and now that this
action has been fixed for HIP compilations in Comgr, hipRTC no
longer needs separate Comgr call to link in the device libs.
Change-Id: Ibf9024cbaaab825584566e8d0b5fce60d7063dd8
[ROCm/clr commit: 283dd8352d]
Because hipRTC is now using the newer
AMD_COMGR_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC, and now that this
action has been fixed for HIP compilations in Comgr, hipRTC no
longer needs separate Comgr call to link in the device libs.
Change-Id: Ibf9024cbaaab825584566e8d0b5fce60d7063dd8
Adding support for gfx941 and gfx942 ISAs.
gfx940 ISA will use sc0:1 sc1:1 on load/store operations
gfx942 ISA will use default load/store operations
Change-Id: If1efbef86f59e2cf2d48fe359cd4166405a0a579
Adding support for gfx941 and gfx942 ISAs.
gfx940 ISA will use sc0:1 sc1:1 on load/store operations
gfx942 ISA will use default load/store operations
Change-Id: If1efbef86f59e2cf2d48fe359cd4166405a0a579
[ROCm/ROCR-Runtime commit: 41f6d0426d]
RUNPATH in libraries will be : $ORIGIN
RUNPATH in binaries will be : $ORIGIN/../lib
Change-Id: I87b6a7d1f58f20499c3a0913d03701ac687d910d
[ROCm/clr commit: 31d1420c54]
When compiling in ASAN mode, remap the first page of device allocations
to system memory. ASAN's memory allocator uses a small amount of extra
memory to store data for housekeeping purpose. But because this memory
is from the GPU memory pool, it might have uncommon memory type for host
to access. Mapping this section of memory to the host makes this memory
accessible to ASAN.
Change-Id: I36f659d616a4d15558372592439a8723c5c84a69
Signed-off-by: Bing Ma <Bing.Ma@amd.com>
When compiling in ASAN mode, remap the first page of device allocations
to system memory. ASAN's memory allocator uses a small amount of extra
memory to store data for housekeeping purpose. But because this memory
is from the GPU memory pool, it might have uncommon memory type for host
to access. Mapping this section of memory to the host makes this memory
accessible to ASAN.
Change-Id: I36f659d616a4d15558372592439a8723c5c84a69
Signed-off-by: Bing Ma <Bing.Ma@amd.com>
[ROCm/ROCR-Runtime commit: 50e754d08b]
HIP_FORCE_DEV_KERNARG=1 will create a device allocation for kernel arg
segment. Flag is 0 by default.
Change-Id: Iaaf5a149f3be8596568878d5d272268baf067c60
[ROCm/clr commit: 5436d362b1]
HIP_FORCE_DEV_KERNARG=1 will create a device allocation for kernel arg
segment. Flag is 0 by default.
Change-Id: Iaaf5a149f3be8596568878d5d272268baf067c60
- Use regular copy API if we exhaust free SDMA engines and not fall back
to compute copy. Falling to compute is affecting performance for
numerous apps that are GPU bound
Change-Id: I75c767eff0b9f5ada324301c5c327fe2c23a9806
[ROCm/clr commit: 60d9a4ebab]
- Use regular copy API if we exhaust free SDMA engines and not fall back
to compute copy. Falling to compute is affecting performance for
numerous apps that are GPU bound
Change-Id: I75c767eff0b9f5ada324301c5c327fe2c23a9806
To prevent reset the mutex while using it, only reset the mutex
if it cannot acquire it.
Change-Id: I95e0ed1bf543f285ce81b4df9c51e16a88081d38
[ROCm/rocm_smi_lib commit: 160c99d12d]
Nicholas Curtis
Ioannis Assiouras
gobhardw
Hao Zhou
ROCm CI Service Account
agunashe
Jacob Lambert
AravindanC
David Yat Sin
Jaydeep Patel
Ranjith Ramakrishnan
Ammar ELWazir
Saleel Kudchadker
Alex Voicu
Bill(Shuzhou) Liu
kjayapra-amd
Jenkins