bc0bd00746
Fix queue interception in tools.
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1. Correct amd::AqlQueue::ExecutePM4 to support interception.
2. Minor fixes to AqlPacket and SoftCP.
3. Minimal change to disable interception of runtime internal queues.
Change-Id: I103fece2ebf9a188d27f01e61221c737405d7253
2017-07-12 16:39:43 -04:00
29b5b5c029
Correct handling of slow clocks under linux.
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Change-Id: I9a1b08d5457caa6739220603bbd37b00febc64d7
2017-07-12 12:49:49 -04:00
3e50adc7ce
Properly order signal copy agent tagging with copy operation.
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Change-Id: Ic428c958551279fbea1b2449afba930b82804ede
2017-07-11 13:10:00 -04:00
c9f0427cb0
Decrement hsa_init ref counter when init fails.
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Change-Id: If9376344d4b559e601932d070731132c8450104e
2017-07-07 21:21:03 -05:00
4174f07fd1
hsa-runtime integration
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Change-Id: I48968966ffe164218ebff88d0e3a1268e96bf1dd
2017-07-05 10:55:30 -04:00
08e0bca567
Support Perf Cntrs (PMC) and Thread Trace (SQTT) over AQL queues
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Change-Id: I716b722895d90b46914c31377e791ad602acecc1
2017-06-15 12:58:31 -04:00
5b4df54b10
Revert "Implement memory fault analysis through context save area"
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This reverts commit 75c9506f9d
2017-06-14 14:21:53 -04:00
75c9506f9d
Implement memory fault analysis through context save area
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When a fatal memory fault occurs the scheduler context-saves all queues
in the process and notifies the runtime through the memory event. The
saved state contains all GPR/LDS data at the moment of the fault.
Retrieve this state and present it to the user if HSA_DEBUG_FAULT is set
to "analyze" and the wavefront caused the fault. If amdgcn-capable objdump
is in the PATH invoke this to disassemble code around the PC.
Queue lifetime is now managed by the runtime to allow querying the
context save state for all active queues.
Change-Id: I6fee662fad1c4f9aa125bf5c53d7d0ea1ab32f95
2017-06-13 23:12:28 -04:00
d98e99949a
Update hsa_isa_t entries
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- Add 7.0.2 (consumer hawaii)
- Add 9.0.1 (gfx900 with xnack)
- Add 9.0.2
- Add 9.0.3
Change-Id: I6a07797027c4eaf47038837c5ae51e05b2aba0e4
2017-06-12 14:34:11 -04:00
a0957bc679
The fallback path covers not just ARM64, need this for Power as well.
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Change-Id: I7bbf76f77bd3ac47a0a0987c1e880e23834588e2
2017-06-07 14:45:29 -05:00
5db53ceda1
Enable SDMA on gfx9, disable on gfx8
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gfx9 has passed qualification. gfx8 stability is under investigation.
Change-Id: Ia72211d47756399ecdfceafeb67c2ab34ebda834
2017-06-02 15:14:14 -05:00
c3e2a88ade
Add preferred agent info to pointer info struct.
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Lookup blit agent via pointer info in memory_fill.
Change-Id: I02feaf68bb9726858e8cb0ede6bc5f2b3707f5af
2017-05-31 05:16:05 -04:00
e38ff18990
Unmap GPUs when allow_access removes them from system pools.
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Change-Id: Ib9eb88622fded43ebd9eddbf78ad6771a5b91e77
2017-05-17 20:58:05 -04:00
8aa19388a9
On GFX9+ amd_queue_t.scratch_backing_memory_location must store the queue's scratch backing store VA, not the offset.
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Also fix permission in couple files.
Change-Id: I4203f8e5a36406b20562d8943ea5c341847f039a
2017-04-18 22:37:56 -05:00
f0a1c7c4c6
Fix gfx9 trap handler to retrieve correct return address
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The trap protocol changed between gfx8 and gfx9. The return address
is in trap temporaries [0,1] on gfx9 rather than [4,5] on gfx8.
Unfortunately SP3 changes the meaning of the ttmp register aliases
in gfx9, further confusing the issue.
Clean up later when LLVM assembly build is introduced to the runtime.
Change-Id: I84ea9bf3736f060dd95d0361f9d5a0f9a3576178
2017-04-05 17:33:49 -05:00
8a5ff78be6
Remove comments, no functional change.
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Change-Id: I923c037803a847352c2c50d9d47460cb0f01f22c
2017-03-28 18:22:49 -05:00
7dfeee5074
Support async. queue errors and dynamic scratch without KFD events.
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Change-Id: I4e9e7a37aa7b9c96b28ce79f562760283e02b1e0
2017-03-28 19:18:18 -04:00
c4544906b9
Refactor signal_wait timing code and respect small timeouts.
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Optimized for Gromacs and SHOC.
Change-Id: Ib674710268b41003259711a0e42d3e770a82018d
2017-03-23 23:55:48 -05:00
ba3f1cb476
We should be using the "used" gcc attribute.
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Change-Id: I1589273740ae66e8d7d8186a88e2c411a2e0425c
See: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#Common-Variable-Attributes
2017-03-20 11:57:39 -04:00
7c6cde1871
Disable SDMA only on gfx900 until it is validated.
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Change-Id: Ib960be3ca6d3fc4b664ba047243964b8c7a33f24
2017-03-20 11:55:22 -04:00
a08d760c70
[Loader] Fix memory allocations for code objects that
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are larger than swap space available
Change-Id: I321487f96fe0a18998301a9058430c19427e5a94
2017-03-11 00:57:25 -05:00
5f50e97d18
Support async error code 256, invalid vendor specific packet.
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Change-Id: I491f34def4c3d54403864fa42670f7847a6141cc
2017-03-10 16:20:27 -05:00
2824786b3b
Relax signal assertion.
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Informs, in debug mode only, that a signal wait violated the HSA
spec with regard to the consuming agents list. This list is used
for optimized signal type selection.
Change-Id: I5879f8f822d01af504ab913482b2532feb00be98
2017-03-10 16:05:34 -05:00
05d587ef79
Add inc/ to some include
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Change-Id: Id027b015c8785a132835a422d97a23b0bbce208a
2017-03-09 19:45:01 -08:00
426d41e27c
Adjust signal sleep to reflect null kernel latency. Performance tested on Gromacs.
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Change-Id: I3851148ee8544b15d840f2c26ca73a83f8d0df2e
2017-03-09 15:20:53 -05:00
9887c26113
Bring loader in sync with stg/sc
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Change-Id: Iccce07b8fa03d37c4267a2a9bd343e6614dc43e7
2017-02-10 11:21:15 -05:00
4d62b9482a
Implement code cache invalidation for Gfx9
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When a new enough microcode build is running use a vendor AQL packet
to submit the PM4 IB.
Change-Id: Icd3e2b322c418477420ba4a29f4455ce340ef0d2
2017-02-09 14:15:21 -05:00
505d722b7d
Fix Api table copy operation and tools version checking.
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Change-Id: Ia76d16f3ea6d0abb931813f90bc3bc2119da5999
2017-02-07 14:26:20 -05:00
bc43f97964
Use fixed size type for queue type arguments.
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Change-Id: I81b605c9cc9b18bcef043a4f0292212241ce5987
2017-02-07 01:22:30 -05:00
28f51d5808
Fix Gfx9 write pointer setup
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Should point directly to amd_queue_t.write_dispatch_id. Only noticeable
with HWS enabled which is not yet stable.
Change-Id: I169906d45225379a3ca2729ff04d298fdbb9a9fb
2017-02-06 14:06:12 -05:00
9e575ea96a
Add support for ARM
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- Build system fixes
- No user-mode high-precision timer by default, use clock_gettime
- Use C11 aligned_alloc pending C++17 std::aligned_alloc
Change-Id: I268365bdfd11d1e817a89584b9e086ee5b86e1dc
2017-01-31 16:43:49 -08:00
7e0a5f9c00
Add support for gfx900
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- Route AQL doorbell directly to HW doorbell
- Reuse precompiled Gfx8 shaders on Gfx9 (ISA is compatible)
- Add a warning for unimplemented code cache invalidation
Change-Id: I92096584a1404e35779c96ae6bdc3e0e7fd04721
2017-01-30 16:36:28 -06:00
1cd46afe6d
Implement SDMA path for Gfx9
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Gfx9 requires monotonic write pointer and doorbell.
Cound fields are 1-based compared with 0-based pre-Gfx9.
- Restructure implementation to use monotonic ring indices
- Remove redundant submission size checks (handled by AcquireWriteAddress)
- Unify copy/fill per-command limit (documentation is unclear)
Change-Id: I57c1675221d2e63aa319fee700d9951671e1bd65
2017-01-26 13:11:21 -05:00
a324f21a46
Add new 1.1 image APIs
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Note: Implementation same as 1.0 APIs for now.
The followup change will have the complete implementation.
Change-Id: Ife633f74ff27eee0bb9b0c46952cf5233b0114e8
2017-01-20 19:37:03 -05:00
8ab28d1a51
Add agent properties for Tools
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Change-Id: I7bc49d35dc559f9c9058aae591b88c5ecc4b3ce5
2017-01-16 13:50:18 -06:00
5162a76616
Revert " Add image 1.1 API changes to current code base"
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Currently HSA HW Profiler is failing to build due to this patch
This reverts commit e0ce8855dd
2017-01-12 06:43:54 -05:00
e0ce8855dd
Add image 1.1 API changes to current code base
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Initial work to import the latest (1.1) hsa_ext_image extension.
Change-Id: I4d55adb09ba4d4dbd43d47a4bc54077d4bc531d2
2017-01-11 17:31:37 -05:00
0e17cc2887
Allow reducing max occupancy (max scratch waves) when applications request large amounts of scratch.
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Also emit error messages to stderr if no async queue error callback was registered and queue fault messages are enabled (on by default).
Queue fault messages are controlled with env key HSA_ENABLE_QUEUE_FAULT_MESSAGE.
Change-Id: I496487b8d048b83aa95b9784e92928211f167b17
2016-12-20 16:52:59 -06:00
433a3bcde8
Readme and comment updates to ROCm 1.4
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Change-Id: I2864a9c475b9ceb2fa08bfc35999c7e0e043b26d
2016-12-16 11:43:36 -06:00
160f8c5880
HSA Enabled IPC support
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Uncommented HSA IPC code.
Changed hsa_amd_ipc_memory_t to be 8 uint32_t's instead of 9 to
match spec
Change-Id: Id1523125e9b876a23c3743df1be29c98b47f6725
2016-12-15 19:16:29 -05:00
08aded148a
Revert "Bring loader in sync with stg/sc"
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This reverts commit c798c60343
2016-12-14 15:14:36 -05:00
c798c60343
Bring loader in sync with stg/sc
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Change-Id: I684522c442de0872007a7e4da8919067fc7b42b3
2016-12-13 16:30:25 -05:00
935c1b0ba9
Per review comments
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Change-Id: I44585a6dcf3c4f0ce10f0e895270c113790e0652
2016-11-28 12:41:32 -06:00
eb2efb83d1
Initial set of changes for ThreadTrace
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Change-Id: I07ce31f9b4f508cef0fc9ca6dadcf26b6c90361e
2016-11-21 23:40:56 -06:00
4b86843409
Remove load_legacy parameter + change prefix for some loaded code object queries back to AMD
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Change-Id: I74e905abd77dab3a7a00b5ced94cd9b5130365c5
2016-11-20 13:46:17 -05:00
8081758a55
Add InterProcess memory sharing support.
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Support is disabled pending KFD / Thunk readiness.
Change-Id: I55def748e3d56cbfcfa6e24983a0ab78567aa81d
2016-11-15 18:58:29 -06:00
9dd76dbeda
Add pointer info support.
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Change-Id: I3edcc0bfddbf12465065c9bc3b6565288faff1b8
2016-11-11 18:40:16 -06:00
e01c43578c
Restrict stack usage in interop map to a more reasonable level.
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Change-Id: I663f262a391d1e7f8a6fc3028ea9acbe37d8bcf0
2016-11-10 16:55:55 -06:00
54245e064c
Allocate only one segment for code object v2+
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Change-Id: I7cd03b5c205d3ea5735f8f29820867ca90ac081b
2016-11-03 09:51:11 -04:00
30f1ec2691
Added support for agent attribute HSA_AMD_AGENT_INFO_MAX_WAVES_PER_CU
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Change-Id: I2b90e7165384c4dce928a620a1782395267b35b0
2016-10-28 11:24:21 -04:00
Sean Keely
Evgeny
Ramesh Errabolu
Kenny Ho
Jay Cornwall
Konstantin Zhuravlyov
hthangir
Christophe Paquot
Konstantin Zhuravlyov
Kent Russell
James Edwards
Chris Freehill