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مولف SHA1 پیام تاریخ
Mike Li c2bed10739 Support for Custom Pitch for gfx103x
Signed-off-by: Mike Li <Tianxinmike.Li@amd.com>
Change-Id: Ica83dff8bb382637010396781190f585754bd150


[ROCm/ROCR-Runtime commit: 93609fd3d4]
2021-02-22 22:05:25 -05:00
Jason Tang 562258ec93 Correct GetIsa() typo
Change-Id: Ia6b5a86bd035fb077f0da9d52160ec8d12987b87


[ROCm/ROCR-Runtime commit: ec22afb8a8]
2021-02-17 11:57:58 -05:00
Sean Keely 622dc89e98 Correct legacy copy path.
Legacy p2p copy path incorrectly transfered in whole pages rather than
the requested size.

Change-Id: I9aa7337754f9e32f587a0cc5305f8ffeb6196f10


[ROCm/ROCR-Runtime commit: 34ac62274a]
2021-02-10 19:53:02 -05:00
Sean Keely 4047b1c3a8 Add hsa_amd_signal_value_pointer.
Enables partial signal interop with non-HSA devices.

Change-Id: Ic39bca84ed1709cbd2cc24b1eb0f4fc6cccb39cf


[ROCm/ROCR-Runtime commit: 01f42dbe46]
2021-02-10 18:47:54 -05:00
Laurent Morichetti b3dc12024b New trap handler ABI (v4)
Replace the stop reasons ttmp11.trap_raised and ttmp11.excp_raised
with ttmp11.wave_stopped which indicates that the trap handler has
halted the wave as the result of an event (trap, single-step or
exception).

If the wave is stopped because of a trap, also record the trap_id in
ttmp11.saved_trap_id[7:0].

Save status.halt in ttmp11.saved_status_halt, so that it can be
restored when resuming a wave (changing a wave's state from stopped to
running or single-stepping).

Change-Id: I7322f59b60e8cc1b92bf5f067dba606a3109ef49


[ROCm/ROCR-Runtime commit: 9ca79d072a]
2021-02-05 09:56:01 -08:00
Evgeny 95ee562f1a adding gfx1030 blocks
Change-Id: Ide2576939c5321dbe928183a8d9984d5ef87a61b


[ROCm/ROCR-Runtime commit: c5aae30d08]
2021-01-29 08:50:10 -06:00
Huang Rui 36d1285c53 Add gfx 10.3.3 into rocrtst list
Change-Id: I854e5092236175e47a2134d703f154885cae8c3e
Signed-off-by: Huang Rui <ray.huang@amd.com>


[ROCm/ROCR-Runtime commit: 554ed5e76d]
2021-01-22 04:22:15 -05:00
Huang Rui cb0f788b9b Add gfx10.3.3 ISA support for Van Gogh
This patch is to let ROCr recognize new gfx10.3.3 ISA.

Change-Id: Ied23eee2752e14c19c8c0a6d7789fded9940e31e
Signed-off-by: Huang Rui <ray.huang@amd.com>


[ROCm/ROCR-Runtime commit: feeb2f62e2]
2021-01-22 04:22:15 -05:00
Laurent Morichetti 062d313530 Don't terminate waves halted at s_endpgm
To support single stepping the instruction preceding an s_endpgm,
unwind the PC by 8 bytes and set ttmp11[9] to notify the debugger
that the wave is halted with a modified PC.

Bump the debug r_version for this new trap handler ABI.

Change-Id: I55e4e0d65576f92da14a336266c31c513baab547


[ROCm/ROCR-Runtime commit: 8aec53969f]
2021-01-21 20:51:38 -08:00
Laurent Morichetti 3eaae50cc6 Correct gfx10.3+ trap handler.
Change-Id: I77d2b41c8882014a430d741ecd777718a1f61561


[ROCm/ROCR-Runtime commit: 8808ed3177]
2021-01-21 09:24:20 -08:00
Tony Tye 0aa0ebe2ee Correct isa lookup for targets that do not support a target feature
Change-Id: I130070a53162e5d9fcc6a64a4bdda7869179be82


[ROCm/ROCR-Runtime commit: 26fe26e415]
2021-01-18 15:47:19 +00:00
Chris Freehill 33438e7adc Correct some target ID strings for gfx908
Change-Id: I7833b561447b9928447cf49472cfe1ca1867e71d


[ROCm/ROCR-Runtime commit: 09bc75bf0d]
2021-01-15 14:56:38 -06:00
Sean Keely 343684f84d Correct computation of scratch slot requirements.
Each SE must be assigned equal numbers of slots and slots
must be assigned in units of whole groups.

Change-Id: I8f3677237fa6f2e2d25e3e78210c5a7a0ad792f3


[ROCm/ROCR-Runtime commit: 7bc6aac5d2]
2021-01-13 15:09:00 -05:00
Sean Keely ddfed66eec Revert "Revert "Cache scratch allocations.""
This reverts commit 4502bb94c9.

Change-Id: I3f3c257270016559f8b2e70151664f0931db28d2


[ROCm/ROCR-Runtime commit: 9fe8ccc3ee]
2021-01-13 15:08:53 -05:00
Tony Tye fdfedaf0d2 Improve Isa class
- Use consistent naming in Isa class.
- Remove unused Isa methods.
- Simplify Isa methods.

Change-Id: I7c4045d08fbfe0d94b3181db8ebc5e5ed8c8cc82


[ROCm/ROCR-Runtime commit: 6bbf6b1c9c]
2021-01-10 18:23:54 +00:00
Tony 3fdfbc56e4 Store target ID in isa registry
Store target ID string in isa registry and use for returning agent and
isa name.

Change-Id: I72a20d8ff963c73d86392158aff3853e4c9bfdbd


[ROCm/ROCR-Runtime commit: 853ccc762e]
2021-01-10 18:23:54 +00:00
Tony bc565f6c69 Correct code object V2 support
- Remove gfx800, gfx804 and gfx901 as they do not exist.
- Map the V2 note record of "AMD:AMDGPU:8:0:0" to gfx802 as they are
  the same target just connected to a differnt motherboard.
- Correct typo for supporting gfx902:xnack+.
- Support agent names with a minor or stepping version greater than 9.

Change-Id: Ife933449f60ab4687e2aaab9baf4c9fc5b86339d


[ROCm/ROCR-Runtime commit: 12eb2764cd]
2021-01-10 18:23:54 +00:00
Sean Keely 4502bb94c9 Revert "Cache scratch allocations."
This reverts commit ce4de85616.

Change-Id: I698b33bacb2be3de6c8185fe89597a60a79521c5


[ROCm/ROCR-Runtime commit: 7e2ba23566]
2021-01-08 11:57:40 -06:00
Sean Keely 0639b53e31 Add support for gfx1032.
Change-Id: I36f93a6b61e74cf17aac1a05d7c1d4ba6369fcc9


[ROCm/ROCR-Runtime commit: d39ae13420]
2021-01-05 17:28:19 -06:00
Sean Keely 14dd324d2f Cleanup warnings when using clang.
Change-Id: I09f72831e29bccdb4170c54e203872412e2f0b59


[ROCm/ROCR-Runtime commit: bd63a2b690]
2020-12-04 22:18:14 -06:00
Tony b36aad204e Make supported targets consistent
Add missing target names and make all parts consistent with which
targets are supported.

- Add gfx805 as a supported target.

- Add all ELF targets to genric code.

- Make offline loader match supported targets.

Change-Id: Idab4d69edc71645aecaa83aa55e29c1aeee4c1d6


[ROCm/ROCR-Runtime commit: b443397bcc]
2020-11-24 03:14:31 +00:00
Sean Keely 62138712cf Add asserts and minimum values for kernarg alignment and utility functions.
Kernel argument size and alignment queries are not supported on
code object v3.

Change-Id: I1bdd34e2e62132f912ac39d80355efd3456df87c


[ROCm/ROCR-Runtime commit: 6182abf5e9]
2020-11-21 21:39:49 -06:00
Tony e1734526fc Update code object V3 kernarg queries
Code object V2 had the ability to support the following queries:

- HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE
- HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE
- HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT
- HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT

However code object V3 onwards cannot support these as the kernel
descriptor changed. These queries need to be deprecated.

Until then return more reasonable values:

- For kernarg alignment return 16 which is the minimum alignment
  required by the HSA standard.

- For kernarg size return the field from the kernel descriptor which
  is a hint. If it is 0 then the compiler is not specifying the kernarg
  size, or the kernel has no kernarg.

Change-Id: I19ce6cd0f3658a2bf62277492f39100ea5ab4256


[ROCm/ROCR-Runtime commit: ef755e4c82]
2020-11-20 21:39:18 -05:00
Sean Keely ce4de85616 Cache scratch allocations.
Avoids calling to KFD to map/unmap scratch allocations for
every large scratch using dispatch.

Change-Id: I9fab5705251ec82b03e4f2f2ca6da7cdccabefb9


[ROCm/ROCR-Runtime commit: 27e044ae4d]
2020-11-20 15:07:01 -05:00
Sean Keely 20f9fbd7f2 Limit clock synchronization to 16Hz.
Improves HIP event performance in directed benchmarks where
clock sync latency is significant.

Change-Id: I78b724a14a8f5b6a9a2b9f4d85afe9d8b81808a6


[ROCm/ROCR-Runtime commit: 32d0fcafa9]
2020-11-20 15:06:13 -05:00
Sean Keely eacc927741 Style update for SDMA enable flag.
Updated to match xnack flag's style.

Change-Id: I6115c0b53660d789e698de1606a9388ae1789866


[ROCm/ROCR-Runtime commit: b51f68b535]
2020-11-20 15:06:02 -05:00
Cordell Bloor 63953d98e1 Fix CMake configure error due to CMP0012
The modern meaning of the construct if( NOT ON ) was added in CMake 2.8,
but when the cmake_minimum_required not set in user code and no policy
level is set in the CMake config, then CMake 2.8 features cannot be
used. In old CMake (the default), ON is interpreted as a variable, and
because it is not defined, it is considered false. The same is true of
OFF.

This change sets a variable as ON, so that old CMake interpretation is
correct, and the if works as expected regardless of policy version.

Change-Id: I67d7ed4ceaf8248eeb5a1c7f54009d72313f3f5d


[ROCm/ROCR-Runtime commit: 4a35f560f6]
2020-11-20 15:04:41 -05:00
Cole Nelson 5dd453a265 opensrc/hsa-runtime/CMakeLists.txt: conformant package names
Names test good:
hsa-rocr-dev_1.2.0.30900-crdnnv.415_amd64.deb
hsa-rocr-dev-1.2.0.30900-crdnnv.415.el7.x86_64.rpm
hsa-rocr-dev-1.2.0.30900-crdnnv.sles151.415.x86_64.rpm

http://confluence.amd.com/display/GPUCPT/Package+File+Naming

Note: rpm requires 'devel' instead of 'dev', to be a subsequent
patchset.

Change-Id: Id6a422f3c335448b52c70c77ed39c9041114b80f
Signed-off-by: Cole Nelson <cole.nelson@amd.com>


[ROCm/ROCR-Runtime commit: 90f2dd5b1b]
2020-11-18 14:56:24 -05:00
Pruthvi Madugundu f254139e48 Fix for uninstallation problem of hsa-rocr-dev
- /opt/rocm-xx/hsa/include directory wasnt deleted after
  debian package uninstallation
- , 

Signed-off-by: Pruthvi Madugundu <pruthvi.madugundu@amd.com>
Change-Id: I213439d73f6533ff3a55e2b0071061d970cf56d4


[ROCm/ROCR-Runtime commit: 87955f8551]
2020-11-11 12:32:11 -08:00
Konstantin Zhuravlyov ba667661c5 Implement Target ID Proposal
Changes from Konstantin Zhuravlyov, Tony Tye

Change-Id: I532801193afa9d5b8ac2a877b5497eab661f0597


[ROCm/ROCR-Runtime commit: 3a08d0964e]
2020-11-10 13:42:35 -05:00
Sean Keely 56fa259711 Diable sram ecc reporting.
Temporary workaround while language and compiler teams sort out
handling both modes.

Change-Id: I5d676cd546382dba05ec0b62bb885baa854614f6


[ROCm/ROCR-Runtime commit: a09ba8bcc8]
2020-10-20 17:06:30 -05:00
Arun Sunil 8c495a73de CMakeLists.txt: Fix issue with rocrtst
Fix for issue where rocrtst could not be built if out directory 
was outside the src (WORK_ROOT) directory due to hard-coded 
relative path for OPENCL_INC_DIR.

Change-Id: Icb93de2266d568e9c2437166e34c88ec526fb45c


[ROCm/ROCR-Runtime commit: 8d00f1aa59]
2020-10-13 18:14:26 -04:00
Evgeny 2c1f448744 aqlprofile: adding counters DISABLE get-info id
Change-Id: I90d0f6ae96b0d80c481648eecf907301fc13ab74


[ROCm/ROCR-Runtime commit: 0d1e5cbcb6]
2020-10-12 17:12:25 -05:00
Sean Keely c3142d6b6d Initialize intercept queue packets properly.
Change-Id: I0ff1540940665409a9ade3a517dd576a8f334c7b


[ROCm/ROCR-Runtime commit: 9192dfe1b0]
2020-10-08 15:33:43 -05:00
Chris Freehill 6e6cc27c73 Add README for rocrtst
Change-Id: Icd43a243ccfc9caf5ade3cd0e7ffc00e251fc0a2


[ROCm/ROCR-Runtime commit: 2b41fb9fdc]
2020-09-28 20:27:53 -05:00
Sean Keely e78c1df5e3 Correct return type error in hsa_amd_signal_wait_any.
The error checking macro IS_OPEN returns an hsa_signal_t.
This conflicts with the return type of uint32_t.

Add an assert and rely on spurious return rule to return zero
when rocr is not initialized.

Change-Id: Ifc9bb75e22ecdd675273de59b31e5026a69c62e0


[ROCm/ROCR-Runtime commit: a3c4aaf95a]
2020-09-25 21:33:23 -04:00
Sean Keely d78de2d062 Add try/catch blocks to image APIs.
Change-Id: I724dcc8015ac556649278dd6cdf1ad4097aaa846


[ROCm/ROCR-Runtime commit: 248904ab26]
2020-09-22 19:49:36 -04:00
Sean Keely e5df994bff Correct image limits tables to SI limits.
Limits remain unchanged through gfx1030.

Change-Id: Ibdd39b7b97101ea0133af6cebdf295aeef81ac45


[ROCm/ROCR-Runtime commit: 33a57ddf72]
2020-09-22 19:49:08 -04:00
Chris Freehill d529685dd8 Add gfx1031 support
Change-Id: I855f7fe8d096331d0c1da10b10adf6b1e75a527f


[ROCm/ROCR-Runtime commit: 4944c74189]
2020-09-10 11:06:58 -04:00
Sean Keely fe47915a8e Use SDMA for small copies in VRAM.
For small copies cache flush latency is larger than data transfer
latency in local VRAM.  Select SDMA for small copies.

Environment key HSA_FORCE_SDMA_SIZE is added for easy adjustment
of the small copy size.  This may be removed after tuning is done.

Change-Id: I733fa0ae01c616617c5de50e71226b51fd589ef2


[ROCm/ROCR-Runtime commit: 2a0c6774fb]
2020-09-03 03:11:57 -05:00
Sean Keely 700dca7dd4 Correct memory release function.
l_name is populated by strdup which requires using free rather
than delete.

Change-Id: I9d9bdcfaa3ef095502270f332b95a0ee5c0bbcfc


[ROCm/ROCR-Runtime commit: 9c20f0e649]
2020-08-26 18:22:59 -05:00
Sean Keely ecf5e6ca8f Convert from double to uint64_t in two steps.
We want wraparound behavior here but we don't want to trigger sanitizer
warnings.  Converting to int64_t and then wraping around by cast to
uint64_t avoids the UB issue that triggers the sanitizer warning.

Change-Id: I9400b988dce7899e9ba42cab3e35c7ffedec8fe1


[ROCm/ROCR-Runtime commit: 5f43778a51]
2020-08-25 20:12:52 -05:00
Cole Nelson 7f409a38c1 packaging: set arch, field separators, vendor info
Enables standards compliant package naming for debian and rpm.

Change-Id: Iad86bf942b4e2938516ef46cda6fa2e4bb3744cc
Signed-off-by: Cole Nelson <cole.nelson@amd.com>


[ROCm/ROCR-Runtime commit: 24bad55dc7]
2020-08-21 11:33:05 -04:00
Chris Freehill 2067fc4f85 Fix build issue with memset use on newer gcc version
Change-Id: I57824a3dac94d3da3675f7c74f2e3bc5ac1052ed


[ROCm/ROCR-Runtime commit: 78be4b8225]
2020-08-19 09:13:24 -05:00
Sean Keely 6b75c08312 Add gfx1030 to image blit kernel build list.
Change-Id: I2ddb6a595bb7ca5f6a94f38f8ecc2e40831c52fd


[ROCm/ROCR-Runtime commit: 1d919adc75]
2020-08-12 16:38:39 -05:00
Sean Keely 240a56b059 Switch to release e_flags id for gfx1030.
Change-Id: I51c9ecdf78d6ec56ccc70ca5777bb011db35fda3


[ROCm/ROCR-Runtime commit: 78e5c06ea8]
2020-08-12 16:38:16 -05:00
Sean Keely d095c05aae Add xnack isa recognition to gfx1030.
Change-Id: I99301a62f1952b6a3cc548272f4129ad8c0542da


[ROCm/ROCR-Runtime commit: dc7e5e7e46]
2020-08-12 16:34:17 -05:00
Sean Keely d4b61cc3e6 Add ELF types for gfx1030.
Change-Id: If875534d698da9840e47c380d5630b6dd742ab0c


[ROCm/ROCR-Runtime commit: ddfe07871a]
2020-08-12 16:34:17 -05:00
Chris Freehill 9e97c1acd1 Add gfx1030 support
Change-Id: I4bccc731ba802480925f98c6c42593503bf9b98d


[ROCm/ROCR-Runtime commit: e702531b40]
2020-08-12 16:34:10 -05:00
Ramesh Errabolu 3b1a619d0a IPC child process should exit and not return
Change-Id: I9b01f473eea1b42cf65c042f89fcf24bfd2ffc0d


[ROCm/ROCR-Runtime commit: 3444da7df6]
2020-08-10 11:19:21 -05:00