hsa_amd_memory_lock_to_pool() and hsa_amd_memory_unlock()
should be called balanced.
Change-Id: I8b1549861bff752aabbb6399d717d1e346079a38
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Recent changes disabled system memory allocation
in the abstraciton layer. That requires memory
allocation/destruction in ROCR. Add destruction logic.
Change-Id: I68fe6b0a620ca743fe5850052ea0efa8bb7931c2
Add a view bit to avoid original resource destruction when parent
dependency doesn't exist with the image view cache
Change-Id: I8277afd575af8f29951c5d1a9f7d94d784251657
Make sure parent_ field is cleared for the internal image views.
The internal image views don't require dependencies tracking.
The issue appeard only when Navi10 pitch workaround was enabled.
Change-Id: I376d212750085a9391f8c32fc2979dcb5d93c89c
Blit manager requires an image view to reduce the amount
of copy kernels. Creation/destruction of a view in ROCr is
an expensive operation. Thus, runtime can cache views for fast access.
Change-Id: Ia67d775b481cc8326d91215ca22d4a73c1dddb59
let ROCr and addrlib decided whether a pitch is supported.
Then, check if we uses workaround.
Also improve image performance for Navi 1x in some cases.
Change-Id: If8bda46648b23c1dcfa26608ca3bb9cd89fef430
The heap must be cleared once per device, but ROCclr doesn't
create a queue per device in HIP. Hence, the clear operation will
be performed during the first queue creation.
Change-Id: I52ceb06d67d11cde6d019c5ab510059f426a9bfb
Pass active queue for transfers in the cache coherency layer.
That will allow to use device transfer queue only for
cases when active queue isn't available, because using device
transfer queue from another active queue may cause a deadlock
Change-Id: Ifbe7e0303b77dbf6eeda3939ffbc25a3df7472de
Current logic when creating a buffer view will end up going into the
allocation block. Even though no memory will be allocated, since
owner()->getSvmPtr() is already allocated, we'll still end up
calling updateFreeMemory().
Checking if we're creating a view, will skip the SVM allocation logic
and let us fall into the actual view creation logic. This won't end up
updating the free memory counter.
Change-Id: I1c260a9ef57895130b272ea1246e06e812b25b37
- Don't notify if the batch is empty, because that means
the current command was processed already.
- Disable pinning optimization to avoid a race condition on stall.
- TS marker submition requires extra AQL barrier
to track the status.
Change-Id: I17eff4ad12ac66cfe1bb44048bebb1891805279d
- Correct GSL path to report targets using the TargetID syntax.
- Correct GSL path to check compatibility of code objects when
loading.
- Add concept of an device isa and create a registery used by ROCm,
PAL and GSL.
- Support XNACK and SRAMECC target features consistently for PAL and ROCm.
- Correct logic for NullDevices and asserts to avoid memory coruption.
- Allow all NullDevices to be created for HIP.
- Numerous other code improvements.
Change-Id: I40abf3d2b22249c1492d1af5919665f8184f4e0e
kjayapra-amd
German Andryeyev
Ioannis Assiouras
Lang Yu
Alex Xie
Ajay
Sourabh Betigeri
Anusha GodavarthySurya
Julia Jiang
haoyuan2
Satyanvesh Dittakavi
Sarbojit Sarkar
pghafari
Saleel Kudchadker
Vladislav Sytchenko
Jason Tang
Ravi C Akkenapally
Tony Tye