Wykres commitów

135 Commity

Autor SHA1 Wiadomość Data
German Andryeyev d17108e8d0 SWDEV-303560 - Remove coarse grain setup by default
The original logic was left after initial testing when HMM
couldn't handle xnack properly

Change-Id: I0abf01805704171e931dfba8b6d95bfe87d5fab1
2021-10-05 17:20:59 -04:00
kjayapra-amd 3081f7ca53 SWDEV-295277 - Report max waves per cu from ROCr backend.
Change-Id: Ie170b26b53f1cc2da851034c96b21de38ce7b563
2021-10-05 12:38:44 -04:00
Tao Sang 10abe8ab37 SWDEV-305884 - Clear up codes
Fix a log typo error
Change-Id: I887ecbdcfe414c2119247228bdd1255b8308da1d
2021-10-04 18:11:32 -04:00
Jason Tang f212fc91ca SWDEV-1 - More 'delete' clean up
info_.extensions_ and settings_ are deleted at amd::Device()::~Device().

Change-Id: I06f240a42e5c131dbd4e61a759f905bcdf84b45a
2021-09-21 11:17:24 -04:00
German Andryeyev f116959b54 SWDEV-302383 - Get active state from device
The queue can be destroyed at the time the app will request
the event status. Hence just get the active state from the device.

Change-Id: I887ecb0cfe414c2119247228b0d1255b8308da1e
2021-09-14 19:01:44 -04:00
German Andryeyev d8a86e4870 SWDEV-282419 - Use HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE for unset
When unsetting runtime should use HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE
for the agent and not HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE

Change-Id: I3814802d1fb3b72c54e7566defafafed6b0d5cee
2021-09-13 15:05:20 -04:00
Jason Tang 73967c3b17 SWDEV-1 - Some 'delete' clean up
Change-Id: I02564f0f0e349375bde1471e9f82df268703367b
2021-09-09 12:12:40 -04:00
Saleel Kudchadker e29b9c00ee SWDEV-301667 - Kern arg placement
Add a env var ROC_USE_FGS_KERNARG to toggle kernel arg placement
By default its in Fine Grain Kernel arg segment for supported asics.

Change-Id: I3d57ed69a1a4db2b392b0438ead499f3ddca4716
2021-09-02 12:36:49 -04:00
Jason Tang 7f83bcdb45 SWDEV-1 - Disable OpenCL support for gfx8 in ROCm path
Change-Id: Ie1e0c0d6273edf6b734909447c2a08252cba305b
2021-08-31 12:48:47 -04:00
Satyanvesh Dittakavi 48c1b895c0 SWDEV-299491 - Update data index in GetSvmAttributes appropriately
Fixes Seg fault caused when the attribute hipMemRangeAttributeAccessedBy
is queried using hipMemRangeGetAttribute

Change-Id: I2ceb2267d89bfc31a55d9eae2685610c7ad89b1f
2021-08-26 13:36:35 -04:00
Satyanvesh Dittakavi b46ffd5fe0 SWDEV-274145 - Fix to return correct data when queried for hipMemRangeAttributeReadMostly attribute
Change-Id: I9041c974b61e7a9c8fbdc748a407bbd04c060876
2021-08-22 23:56:08 -07:00
German Andryeyev 992830bab7 SWDEV-295555 - Add SVM mode query
The new query MemRangeAttribute::CoherencyMode can return current
coherency mode for the provided memory region. Coherency mode can
be one of the following types: FineGrain, CoarseGrain and
Indeterminate

Change-Id: Ib66feeeb14f57a8b1cc731c65bb3d0276d297ff7
2021-08-22 23:56:08 -07:00
German Andryeyev 2babcfbdbb SWDEV-290384 - Enable active wait on CPU if HIP requested
Change-Id: Idea5adf7a4705cb999da6785e6229fe3200dce17
2021-08-22 23:56:08 -07:00
German Andryeyev ff15c0893e SWDEV-292018 - Switch to internal signals for markers
Add ref counting to ProfilingSignal class to track the last release.
If a signal was used in the marker, then don't reuse it,
but create a new one for internal usage.
Don't rely on HSA callback for the command status update if there
are no pending dispatches.

Change-Id: I19f14ed9d80acfe79993b343b2187635f8428a20
2021-08-22 23:56:07 -07:00
German Andryeyev e4dae85ade SWDEV-290495 - Add HSA_AMD_AGENT_INFO_SVM_DIRECT_HOST_ACCESS query
Change-Id: Ib18a53a9016eb5c5ffd51bf6835cba7299ec8421
2021-08-22 23:56:07 -07:00
agunashe d96481fb36 SWDEV-293742 - Update copyright end year VDI repo
Change-Id: I69d2fea4a7a43adf96ccea794270e4af991c5261
2021-08-22 23:56:07 -07:00
pvellien c11c02f2c7 SWDEV-285333 - Introduce Address sanitizer hostcall service
Change-Id: Id29aacd09d0a9934a027446c57c7095804e1a454
2021-08-22 23:56:07 -07:00
German Andryeyev ce8dad2ecc SWDEV-290160 - Switch to global HSA signals
Runtime can't assign internal HSA signals for HIP events, because
HIP application can destroy the HIP stream or signal reuse may
occur internally. Switch to global HSA signals for HIP events.

Change-Id: Ieaea2d6b039e492b2e7c5112782a8f4e601e50a1
2021-08-22 23:56:07 -07:00
Saleel Kudchadker 8e08880cc3 SWDEV-247372 - Add logging for debug
Change-Id: Id5a27034005a7deba37072d8a4c6f250104a96c8
2021-08-22 23:56:07 -07:00
Sourabh Betigeri b2a1dc26ba SWDEV-286446 - This patch enables stream operations on vega10, vega20, MI100 and MI200
Change-Id: I6f07036d8ee6e4c6b55196a13288f8107488d824
2021-08-22 23:56:07 -07:00
German Andryeyev 85c70a7495 SWDEV-284671 - Add HW event wait to improve hipDeviceSynchronize
If AMD event contains a reference to a HW event, then runtime
could check/wait for HW event. CPU status update will occur later
after HSA signal callback, but it's not important for the result.

Change-Id: I591391a953bbdba6a25ac07e2cd98aeb17cd4596
2021-08-22 23:56:07 -07:00
German Andryeyev 89b69638d1 SWDEV-240804 - Update ReadMostly attribute
Switch HSA_AMD_SVM_ATTRIB_READ_ONLY to
HSA_AMD_SVM_ATTRIB_READ_MOSTLY to match Cuda. The new attribute
was just exposed in ROCr/KFD.

Change-Id: I2ee522d33c347ba52a4e272d2cd7f67960490cf7
2021-08-22 23:56:07 -07:00
German Andryeyev a9a1e21445 SWDEV-240804 - Add coarse grain memory support
Add an extension to memory advise to disable cache coherency for
better performance

Change-Id: I283703d81d9c36ddfa2c8fffa15eef60e2195056
2021-08-22 23:56:07 -07:00
kjayapra-amd 1c49d8816c SWDEV-286346 - Implement Arena Memory Object for externally created memory.
Change-Id: I8530602d89edf83ad367c52167e48a1559ee1e18
2021-05-18 10:59:52 -04:00
Jason Tang ed923eb12e SWDEV-269983 - Re-enable OpenCL Offline Compilation in ROCr path
Change-Id: I160c56a6964219c56c85ebeb5f475be535c39022
2021-05-18 10:46:46 -04:00
German Andryeyev 9b3072ae12 SWDEV-240804 - Switch SVM attribute for the first alloc
Use HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE flag for the initial
allocation instead of HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE.

Change-Id: Ia52fe205563df1ea916dc2dc81e749e11c16f83d
2021-05-18 09:32:29 -04:00
German Andryeyev 3f7a6b01e3 SWDEV-240804 - Remove AMD_HMM_SUPPORT define
Use dynamic logic for HMM based on it's availability

Change-Id: I63751d94571d5af6eb57bef2cb0e071120bfa103
2021-05-14 17:41:06 -04:00
Ravi C Akkenapally 93ae30730a SWDEV-286446 - StreamOperations: Enable for all gfx9
Change-Id: I913a31c8bfdf1031d4cd491f1c689aa4df05c02c
2021-05-14 16:15:27 -04:00
Brian Sumner 6d09a83b2d SWDEV-285332 - move common context into parent
Change-Id: I99ceb62ad948e1fa9d1dcaa5ede98626cc95bea7
2021-05-09 09:18:39 -07:00
Satyanvesh Dittakavi 88fca7bf9e SWDEV-281062 - hipIpcOpenMemHandle should return the base ptr
hipIpcOpenMemHandle should return the device pointer which is
similar to the base ptr of the original allocation even if the offset
to the original pointer is passed to hipIpcGetMemHandle

Change-Id: I99c0553e8c67c15b5fed880b6a4c74bce39c3aee
2021-04-22 02:59:05 -04:00
Vladislav Sytchenko cbeb372e46 SWDEV-280473 - Remove HSAIL support from the ROCm backend
In adition to removing the HSAIL logic from the ROCm backend, guard all
of the HSAIL includes in the common layer behind the WITH_COMPILER_LIB
define. This is to avoid including HSAIL headers when building with
no support for it.

In common logic replace the use of the aclType enum with the new
Program::file_type_t enum. This is essentially a local copy of the HSAIL
enum to avoid including any HSAIL headers.

Change-Id: Ica0651d1b29dfccc255cc584eb82a5cb35e1b520
2021-04-12 14:55:06 -04:00
Saleel Kudchadker aa38af8c96 SWDEV-276120 - Remove support for barrier sync
ROC_BARRIER_SYNC will not work with direct dispatch.
Remove and cleanup.

Change-Id: I81368b2e65039477bd0343bb92708dab48867db6
2021-04-07 17:08:39 -04:00
Sarbojit Sarkar d8d6c4e55d SWDEV-280089 - nullptr was getting added into MemObj
Change-Id: Ica56126156198140a143182de3d93d86730cadf1
2021-04-06 23:41:50 -04:00
German Andryeyev 8c513407af SWDEV-278346 - Replace assert with LogWarning()
ROCr returns some unexpected values and for now just return
invalid device back to the app

Change-Id: Ia6fb709ed2dc77d77bd5d64de80b41b3720bed76
2021-03-25 10:19:33 -04:00
German Andryeyev e9c484d1ce SWDEV-274145 - process ACCESS_QUERY for all devices
HIP requires to return AccessedBy query for all device, but ROCr
can process one per query. Hence send the queries for all
available devices and then accumulate the results in runtime.

Change-Id: I082f9adb8e31c775a8ad1bf7a5af37440ef4bd16
2021-03-08 14:19:13 -05:00
Jason Tang c13f9df42a SWDEV-1 - Change file mode back to 644
Change-Id: I433740d65c8f648e346107f6d8fa57d69463b713
2021-03-05 10:17:58 -05:00
kjayapra-amd 95e3a6d985 SWDEV-259566 - Adding support to retrieve handle for offsetted pointer.
Change-Id: I4a700c31a9ab481c4ea43923af57e83247555ab0
2021-03-04 12:28:59 -05:00
German Andryeyev fbde61de7f SWDEV-274199 - Enable SVM tracking
ROCr/KFD doesn't validate memory pointers. Enable validation inside
ROCclr, using SVM tracking mechanism.

Change-Id: I581e32ff37187f9ed8d9a302e8fd9f6ca935bdd7
2021-03-03 13:18:56 -05:00
Ravi C Akkenapally e94d482c8f SWDEV-179105 - Stream Operations: Add feature querying support
Change-Id: I01cb85223b83f3655e5e21ad16639da406e5cd3e
2021-03-02 11:02:15 -08:00
kjayapra-amd a7abe44436 SWDEV-270013 - Assign Kern_args segment only for gfx90a.
Change-Id: Icc890041eb27800cb78ef9e3d7bbe02658f53821
2021-03-02 11:07:37 -05:00
Vladislav Sytchenko c93f66a5ec SWDEV-270013 - Fix uninitialized variable warning
Change-Id: Ic4c8090e94e82798c294ac4532ca20efbc5a3a54
2021-02-23 11:49:28 -05:00
Vladislav Sytchenko 671778bdd3 SWDEV-232428 - Push hostcall implementation to the device layer
This change unifies the hostcall implementation for all the backends,
by pushing the common logic to the device layer. This is done by
replacing the use of hsa_signal_t with device::Signal (a light wrapper
around it).

Change-Id: I7b6fca7930b5a0b199da5d85e2e048354cc04e7b
2021-02-16 17:19:57 -05:00
Jason Tang c65be06c4c SWDEV-265304 - Disable GFX8 in LinuxPro ROCr build
Change-Id: Ia26bb025a133a4acb255a539a45668975019cc6e
2021-02-16 13:32:47 -05:00
Ravi C Akkenapally 0a5f9a3b10 SWDEV-179105 - Stream Operations: Add support for Wait and Write
Change-Id: Ibffa1d6d573826b64763da280074a77271d66808
2021-02-15 17:02:38 -08:00
kjayapra-amd 2df099df9e SWDEV-270013 - Allocate kernel_arguments from kern_arg & finegrain pool instead of coarse grain.
Change-Id: Id4c6977934fdd6ef2311f6e75593801f1e51983c
2021-02-15 18:20:08 -05:00
Payam a2e0b0495c SWDEV-257937 - Updated fix for ROC_BARRIER_SYNC=0
Change-Id: I7e28e541b654db57fb0890d7dbb7519cfb2d93db
2021-02-11 14:01:45 -05:00
German Andryeyev fb142e7b2f SWDEV-271806 - Disable pinning for views.
Only parent object should pin system memory

Change-Id: Ic9a0a34e3aff2263501c564c3cebd33f4f7e2455
2021-02-11 13:05:58 -05:00
Rahul Garg df0b14ff47 SWDEV-271182 - Fix HdpMemFlushCntl and HdpRegFlushCntl
Change-Id: Ib690b475c2c4514c862ded5fc2bdd1049e27bd46
2021-02-10 11:40:35 -05:00
German Andryeyev 6966d8098e SWDEV-269654 - Fix HIP stream busy query
- Avoid GPU wait on the marker submission and update the command
batch after HSA signal callback upon HSA barrier completion.

Change-Id: I5c1c97212aefc2ae4b99aa9e2a81627ee9a38c1c
2021-02-09 12:57:12 -05:00
kjayapra-amd 85fafb0561 SWDEV-270013 - Adding code to differentiate between kern_arg + fine_grain and fine_grain segment of system memory.
Change-Id: Id0404b2dab8561946ad0a90a77030582f7e021a4
2021-01-28 09:48:17 -05:00