68344576d3
SWDEV-460242 - Add system memory suballocator
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Switch commands creation to the new suballocator to avoid
frequent expensive OS calls
Change-Id: I3597c811820e577c15708bad8b8a41aa53acc400
[ROCm/clr commit: 5b0bfdcbad
2024-05-28 06:28:17 +00:00
3ca0dbc4d7
SWDEV-460151 - Enabling gfx12 in HIP runtime.
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Change-Id: I374ea7c3119b0c61f9846a862c4a448ddb179748
[ROCm/clr commit: f5d0ee650b
2024-05-28 06:28:07 +00:00
0812cc34a6
SWDEV-451945 - Remove ShouldLoadPlatform function
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Change-Id: Iabb4071bb77201576bc2c0488a04f4fa188815df
[ROCm/clr commit: 2eb30376ba
2024-05-06 10:42:59 -04:00
588e870000
SWDEV-301667 - Pass reference to kernel name
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Change-Id: I21abe109ddfabfe7640bf78a96c81a1317d31952
[ROCm/clr commit: 4a9d24a211
2024-05-05 16:38:20 -04:00
7c56ed2526
SWDEV-460091 - Handle cases where inline variables are included in multiple translation unit.
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Change-Id: I92179ad198abbdaf5aec9c3c4ba76eeb6b0cc761
[ROCm/clr commit: 68ddd8f3a0
2024-05-03 15:52:28 -04:00
f30be8996b
SWDEV-433371 - Build needs comgr >= 2.8
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Unbundle compressed code objects needs comgr 2.8 or higher
Change-Id: I23942d2038e19b02c3ea5d3c9c1fe5367db87136
[ROCm/clr commit: 1bd8b4eaf5
2024-05-03 09:34:49 +00:00
a21913a0bd
SWDEV-451594 - Change device kernel args to use HDP flush by default
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The Readback and Avoid HDP Flush memory ordering workaround is
used as a fallback solution only when HDP flush register is invalid
Change-Id: Ic284eba1f95ed22b0270d3abeb904fb902015b1a
[ROCm/clr commit: 6cb7b6ec6b
2024-05-02 19:35:13 +00:00
c0ee0ffa1c
SWDEV-433371 - use comgr to unbundle code objects
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1.Make runtime use comgr to unbundle code objects
2.Support compressed/uncompressed modes
3.Remove HIP_USE_RUNTIME_UNBUNDLER and
HIPRTC_USE_RUNTIME_UNBUNDLER to simplify logics
4.Add comgr wrapper for
amd_comgr_action_info_set_bundle_entry_ids()
Change-Id: Ic41b1ad1b64cca1e31986437983a5146d52a7329
[ROCm/clr commit: e53df57ffe
2024-05-01 16:09:12 -04:00
d5b57de7e5
SWDEV-449327 - Adding CONTRIBUTING.md in clr repos
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Change-Id: I3601373f680aa4bff0075f4b3b9e885e54b4600d
[ROCm/clr commit: 996c16ad0a
2024-05-01 11:48:29 -04:00
35ab01f7de
[SWDEV-442583] - Fix hipLaunchCooperativeKernel API error codes
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Change-Id: Id3cb4b58b9efd3aceec4377d4d1d3a053c50333e
[ROCm/clr commit: 59051ed3af
2024-05-01 11:36:59 -04:00
1e22a14b1b
SWDEV-455586 - create ocltst ASAN test instrumented pkg
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Change-Id: I820cacd75a36363d1387e2e881c96937281bc265
[ROCm/clr commit: feaef7f54e
2024-04-30 17:50:15 -04:00
0cf1f056a7
SWDEV 301667 - Fix Debug dot print for graphs
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- Fix possible buffer overflow for long kernel names
Change-Id: I3c51669de7ff242d03f9210ee045b6d5e7ac274a
[ROCm/clr commit: f1ef05b121
2024-04-30 12:26:10 -04:00
40bd47ba42
SWDEV-301667 - Add LOG_TS mask
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- Add LOG_TS mask for printing signal times
- Read raw ticks from signals
Change-Id: Ibdd0bf06c790729f6c65083a4784c97a3c3219e0
[ROCm/clr commit: 948ca5a931
2024-04-30 12:24:48 -04:00
ab70925687
SWDEV-456279 - Adding new hip flag to access contiguous memory and pass the flag to HSA API.
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Change-Id: I1bafeaa3096395c729723af958d609bc41e7845c
[ROCm/clr commit: 1d48f2a1ab
2024-04-30 05:25:38 -04:00
af5aaa806f
SWDEV-459583 - Update codeownder in clr repos
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Change-Id: Ief73138faed0af70b90186db5bde6689e0a83f88
[ROCm/clr commit: 08889f438f
2024-04-29 19:00:20 -04:00
daceede8a7
SWDEV-311271 - Enable mempools under Linux
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Change-Id: I7fda94e61121f9d3a30f4ad185b8a97712922f3c
[ROCm/clr commit: 7a371503b2
2024-04-29 18:06:34 -04:00
154a113a88
SWDEV-413997 - Changes to use GlobalContext in views.
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Change-Id: I1f8411eae9ed49632667e244a25f223fed92c720
[ROCm/clr commit: 0e1a0572e6
2024-04-29 16:41:39 -04:00
fd08a5b6e3
SWDEV-458516 - Add support for external CI builds using Azure Pipelines
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Change-Id: Iedd6290a813d6e43a4350709484f78e05b08adc8
[ROCm/clr commit: d7d1e013d0
2024-04-29 15:31:26 -04:00
8afb040f8b
SWDEV-451004 - Remove .bat files from hip-dev/devel package
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The .bat file will not be removed from windows pacakge.
Also used cmake install(PROGRAMS …), which will set the correct permission rather than hard coding the permission
Change-Id: I8b57778b59f70e01de949be2ea353b67eec70d2f
[ROCm/clr commit: 9e74f6de8a
2024-04-29 14:13:26 -04:00
d49fa8d06b
SWDEV-413997 - Handling cases where multiple phys_mem is mapped into a single virtual address.
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Change-Id: Ie678e607a64f2e5c35a10b9083185f041c5527ac
[ROCm/clr commit: 49b4aef8c9
2024-04-28 08:28:12 -04:00
b1c0f73229
SWDEV-353281 - Corret VA unmap
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Make sure graph mempool unmaps VA on release
Change-Id: Id3f1bd8d0115b533ae60aa5ba3676b8bf7e5b961
[ROCm/clr commit: 5c1804aa14
2024-04-26 09:37:01 -04:00
32e94ef1cc
SWDEV-457859 - Initialize isWGPMode_ in WorkGroupInfo
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Change-Id: Ie3f3c0bcea84368c1b0607fd52b4bc7cae41c512
[ROCm/clr commit: cffff4e1cb
2024-04-25 16:36:55 -04:00
15b8dc404c
SWDEV-420016 - Add more driver side graph APIs
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Signed-off-by: shadi <shadi.dashmiz@amd.com >
Change-Id: Iff3ee7dcbcd24836f227fdc9bd5ff4b554ac914f
[ROCm/clr commit: f2b01782ac
2024-04-25 12:50:43 -04:00
08e7942cf8
SWDEV-447691 - Correct handle type for DX12 semaphore
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Change-Id: Id23882286cb2a0d0472964ffc501ab27b7dc7f00
[ROCm/clr commit: 9fdddb7c5d
2024-04-25 11:24:56 -04:00
b052e90ea8
SWDEV-451099 - Added include for __half type definitions for non-HIP code on windows
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Change-Id: Id80cef5a36db8707276de052cbaf73b6826d222f
[ROCm/clr commit: 2841aab017
2024-04-24 15:31:31 -04:00
d1507ad475
SWDEV-353281 - Align VA size
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Lower layer ignores alignment
Change-Id: If16df951ecefddc804a6effe013058afc595d30f
[ROCm/clr commit: 5c23440199
2024-04-24 15:22:20 -04:00
a2b2a6752d
457619 - Fixed the broken link to build HIP instructions
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Change-Id: Ica87b4ab511d26e0372502f069afc0e3baaa3256
[ROCm/clr commit: 1761f1b7f5
2024-04-24 11:41:07 -04:00
85a372e4eb
[SWDEV-454661][SWDEV-454653] - GraphExecMemcpyNodeSetParam to return error on memcpy direction change
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Change-Id: I2c8f5ea394caeaaa6895003e63cd62a052c491f8
[ROCm/clr commit: 880963346d
2024-04-23 12:56:30 -04:00
99e538f29e
Switch luxmark to lightning compiler for all ASICs
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Change-Id: Idcd37628a2167f0bd2db2a83132a1862cbd051b0
[ROCm/clr commit: 5a715ed160
2024-04-23 10:00:39 -04:00
f613be3d81
SWDEV-413997 - Cleanup fixes for Virtual Memory Management.
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Change-Id: I9a4a4d9087b5daf15e3ba31e786d34db431212a1
[ROCm/clr commit: 74ffc5f0d5
2024-04-22 10:58:06 -04:00
a2ffb2ad40
SWDEV-440746 - Release last command on terminate
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Change-Id: Ib6a9b8fc9a8692eb17b39b854cefd92c6b59733f
[ROCm/clr commit: 0ccdb3e160
2024-04-22 09:57:38 -04:00
74d80fb509
SWDEV-440746 - Remove obsolete code
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The "optimized" version of memcpy is outdated and
was used in win32 only.
Change-Id: I7f2e0e9051e37cec95438266824b5b0025c324c6
[ROCm/clr commit: 7448113cfc
2024-04-22 09:56:42 -04:00
2335c92a1a
SWDEV-455041 - Continue processing fat binary even if other code object bundle processing fail.
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Change-Id: Iea553ab0265c08341f915644075ce2b6ed9b3200
[ROCm/clr commit: 863c56262e
2024-04-20 14:25:49 -04:00
cb1f02f4f7
SWDEV-453180 - Add UUID support for HIP_VISIBLE_DEVICES on Windows
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- UUID needs to be specified in the format GPU-<body>, <body> encodes UUID as a 16 chars
- Convert set UUID in HIP_VISIBLE_DEVICES to device index internally
- Then use existing device index logic for HIP_VISIBLE_DEVICES
Change-Id: I654f492a49cd4d7a9b7339360ab558165240caa5
[ROCm/clr commit: fb217fa9e0
2024-04-20 02:39:19 -04:00
02d949ec38
SWDEV-440746 - Wait for signal before release
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Change-Id: I9e2aefdbcbba153c7f1080d80aab7a345eaf1eb4
[ROCm/clr commit: 329ba271fa
2024-04-19 18:33:28 -04:00
00fb29aab6
SWDEV-353281 - Reuse timestamp on memory reuse
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Mempool may reuse memory without a wait. Hence, the timestamp has
to be preserved and can't be destroyed.
Change-Id: I6f095f44afa69887a4b7aeb3b329804aedd96f3e
[ROCm/clr commit: ffb516db3e
2024-04-19 18:00:29 -04:00
7eaba0bd33
SWDEV-440746 - Don't set CL_SUBMITTED twice
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Change-Id: I9ba34454f7487d6bc0d398b322a147cbac6c6443
[ROCm/clr commit: fd81490bb8
2024-04-19 17:36:51 -04:00
2e58154d80
SWDEV-446610 - Attribute HIP_POINTER_ATTRIBUTE_SYNC_MEMOPS should return the correct value
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Change-Id: Ieced2ee61bba28f2d1df96893a661287b0a5c7b7
[ROCm/clr commit: 8f7acbdadb
2024-04-19 14:40:09 -04:00
2f430138c5
SWDEV-451594 - Implement Readback and Avoid HDP Flush workaround for device kernel args
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Change-Id: I6d41a089a17f55306e7ff402588a1e831b20a7a7
[ROCm/clr commit: bf74ef4025
2024-04-19 09:29:20 -04:00
c7022ad6ce
SWDEV-455869 - Revert "SWDEV-410751 - Consider null amd::memory is invalid."
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This reverts commit 60a3077ed4e829ef68e4
2024-04-19 00:54:26 -04:00
71aa6ff3a0
SWDEV-413997 - VMM IPC implementation for Linux.
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Change-Id: Icfeb83ca51e96be35abb67a94d6e3e1a1ca5a934
[ROCm/clr commit: 56ebf5157a
2024-04-18 11:28:13 -04:00
b77908a819
SWDEV-450053 - Handle MemcpyNodeSetParamsTo/FromSymbol negative parameters
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For all windows allocation on SVM memory tagged with flag ROCCLR_MEM_INTERPROCESS.
hipHostMalloc validation is based on flag. So remove ROCCLR_MEM_INTERPROCESS before check.
Change-Id: I823bbf228d9a4a9acb4abffc01ac6b3f544c6e12
[ROCm/clr commit: 8179fa98a2
2024-04-18 05:39:35 -04:00
3dae883e73
SWDEV-453535 - Capture hipMemset3DAsync.
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Change-Id: I517c2557573db258b3e3e353f02f6a56652b0fde
[ROCm/clr commit: 12e0bdcd32
2024-04-18 00:05:45 -04:00
24bb38acb8
SWDEV-455346 - End wait if HostcallListener terminates.
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Change-Id: I21ec8eadb189147c579ec65acf68de40d604686b
[ROCm/clr commit: 8942939fac
2024-04-18 00:04:00 -04:00
562f3ef098
SWDEV-440746 - Fix the hostcall buffer creation
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Avoid a deadlock on the host call buffer creation. Since the buffer will be
allocated in the queue thread, then use direct device memory allocation
skipping the global context lock.
Change-Id: I09b55ee03bb42ab5d320c152b52a8c842c5fdcc1
[ROCm/clr commit: 62559a6e5a
2024-04-17 12:37:23 -04:00
d2b2b2c5fa
SWDEV-441603 - Correct dst device
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Signed-off-by: sdashmiz <shadi.dashmiz@amd.com >
Change-Id: Ie60aa598dd73df66cdf02c1d96daf2dfccba7a59
[ROCm/clr commit: d511e57257
2024-04-17 09:21:06 -04:00
5a7b0c50ad
SWDEV-379007 - fix bool check for fp8_fnuz
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for fnuz nums zero val is 0x00, -0 i.e. 0x80 would be a NaN
Change-Id: Ibdc4fb4b9fb307b5952434f08d45a8ddd6262db8
[ROCm/clr commit: d7b0d78fad
2024-04-17 05:31:21 -04:00
c44b565943
SWDEV-454959 - ignore the upper half of the mask in wave32 mode
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Change-Id: If027dd8cbe5cbe142fff353cb72c16f08e9aea8e
[ROCm/clr commit: 03562a2547
2024-04-17 10:12:57 +05:30
e3266682d0
SWDEV-455699 - removing HW_REG_TRAPSTS for gfx12
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Change-Id: I5f8b030eefdb37d3d51da3e135e5aa0f18ad9018
[ROCm/clr commit: 5ddca5854c
2024-04-16 19:46:21 -04:00
80f02a1534
SWDEV-379007 - use avx instruction for bf16 cvt
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AMD CPUs have had avx512_bf16 support for quite some time now (from
consumer Ryzen 7000 series to enterprise grade CPUs). This
patch should allow users to use the hardware bf16 unit when running the
__host__ variants of the function. This can be enabled via `hipcc ...
-mavx512vl -mavx512bf16`.
Change-Id: I67c377afc95ddfe8d45a048dce078a247d4a1878
[ROCm/clr commit: 49349f168c
2024-04-16 18:35:08 -04:00
German Andryeyev
kjayapra-amd
Alex Xie
Saleel Kudchadker
Maneesh Gupta
Ioannis Assiouras
taosang2
Julia Jiang
Rahul Manocha
Jaydeep Patel
amd-jmacaran
Ranjith Ramakrishnan
shadi
Rahul Manocha
Konstantin Zhuravlyov
Rakesh Roy
Satyanvesh Dittakavi
Anusha GodavarthySurya
Jatin Chaudhary
Sameer Sahasrabuddhe
pghafari