Extra CPU read back will be performed before every submission to make sure
previous writes over PCIE reached GPU. HDP flush is done by CP.
Change-Id: I402d28ca26c8cee4a3920feb3599af8c285d0889
[ROCm/clr commit: cfc07c88ee]
Persistent memory should use direct access for write map and
indirect for read map.
Change-Id: I9fc84836d60088b24012ed25f7ef8c16e33796a3
[ROCm/clr commit: c8b3253a24]
- Add the new fillBuffer kernel, which allows to launch a limited
number of workgroups for memory fill operation
- Switch fill memory to 16 bytes write by default
- Allow to limit the workgroups with DEBUG_CLR_LIMIT_BLIT_WG
Change-Id: Ibad1822f2d42b2fc71bcfc1917c31409c0623e8e
[ROCm/clr commit: f1dc81f427]
Add support of HIP_FORCE_DEV_KERNARG under PAL.
Fix persistent memory detection for a resource view.
Change-Id: Ifb7db2db14e0c2205a9661cfa53887ec61ab26a4
[ROCm/clr commit: 5f297d75d9]
This patch did not consider the dicussions in SWDEV-270908
> "we found that in GeekBench5, forcing Wave64 instead of the default
> Wave32 compute policy yields big gains in every subtest except one"
This reverts commit 10e2958197.
Change-Id: Ice1728585b9d1b2c1b36a06cfa0b8c47cb2bfa49
[ROCm/clr commit: 06dcaae619]
This reverts commit dfa7790030.
Reason for revert: Deferred to a future release.
Change-Id: Ia66c37f0ab9734dee73c930d10d7469d5fd57254
[ROCm/clr commit: 5dc104b3ea]
Pinned copy can cause big performance drops, because slow pinning under Windows.
Use up to 128MB for staging transfers. Change staging buffer size to 4MB.
Linux path should still have the old defaults.
Change-Id: I954edceb3ec89e8e670be116aa2d0a9564c8b11c
[ROCm/clr commit: 79d12df147]
Sync between compute and SDMA engines can be very expensive under Windows.
Use CP DMA for tiny transfers (< 1KiB) to avoid syncs and improve performance.
Change-Id: I9db39a2199f7b9e337ed08fd36d9cbc150502f1f
[ROCm/clr commit: 473621c008]
assert statement were hit silently in Release builds like SWDEV-353548.
Issue only seen in Debug builds
Change-Id: I9f7177806c854d64fcf986e9f6092076d8a05f23
[ROCm/clr commit: 040c416cb1]
- Correct GSL path to report targets using the TargetID syntax.
- Correct GSL path to check compatibility of code objects when
loading.
- Add concept of an device isa and create a registery used by ROCm,
PAL and GSL.
- Support XNACK and SRAMECC target features consistently for PAL and ROCm.
- Correct logic for NullDevices and asserts to avoid memory coruption.
- Allow all NullDevices to be created for HIP.
- Numerous other code improvements.
Change-Id: I40abf3d2b22249c1492d1af5919665f8184f4e0e
[ROCm/clr commit: c7e8d91e14]
Anusha GodavarthySurya
German
Juan Manuel MARTINEZ CAAMAÑO
Todd tiantuo Li
Konstantin Zhuravlyov
Xie,AlexBin
Maneesh Gupta
Tao Sang
kjayapra-amd
Ajay
pghafari
haoyuan2
Vladislav Sytchenko
Sourabh Betigeri
Julia Jiang
Jason Tang
Tony Tye
Laurent Morichetti