Ioannis Assiouras
775dc204aa
SWDEV-463865 - changed device,roc and pal namespaces to be nested under amd
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Change-Id: Icad342843c039c634e249a13a7aa31400730b1dd
2024-06-07 12:23:06 -04:00
Sourabh Betigeri
a9f05e22db
Revert "SWDEV-301667 - Disable HostBlit copy for HIP"
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This reverts commit 5447cf8872 .
Reason for revert: SWDEV-455075, SWDEV-461507 - This change forces to
use ROCr's copy path. Reintroducing hostBlit copy path for
host-to-host copies.
Change-Id: Ic3c45b49e481c9dcdaa7611f61071778790b7e6c
2024-05-28 06:31:10 +00:00
German Andryeyev
f1dc81f427
SWDEV-432174 - Change the fillBuffer kernel
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- Add the new fillBuffer kernel, which allows to launch a limited
number of workgroups for memory fill operation
- Switch fill memory to 16 bytes write by default
- Allow to limit the workgroups with DEBUG_CLR_LIMIT_BLIT_WG
Change-Id: Ibad1822f2d42b2fc71bcfc1917c31409c0623e8e
2023-11-16 14:25:55 -04:00
Saleel Kudchadker
5447cf8872
SWDEV-301667 - Disable HostBlit copy for HIP
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Change-Id: I46333ff42e8c1d402ece97e3ead7b539a27c3f82
2023-07-17 17:49:11 -04:00
Anusha GodavarthySurya
274f2de391
SWDEV-364576 - initialize device malloc heap state using blit kernel
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Change-Id: I5d0172aff7d2c04b322a4d828b8a2b438158b80f
2023-01-07 06:53:53 +00:00
Ioannis Assiouras
72b45e2a1f
SWDEV-369581 - Convey copy API metadata to ROCclr
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Change-Id: I569462d6d268700d419510255e201bf7d80d6714
2022-12-09 00:27:15 -05:00
Ajay
373a7d1195
SWDEV-347670 - GPU StreamWait and StreamWrite support in Windows PAL backend
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Change-Id: Ic4881305b6332e217f3d3127dce7e9d9d0a7df11
2022-09-15 13:57:40 -04:00
German Andryeyev
07c1b9a998
SWDEV-336024 - Clear device heap to 0
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This reverts commit 04bfd93569 .
Reason for revert: Fix regressions
Change-Id: I7d883e1c3cbd27bb64b581ec800243ad7dfe24fd
2022-05-19 09:10:08 -04:00
German Andryeyev
04bfd93569
SWDEV-336024 - Clear device heap to 0
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The heap must be cleared once per device, but ROCclr doesn't
create a queue per device in HIP. Hence, the clear operation will
be performed during the first queue creation.
Change-Id: I52ceb06d67d11cde6d019c5ab510059f426a9bfb
2022-05-11 11:03:56 -04:00
kjayapra-amd
7fb80a027a
SWDEV-305527 - Changes to handle memset blit kernel that takes width, height and depth. This also fixes SWDEV-317261.
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Change-Id: Ic85f63a95d9d8f48884fc8c7fd95cbb496dfbbca
2022-03-31 09:02:33 -04:00
kjayapra-amd
2e9bc8f793
SWDEV-312822 - Revert "SWDEV-310187 - Change flag to keep track of aligned sizes instead of expanded patterns."
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This reverts commit 8307886644 .
Change-Id: I022c2a8375f9929e9723cec66e1e0b960263fc39
2021-11-28 23:39:40 -05:00
kjayapra-amd
8307886644
SWDEV-310187 - Change flag to keep track of aligned sizes instead of expanded patterns.
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Change-Id: I763feda8688bb1b7b11033a2a8cba0f69f07167d
2021-11-19 10:32:40 -05:00
kjayapra-amd
4c8b32b13c
SWDEV-232903 - Change pattern64 to uint64_t from size_t to handle 32 bit machines.
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Change-Id: I423cd14d145556544563027931562d7b8bf9442d
2021-10-18 14:31:09 -04:00
kjayapra-amd
88ed58735d
SWDEV-232903 - Move hipmemset Dword optimization to ROCclr.
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Change-Id: I3eae61720cbc6364f1aaac4865bfd8b6ded08097
2021-10-13 11:32:15 -04:00
agunashe
d96481fb36
SWDEV-293742 - Update copyright end year VDI repo
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Change-Id: I69d2fea4a7a43adf96ccea794270e4af991c5261
2021-08-22 23:56:07 -07:00
Ravi C Akkenapally
0a5f9a3b10
SWDEV-179105 - Stream Operations: Add support for Wait and Write
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Change-Id: Ibffa1d6d573826b64763da280074a77271d66808
2021-02-15 17:02:38 -08:00
Laurent Morichetti
d9d9c69399
Replace cl_* integral types with standard types.
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cl_bool -> bool
cl_int -> int32_t
cl_uint -> uint32_t
cl_long -> int64_t
cl_ulong -> uint64_t
cl_float -> float
cl_double -> double
cl_bitfield -> uint64_t
Change-Id: I840c8993b55f98f5b745d21e27f5f28233647a58
2020-02-12 13:16:06 -08:00
Laurent Morichetti
b4c6143a2f
Update copyright info
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Change-Id: Ia4f9ff0f5f873b4223a8cca154188bb0d2f1abba
2020-02-04 09:26:14 -08:00
Laurent Morichetti
20c7173849
Merge branch 'origin/pghafari/vdi-prototype' into lmoriche/amd-master
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Change-Id: Id3b833d405596735becb3346f3b08c6da57033fe
2020-01-30 20:12:13 -08:00