775dc204aa
SWDEV-463865 - changed device,roc and pal namespaces to be nested under amd
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Change-Id: Icad342843c039c634e249a13a7aa31400730b1dd
2024-06-07 12:23:06 -04:00
7de7da4016
SWDEV-455254 - Reduce blit kernels signature
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Remove offset from blit kernels, since it can be applied in setup.
Change-Id: I06b585068d68a0ee8e125ddf46a36fccb372f30d
2024-04-12 14:45:55 -04:00
e643406caa
SWDEV-347670 - StreamWait and StreamWrite on Windows
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__amd_streamOpsWrite blitkernel in device-libs has only 3 args.
so getting rid of the 4th unused arg (sizeBytes)
Change-Id: I81cc1107f8b424bf58558c93a2495a1b878aef91
2024-02-26 22:45:10 -05:00
ed4e1fec98
SWDEV-434298 - Change copy buffer kernel
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The new copy kernel can limit the number of launched workgoups.
It can copy in chunks of 16 bytes or 4 bytes.
Workgoup size is increased to 512 or 1024
Change-Id: Ic3fefa2d5bda6afebd1acc4d41ad310b138af6df
2023-11-28 16:56:30 -05:00
f1dc81f427
SWDEV-432174 - Change the fillBuffer kernel
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- Add the new fillBuffer kernel, which allows to launch a limited
number of workgroups for memory fill operation
- Switch fill memory to 16 bytes write by default
- Allow to limit the workgroups with DEBUG_CLR_LIMIT_BLIT_WG
Change-Id: Ibad1822f2d42b2fc71bcfc1917c31409c0623e8e
2023-11-16 14:25:55 -04:00
6a8bc3c718
SWDEV-419688 - Do not run GWS init kernel for targets > gfx12 and MI300.
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Change-Id: I8e7441268978be71ab8a5a33e7f8bcf69660e500
(cherry picked from commit 36d37ef614909c0f215512aac0c133408d787080)
2023-10-05 14:57:56 -04:00
7912f3af89
SWDEV-409299 - Vega clinfo is not working
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Change-Id: Ia48bc6f130bd102dff210b105de6f9c02ebbe012
2023-07-10 09:53:50 -04:00
d6946ffcbc
SWDEV-406687 - combining rocblitcl and palblitcl blit kernel defs
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Change-Id: Ia312d73584a03491e8d574f424295b64df6de174
2023-06-23 18:38:36 -04:00
7fb80a027a
SWDEV-305527 - Changes to handle memset blit kernel that takes width, height and depth. This also fixes SWDEV-317261.
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Change-Id: Ic85f63a95d9d8f48884fc8c7fd95cbb496dfbbca
2022-03-31 09:02:33 -04:00
ef3d6f7b28
SWDEV-308644 - update blit kernel setup in rocm
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Change-Id: Iaa9ff97b3ed7d379189c359696be932a83cf203c
2021-11-15 13:28:07 -05:00
7413b7f79b
SWDEV-294420 - Ignore Image blit kernels if image instructions are not supported.
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Change-Id: I145172672b0b032aa722649b0c4ca9267e3e5c85
2021-10-05 18:12:44 -04:00
cbb8d82bdb
SWDEV-292525 - [vdi] Path to streamOps shaders
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Implementation to use a blit kernel to perform
a hipStreamWait/write instead of an AQL packet.
Change-Id: I462671ed5cec37144dfe97ff66439249196117c1
2021-09-27 13:59:35 -04:00
21ba34d0fe
SWDEV-297448 - Add 64bit and 16bit write support
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For the fillBuffer shader, if there are two 32bit writes to a MMIO
register, it can get dropped. It has to be a single 64bit write.
Add optimization to fillBuffer to write 64bit and 16bit writes.
Change-Id: I3aa78e027898f8ae01e9c8f09004615673720c2b
2021-09-08 12:30:04 -04:00
d96481fb36
SWDEV-293742 - Update copyright end year VDI repo
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Change-Id: I69d2fea4a7a43adf96ccea794270e4af991c5261
2021-08-22 23:56:07 -07:00
093f7fa3ca
SWDEV-244600 - HIP BLIT code object needs to have reserved symbol name
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Change-Id: I8401fea5eab71c0f7414eec0666066d9553a6622
2020-08-06 01:14:06 -04:00
b4c6143a2f
Update copyright info
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Change-Id: Ia4f9ff0f5f873b4223a8cca154188bb0d2f1abba
2020-02-04 09:26:14 -08:00
20c7173849
Merge branch 'origin/pghafari/vdi-prototype' into lmoriche/amd-master
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Change-Id: Id3b833d405596735becb3346f3b08c6da57033fe
2020-01-30 20:12:13 -08:00
Ioannis Assiouras
German Andryeyev
Ajay
kjayapra-amd
Alex Xie
Julia Jiang
Sourabh
Saleel Kudchadker
Anusha Godavarthy Surya
Laurent Morichetti