Some chunk memory are not guaranteed to be resident during
initial allocation. Use CPDMA to force resident.
Change-Id: If1a2da3e75f136caaa4c7a29d8f604d6af2639fa
Runtime can't assign internal HSA signals for HIP events, because
HIP application can destroy the HIP stream or signal reuse may
occur internally. Switch to global HSA signals for HIP events.
Change-Id: Ieaea2d6b039e492b2e7c5112782a8f4e601e50a1
Add lock protection for signal processing
If signal is reused, then disable reference to it from HIP
Increase the pool signal size to 32
Change-Id: I7d529b35910f83ce577c9eca6d3386759611ccc0
- Create an env var ROC_ACTIVE_WAIT_TIMEOUT to set active wait timeout
- Record profiling informaion if marker_ts_ property is valid.
Change-Id: If0d8aec8d9b0715027cf0f7c3dc8a4c722a6bae6
If AMD event contains a reference to a HW event, then runtime
could check/wait for HW event. CPU status update will occur later
after HSA signal callback, but it's not important for the result.
Change-Id: I591391a953bbdba6a25ac07e2cd98aeb17cd4596
Revert back to using the Raven (gfx902) target ID for Raven 2 (gfx909).
This is due to the HSAIL compiler not supporting gfx909.
In theory there should be no issue with running Raven isa on Raven 2.
Change-Id: I425edebc99075799eda5522fad231b8fb3184873
Switch HSA_AMD_SVM_ATTRIB_READ_ONLY to
HSA_AMD_SVM_ATTRIB_READ_MOSTLY to match Cuda. The new attribute
was just exposed in ROCr/KFD.
Change-Id: I2ee522d33c347ba52a4e272d2cd7f67960490cf7
All KMD/asic_reg/UGL headers are located under the drivers folder. No
need for the AMD_UGL_PATH variable as it essentially is
${AMD_DRIVERS_PATH}/ugl.
Change-Id: I070d737d50f2096493b3e75ef9b9e824cb19d048
With HIP API callback runtime has to stall the queue until the
callback is done. Rocclr will introduce SW blocking HSA signal,
which will be released after the callback is done.
Change-Id: I6411f3efab31b468e3b87ebb5c8d155e116b613d
This change refactors the current ROCclr cmake build to accomodate a
more modular approach. This allows easier support for multiple compiler
and/or multiple runtime backends.
Currently supported compilers:
HSAIL - enabled by ROCCLR_ENABLE_HSAIL (defaults to OFF)
LC - enabled by ROCCLR_ENABLE_LC (defaults to ON)
Currently supported runtimes:
HSA - enabled by ROCCLR_ENABLE_HSA (defaults to ON)
PAL - enabled by ROCCLR_ENABLE_PAL (defaults to OFF)
Any configuration is supported as long as at least one compiler and one
runtime is enabled.
Since ROCclr clients can configure it differently, one cannot reuse the
same ROCclr build artifacts between different clients. To assure this,
this patch assumes that ROCclr will be built as part of the clients
project.
Change-Id: Id4a5c43634296802b8ae87d1ad5984968391ccaf
- Make sure barrier with dependent signals issues before queue
index reservation
- Don't issue extra barrier if it's already a barrier command
with dependent signals
Change-Id: I179a8b7adac79eed698f4a4d9eca2606d8e913aa
Chauncey Hui
German Andryeyev
Vladislav Sytchenko
Jason Tang
Anusha GodavarthySurya
Alex Xie
Saleel Kudchadker
Christophe Paquot
Sourabh Betigeri
Aaron Liu
Arya.Rafii
kjayapra-amd
cjatin