Ma, Bing
a75174f855
* Clean up obsolete SPM logics
* Add PERFCOUNTER_SELECT1 to CounterRegInfo
* Add RLC_SPM_PERFMON_SAMPLE_DELAY_MAX
[ROCm/aqlprofile commit: 6f236ffb5f]
407 строки
19 KiB
C++
407 строки
19 KiB
C++
// MIT License
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//
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// Copyright (c) 2017-2025 Advanced Micro Devices, Inc.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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#ifndef SRC_PM4_GFX10_CMD_BUILDER_H_
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#define SRC_PM4_GFX10_CMD_BUILDER_H_
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#include <assert.h>
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#include "def/gfx10_def.h"
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#include "pm4/cmd_builder.h"
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namespace pm4_builder {
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/// @brief class Gfx10CmdBuilder implements the virtual class CmdBuilder
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/// for GFX10 gpus
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class Gfx10CmdBuilder : public CmdBuilder {
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private:
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// @brief Return a Type 3 PM4 packet header
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static uint32_t MakePacket3Header(uint32_t opcode, size_t packet_size) {
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uint32_t count = packet_size / sizeof(uint32_t) - 2;
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uint32_t header = PACKET3(opcode, count);
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return header;
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}
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public:
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Gfx10CmdBuilder(const reg_base_offset_table* _table) : CmdBuilder(_table){};
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static constexpr bool IsPrivilegedConfigReg(uint32_t addr) {
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return ((addr >= CONFIG_SPACE_START) && (addr <= CONFIG_SPACE_END));
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}
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void BuildBarrierCommand(CmdBuffer* cmdBuf) {
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// Initialize the command header
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uint32_t header = MakePacket3Header(PACKET3_EVENT_WRITE, 2 * sizeof(uint32_t));
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uint32_t dword2 =
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PACKET3_EVENT_WRITE__EVENT_TYPE(CS_PARTIAL_FLUSH) |
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PACKET3_EVENT_WRITE__EVENT_INDEX(PACKET3_EVENT_WRITE__EVENT_INDEX__CS_PARTIAL_FLUSH);
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// build the pm4mec_event_write command which has 2 Dwords
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uint32_t pm4mec_event_write_cmd[2] = {header, dword2};
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// Append the built command into output Command Buffer
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APPEND_COMMAND_WRAPPER(cmdBuf, pm4mec_event_write_cmd);
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}
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void BuildWriteWaitIdlePacket(CmdBuffer* cmdbuf) override { BuildBarrierCommand(cmdbuf); }
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void BuildCacheFlushPacket(CmdBuffer* cmdbuf, size_t addr, size_t size) {
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// Initialize the command header
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uint32_t header = MakePacket3Header(PACKET3_ACQUIRE_MEM, 8 * sizeof(uint32_t));
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// Specify the base address of memory to invalidate.
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// The address must be 256 byte aligned.
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uint32_t dword5 = PACKET3_ACQUIRE_MEM__COHER_BASE_LO((uint32_t(addr >> 8)));
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uint32_t dword6 = PACKET3_ACQUIRE_MEM__COHER_BASE_HI((uint8_t(addr >> 40)));
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// Specify the size of memory to invalidate.
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// Size is specified in terms of 256 byte chunks. A coher_size
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// of 0xFFFFFFFF actually specified 0xFFFFFFFF00 (40 bits)
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// of memory. The field coher_size_hi specifies memory from
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// bits 40-64 for a total of 256 TB.
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size = ((addr % 256 + size) >> 8) + ((size + 0xFF) >> 8) - (size >> 8);
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uint32_t dword3 = PACKET3_ACQUIRE_MEM__COHER_SIZE((uint32_t(size)));
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uint32_t dword4 = PACKET3_ACQUIRE_MEM__COHER_SIZE_HI((uint32_t(size >> 32)));
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// Specify the poll interval for determing if operation is complete
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uint32_t dword7 = PACKET3_ACQUIRE_MEM__POLL_INTERVAL(0x10);
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// Program GCR Control Register. Initialize L2 Cache flush
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// for Non-Coherent memory blocks
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uint32_t dword8 = PACKET3_ACQUIRE_MEM__GCR_CNTL(
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((GCR_CNTL__SEQ_FORWARD & GCR_CNTL__SEQ_MASK) | GCR_CNTL__GL2_WB_MASK));
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// build the pm4mec_acquire_mem command which has 8 Dwords
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uint32_t pm4mec_acquire_mem_cmd[8] = {header, 0, dword3, dword4,
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dword5, dword6, dword7, dword8};
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// Append the built command into output Command Buffer
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APPEND_COMMAND_WRAPPER(cmdbuf, pm4mec_acquire_mem_cmd);
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}
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void BuildWaitRegMemCommand(CmdBuffer* cmdbuf, bool mem_space, uint64_t wait_addr, bool func_eq,
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uint32_t mask_val, uint32_t wait_val) override {
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// Initialize the command header
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uint32_t header = MakePacket3Header(PACKET3_WAIT_REG_MEM, 7 * sizeof(uint32_t));
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uint32_t dword7 = PACKET3_WAIT_REG_MEM__POLL_INTERVAL(0x04);
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uint32_t dword2_operation =
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PACKET3_WAIT_REG_MEM__OPERATION(PACKET3_WAIT_REG_MEM__OPERATION__WAIT_REG_MEM);
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// Apply the space to which addr belongs
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uint32_t dword2_mem_space =
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mem_space
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? PACKET3_WAIT_REG_MEM__MEM_SPACE(PACKET3_WAIT_REG_MEM__MEM_SPACE__MEMORY_SPACE)
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: PACKET3_WAIT_REG_MEM__MEM_SPACE(PACKET3_WAIT_REG_MEM__MEM_SPACE__REGISTER_SPACE);
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// Apply the function - equal / not equal desired by user
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uint32_t dword2_function =
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func_eq ? PACKET3_WAIT_REG_MEM__FUNCTION(
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PACKET3_WAIT_REG_MEM__FUNCTION__EQUAL_TO_THE_REFERENCE_VALUE)
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: PACKET3_WAIT_REG_MEM__FUNCTION(
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PACKET3_WAIT_REG_MEM__FUNCTION__NOT_EQUAL_REFERENCE_VALUE);
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uint32_t dword2 = dword2_operation | dword2_mem_space | dword2_function;
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// Apply the mask on value at address/register
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uint32_t dword6 = PACKET3_WAIT_REG_MEM__MASK(mask_val);
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// Value to use in applying equal / not equal function
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uint32_t dword5 = PACKET3_WAIT_REG_MEM__REFERENCE(wait_val);
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// The address to poll should be DWord (4 byte) aligned
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// Update upper 32 bit address if addr is not a register
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uint32_t dword3 = 0;
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uint32_t dword4 = 0;
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if (mem_space) {
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assert(!(wait_addr & 0x3) && "WaitRegMem address must be 4 byte aligned");
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dword3 = PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_LO((Low32(wait_addr) >> 2));
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dword4 = PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_HI(High32(wait_addr));
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} else
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dword3 = PACKET3_WAIT_REG_MEM__REG_POLL_ADDR(wait_addr);
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// build the pm4mec_wait_reg_mem command which has 7 Dwords
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uint32_t pm4mec_wait_reg_mem_cmd[7] = {header, dword2, dword3, dword4, dword5, dword6, dword7};
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// Append the built command into output Command Buffer
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APPEND_COMMAND_WRAPPER(cmdbuf, pm4mec_wait_reg_mem_cmd);
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}
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void BuildWriteShRegPacket(CmdBuffer* cmdbuf, uint32_t addr, uint32_t value) override {
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// Initialize the command header
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uint32_t header = MakePacket3Header(PACKET3_SET_SH_REG, 2 * sizeof(uint32_t) + sizeof(value));
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uint32_t dword2 = PACKET3_SET_SH_REG__REG_OFFSET((addr - PERSISTENT_SPACE_START)) |
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PACKET3_SET_SH_REG__INDEX(PACKET3_SET_SH_REG__INDEX__DEFAULT);
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// build the pm4mec_set_sh_reg command which has 3 Dwords
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uint32_t pm4mec_set_sh_reg_cmd[3] = {header, dword2, value};
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// Append the built command into output Command Buffer
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APPEND_COMMAND_WRAPPER(cmdbuf, pm4mec_set_sh_reg_cmd);
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}
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void BuildCopyRegDataPacket(CmdBuffer* cmdbuf, uint32_t src_reg_addr, const void* dst_addr,
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uint32_t size, bool wait) override {
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// Initialize the command header
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uint32_t header = MakePacket3Header(PACKET3_COPY_DATA, 6 * sizeof(uint32_t));
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uint32_t dword2 =
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(IsPrivilegedConfigReg(src_reg_addr)
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? PACKET3_COPY_DATA__SRC_SEL(PACKET3_COPY_DATA__SRC_SEL__PERFCOUNTERS)
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: PACKET3_COPY_DATA__SRC_SEL(PACKET3_COPY_DATA__SRC_SEL__MEM_MAPPED_REGISTER)) |
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PACKET3_COPY_DATA__SRC_CACHE_POLICY(PACKET3_COPY_DATA__SRC_CACHE_POLICY__LRU) |
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PACKET3_COPY_DATA__DST_SEL(PACKET3_COPY_DATA__DST_SEL__TC_L2) |
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PACKET3_COPY_DATA__DST_CACHE_POLICY(PACKET3_COPY_DATA__DST_CACHE_POLICY__LRU) |
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(wait ? PACKET3_COPY_DATA__WR_CONFIRM(PACKET3_COPY_DATA__WR_CONFIRM__WAIT_FOR_CONFIRMATION)
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: PACKET3_COPY_DATA__WR_CONFIRM(
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PACKET3_COPY_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_CONFIRMATION)) |
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((size == 0) ? PACKET3_COPY_DATA__COUNT_SEL(PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA)
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: PACKET3_COPY_DATA__COUNT_SEL(PACKET3_COPY_DATA__COUNT_SEL__64_BITS_OF_DATA));
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// Specify the source register offset
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uint32_t dword3 = PACKET3_COPY_DATA__SRC_REG_OFFSET(src_reg_addr);
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// Specify the destination memory address
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uint32_t dword6 = PACKET3_COPY_DATA__DST_ADDR_HI(PtrHigh32(dst_addr));
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uint32_t dword5 = 0;
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if (size == 0) {
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dword5 |= PACKET3_COPY_DATA__DST_32B_ADDR_LO((PtrLow32(dst_addr) >> 2));
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} else {
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dword5 |= PACKET3_COPY_DATA__DST_64B_ADDR_LO((PtrLow32(dst_addr) >> 3));
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}
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// build the pm4mec_copy_data command which has 6 Dwords
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uint32_t pm4mec_copy_data_cmd[6] = {header, dword2, dword3, 0, dword5, dword6};
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// Append the built command into output Command Buffer
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APPEND_COMMAND_WRAPPER(cmdbuf, pm4mec_copy_data_cmd);
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}
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void BuildMutexAcquirePacket(CmdBuffer* cmdbuf, size_t addr) override {
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constexpr uint32_t GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 8;
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uint32_t header = MakePacket3Header(PACKET3_ATOMIC_MEM, 9 * sizeof(uint32_t));
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uint32_t dword2 =
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PACKET3_ATOMIC_MEM__COMMAND(PACKET3_ATOMIC_MEM__COMMAND__LOOP_UNTIL_COMPARE_SATISFIED) |
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PACKET3_ATOMIC_MEM__ATOMIC(GL2_OP_ATOMIC_CMPSWAP_RTN_32);
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uint32_t dword9 = PACKET3_ATOMIC_MEM__LOOP_INTERVAL(4);
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uint32_t dword3 = PACKET3_ATOMIC_MEM__ADDR_LO(uint32_t(addr));
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uint32_t dword4 = PACKET3_ATOMIC_MEM__ADDR_HI((addr >> 32));
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uint32_t dword5 = PACKET3_ATOMIC_MEM__SRC_DATA_LO(MakeMutexSlot());
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uint32_t dword6 = PACKET3_ATOMIC_MEM__CMP_DATA_LO(0);
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// build the pm4mec_atomic_mem command which has 9 Dwords
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uint32_t pm4_mec_atomic_mem_cmd[9] = {header, dword2, dword3, dword4, dword5,
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dword6, 0, 0, dword9};
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APPEND_COMMAND_WRAPPER(cmdbuf, pm4_mec_atomic_mem_cmd);
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}
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void BuildMutexReleasePacket(CmdBuffer* cmdbuf, size_t addr) override {
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constexpr uint32_t GL2_OP_ATOMIC_SWAP_RTN_32 = 7;
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uint32_t header = MakePacket3Header(PACKET3_ATOMIC_MEM, 9 * sizeof(uint32_t));
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uint32_t dword2 = PACKET3_ATOMIC_MEM__COMMAND(PACKET3_ATOMIC_MEM__COMMAND__SINGLE_PASS_ATOMIC) |
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PACKET3_ATOMIC_MEM__ATOMIC(GL2_OP_ATOMIC_SWAP_RTN_32);
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uint32_t dword3 = PACKET3_ATOMIC_MEM__ADDR_LO(uint32_t(addr));
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uint32_t dword4 = PACKET3_ATOMIC_MEM__ADDR_HI((addr >> 32));
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uint32_t dword5 = PACKET3_ATOMIC_MEM__SRC_DATA_LO(0);
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// build the pm4mec_atomic_mem command which has 9 Dwords
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uint32_t pm4_mec_atomic_mem_cmd[9] = {header, dword2, dword3, dword4, dword5, 0, 0, 0, 0};
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APPEND_COMMAND_WRAPPER(cmdbuf, pm4_mec_atomic_mem_cmd);
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}
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void BuildPrimeL2(CmdBuffer* cmdBuf, uint64_t addr) override {};
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void BuildPredExecPacket(CmdBuffer* cmdbuf, uint32_t xcc_id = 0, uint32_t exec_count = 0) {}
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void BuildWriteUConfigRegPacket(CmdBuffer* cmdbuf, uint32_t addr, uint32_t value) override {
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// Initialize the command header
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uint32_t header =
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MakePacket3Header(PACKET3_SET_UCONFIG_REG, 2 * sizeof(uint32_t) + sizeof(value));
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uint32_t dword2 = PACKET3_SET_UCONFIG_REG__REG_OFFSET((addr - UCONFIG_SPACE_START));
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// build the pm4mec_set_uconfig_reg command which has 3 Dwords
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uint32_t pm4mec_set_uconfig_reg_cmd[3] = {header, dword2, value};
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// Append the built command into output Command Buffer
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APPEND_COMMAND_WRAPPER(cmdbuf, pm4mec_set_uconfig_reg_cmd);
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}
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void BuildWritePConfigRegPacket(CmdBuffer* cmdbuf, uint64_t addr, uint32_t value) {
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// Initialize the command header
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uint32_t header = MakePacket3Header(PACKET3_COPY_DATA, 6 * sizeof(uint32_t));
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uint32_t dword2 =
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PACKET3_COPY_DATA__SRC_SEL(PACKET3_COPY_DATA__SRC_SEL__IMMEDIATE_DATA) |
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PACKET3_COPY_DATA__SRC_CACHE_POLICY(PACKET3_COPY_DATA__SRC_CACHE_POLICY__LRU) |
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(IsPrivilegedConfigReg(addr) && bUsePerfCounterMode
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? PACKET3_COPY_DATA__DST_SEL(PACKET3_COPY_DATA__DST_SEL__PERFCOUNTERS)
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: PACKET3_COPY_DATA__DST_SEL(PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REGISTER)) |
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PACKET3_COPY_DATA__DST_CACHE_POLICY(PACKET3_COPY_DATA__DST_CACHE_POLICY__LRU) |
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PACKET3_COPY_DATA__WR_CONFIRM(PACKET3_COPY_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_CONFIRMATION) |
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PACKET3_COPY_DATA__COUNT_SEL(PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA);
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uint32_t dword3 = PACKET3_COPY_DATA__IMM_DATA(value);
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// extend register address to all 64-bit
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uint32_t dword5 = Low32(addr);
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uint32_t dword6 = PACKET3_COPY_DATA__DST_ADDR_HI(High32(addr));
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// build the pm4mec_copy_data command which has 6 Dwords
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uint32_t pm4mec_copy_data_cmd[6] = {header, dword2, dword3, 0, dword5, dword6};
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// Append the built command into output Command Buffer
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APPEND_COMMAND_WRAPPER(cmdbuf, pm4mec_copy_data_cmd);
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}
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void BuildWriteConfigRegPacket(CmdBuffer* cmdbuf, uint32_t addr, uint32_t value) {
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return IsPrivilegedConfigReg(addr) ? BuildWritePConfigRegPacket(cmdbuf, addr, value)
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: BuildWriteUConfigRegPacket(cmdbuf, addr, value);
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}
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uint32_t BuildCopyCounterDataPacket(CmdBuffer* cmdbuf, uint64_t src_reg_addr_lo,
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uint64_t src_reg_addr_hi, const void* dst_addr,
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uint32_t dw_mask) {
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uint32_t read_counter = 0;
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if (dw_mask & 0x1) {
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BuildCopyRegDataPacket(cmdbuf, src_reg_addr_lo, (uint32_t*)dst_addr + read_counter,
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PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA, false);
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++read_counter;
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}
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if (dw_mask & 0x2) {
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BuildCopyRegDataPacket(cmdbuf, src_reg_addr_hi, (uint32_t*)dst_addr + read_counter,
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PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA, false);
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++read_counter;
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}
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return read_counter;
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}
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void BuildWriteRegDataPacket(CmdBuffer* cmdbuf, uint32_t dst_reg_addr, const uint32_t* data,
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uint32_t count, bool wait) {
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// Initialize the command header
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uint32_t header =
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MakePacket3Header(PACKET3_WRITE_DATA, 4 * sizeof(uint32_t) + count * sizeof(data[0]));
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// ordinal2
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uint32_t dword2 =
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PACKET3_WRITE_DATA__DST_SEL(
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PACKET3_WRITE_DATA__DST_SEL__MEM_MAPPED_REGISTER) | // mem-mapped reg
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PACKET3_WRITE_DATA__ADDR_INCR(
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PACKET3_WRITE_DATA__ADDR_INCR__DO_NOT_INCREMENT_ADDRESS) | // not increment address
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(wait ? PACKET3_WRITE_DATA__WR_CONFIRM(
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PACKET3_WRITE_DATA__WR_CONFIRM__WAIT_FOR_WRITE_CONFIRMATION)
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: PACKET3_WRITE_DATA__WR_CONFIRM(
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PACKET3_WRITE_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_WRITE_CONFIRMATION));
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// ordinal3
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uint32_t dword3 = PACKET3_WRITE_DATA__DST_MMREG_ADDR(dst_reg_addr); // mem-mapped reg
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// ordinal4
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uint32_t dword4 = PACKET3_WRITE_DATA__DST_MEM_ADDR_HI(0); // mem-mapped reg
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// build the pm4mec_write_data command which has 4 Dwords
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uint32_t pm4mec_write_data_cmd[4] = {header, dword2, dword3, dword4};
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// Append the built command into output Command Buffer
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APPEND_COMMAND_WRAPPER(cmdbuf, pm4mec_write_data_cmd);
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// appending data dwords
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for (uint32_t i = 0; i < count; ++i) {
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APPEND_COMMAND_WRAPPER(cmdbuf, data[i]);
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}
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if (count & 1) {
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// Insert a NOP spacer
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BuildNopPacket(cmdbuf, 1);
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}
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}
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void BuildNopPacket(CmdBuffer* cmdbuf, uint32_t num_dwords) {
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uint32_t header = MakePacket3Header(PACKET3_NOP, num_dwords * sizeof(uint32_t));
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APPEND_COMMAND_WRAPPER(cmdbuf, header);
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if (num_dwords > 1) {
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std::vector<uint32_t> data_block((num_dwords - 1), 0);
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APPEND_COMMAND_WRAPPER(cmdbuf, data_block.data(), (num_dwords - 1));
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}
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}
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void BuildThreadTraceEventFinish(CmdBuffer* cmdBuf) {}
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void BuildIndirectBufferCmd(CmdBuffer* cmdbuf, const void* cmd_addr, std::size_t cmd_size) {
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// Verify the address is 4-byte aligned
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assert(!(uintptr_t(cmd_addr) & 0x3) && "IndirectBuffer address must be 4 byte aligned");
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// Initialize the command header
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uint32_t header = MakePacket3Header(PACKET3_INDIRECT_BUFFER, 4 * sizeof(uint32_t));
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// Specify the address of indirect buffer encoding cmd stream
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uint32_t dword2 = PACKET3_INDIRECT_BUFFER__IB_BASE_LO((PtrLow32(cmd_addr) >> 2));
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uint32_t dword3 = PACKET3_INDIRECT_BUFFER__IB_BASE_HI(PtrHigh32(cmd_addr));
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// Specify the size of indirect buffer and cache policy to set
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// upon executing the cmds of indirect buffer
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uint32_t dword4 =
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PACKET3_INDIRECT_BUFFER__VALID(1) |
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PACKET3_INDIRECT_BUFFER__IB_SIZE((cmd_size / sizeof(uint32_t))) |
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PACKET3_INDIRECT_BUFFER__CACHE_POLICY(PACKET3_INDIRECT_BUFFER__CACHE_POLICY__STREAM);
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// build the pm4mec_indirect_buffer command which has 4 Dwords
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uint32_t pm4mec_indirect_buffer_cmd[4] = {header, dword2, dword3, dword4};
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// Append the built command into output Command Buffer
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APPEND_COMMAND_WRAPPER(cmdbuf, pm4mec_indirect_buffer_cmd);
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}
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void BuildWriteShRegPacket(CmdBuffer* cmd, const Register& reg, uint32_t value) {
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BuildWriteShRegPacket(cmd, get_addr(reg), value);
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}
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void BuildWriteUConfigRegPacket(CmdBuffer* cmd, const Register& reg, uint32_t value) {
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BuildWriteUConfigRegPacket(cmd, get_addr(reg), value);
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}
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void BuildWritePConfigRegPacket(CmdBuffer* cmd, const Register& reg, uint32_t value) {
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BuildWritePConfigRegPacket(cmd, get_addr(reg), value);
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}
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void BuildCopyCounterDataPacket(CmdBuffer* cmd, const Register& reg_lo, const Register& reg_hi,
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const void* dst_addr, uint32_t mask) {
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BuildCopyCounterDataPacket(cmd, (mask & 1 << 0) ? get_addr(reg_lo) : 0,
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(mask & 1 << 1) ? get_addr(reg_hi) : 0, dst_addr, mask);
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}
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void BuildWriteConfigRegPacket(CmdBuffer* cmd, const Register& reg, uint32_t value) {
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BuildWriteConfigRegPacket(cmd, get_addr(reg), value);
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}
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void BuildWaitRegMemCommand(CmdBuffer* cmd, bool mem_space, const Register& wait_addr,
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bool func_eq, uint32_t mask_val, uint32_t wait_val) {
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BuildWaitRegMemCommand(cmd, mem_space, get_addr(wait_addr), func_eq, mask_val, wait_val);
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}
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void BuildWriteRegDataPacket(CmdBuffer* cmd, const Register& reg, const uint32_t* data,
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uint32_t count, bool wait) {
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BuildWriteRegDataPacket(cmd, get_addr(reg), data, count, wait);
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}
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void BuildCopyRegDataPacket(CmdBuffer* cmd, const Register& reg, const void* dst_addr,
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uint32_t size, bool wait) {
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BuildCopyRegDataPacket(cmd, get_addr(reg), dst_addr, size, wait);
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}
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};
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} // namespace pm4_builder
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#endif // SRC_PM4_GFX10_CMD_BUILDER_H_
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