Sean Keely 32d0fcafa9 Limit clock synchronization to 16Hz. ...

Improves HIP event performance in directed benchmarks where
clock sync latency is significant.

Change-Id: I78b724a14a8f5b6a9a2b9f4d85afe9d8b81808a6

2020-11-20 15:06:13 -05:00

..

common

Make explicit reference between init modules.

2020-07-15 16:02:15 -04:00

inc

Limit clock synchronization to 16Hz.

2020-11-20 15:06:13 -05:00

runtime

Limit clock synchronization to 16Hz.

2020-11-20 15:06:13 -05:00

util

Style update for SDMA enable flag.

2020-11-20 15:06:02 -05:00