Laurent Morichetti
134 строки
4.8 KiB
C++
134 строки
4.8 KiB
C++
/* Copyright (c) 2014-present Advanced Micro Devices, Inc.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE. */
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#ifndef HWDBG_GPUDEBGGER_H_
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#define HWDBG_GPUDEBGGER_H_
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#include <cstddef>
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#include <cstdint>
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#include "hsa.h"
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#include "amd_hsa_kernel_code.h"
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#include "device/device.hpp"
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#include "device/hwdebug.hpp"
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#include "acl.h"
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static const int NumberReserveVgprs = 4;
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namespace gpu {
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/**
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* \defgroup Services_API OCL Runtime Services API
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* @{
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*/
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/*! \brief Dispatch packet information
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*
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* This structure contains the packet information for kernel dispatch
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*/
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struct PacketAmdInfo {
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uint32_t trapReservedVgprIndex_; //!< reserved VGPR index, -1 when they are not valid
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uint32_t scratchBufferWaveOffset_; //!< scratch buffer wave offset, -1 when no scratch buffer
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void* pointerToIsaBuffer_; //!< pointer to the buffer containing ISA
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size_t sizeOfIsaBuffer_; //!< size of the ISA buffer
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uint32_t numberOfVgprs_; //!< number of VGPRs used by the kernel
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uint32_t numberOfSgprs_; //!< number of SGPRs used by the kernel
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size_t sizeOfStaticGroupMemory_; //!< Static local memory used by the kernel
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};
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/*! \brief Cache mask for invalidation
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*/
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struct HwDbgGpuCacheMask {
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HwDbgGpuCacheMask() : ui32All_(0) {}
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HwDbgGpuCacheMask(uint32_t mask) : ui32All_(mask) {}
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union {
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struct {
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uint32_t sqICache_ : 1; //!< Instruction cache
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uint32_t sqKCache_ : 1; //!< Data cache
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uint32_t tcL1_ : 1; //!< tcL1 cache
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uint32_t tcL2_ : 1; //!< tcL2 cache
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uint32_t reserved_ : 28;
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};
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uint32_t ui32All_;
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};
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};
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/*! \brief Address watch information
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*
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* Information about each watch point - address, mask, mode and event
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*/
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struct HwDbgAddressWatch {
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void* watchAddress_; //! The address of watch point
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uint64_t watchMask_; //! The mask for watch point (lower 24 bits)
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cl_dbg_address_watch_mode_amd watchMode_; //! The watch mode for this watch
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DebugEvent event_; //! Event of the watch point (not used for now)
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};
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/*! \brief Runtime structure used to communicate debug information
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* between Ocl services and core for a kernel dispatch.
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*/
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struct DebugToolInfo {
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uint64_t scratchAddress_; //! Scratch memory address
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size_t scratchSize_; //! Scratch memory size
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uint64_t globalAddress_; //! Global memory address
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uint32_t cacheDisableMask_; //! Cache mask, indicating caches disabled
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uint32_t exceptionMask_; //! Exception mask
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uint32_t reservedCuNum_; //! Number of reserved CUs for display,
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//! which ranges from 0 to 7 in the current implementation.
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bool monitorMode_; //! Debug or profiler mode
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bool gpuSingleStepMode_; //! SQ debug mode
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amd::Memory* trapHandler_; //! Trap handler address
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amd::Memory* trapBuffer_; //! Trap buffer address
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bool sqPerfcounterEnable_; //! whether SQ perf counters are enabled
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aclBinary* aclBinary_; //! pointer of the kernel ACL binary
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amd::Event* event_; //! pointer of the kernel event in the enqueue command
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};
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/*! \brief Message used by the KFD wave control for CI
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*
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* Structure indicates the various information used by the wave control function.
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*/
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struct HwDebugWaveAddr {
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uint32_t VMID_ : 4; //! Virtual memory id
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uint32_t wave_ : 4; //! Wave id
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uint32_t SIMD_ : 2; //! SIMD id
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uint32_t CU_ : 4; //! Compute unit
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uint32_t SH_ : 1; //! Shader array
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uint32_t SE_ : 1; //! Shader engine
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};
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/*! \brief Kernel code information
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*
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* This structure contains the pointer of mapped kernel code for host access
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* and its size (in bytes)
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*/
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struct AqlCodeInfo {
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amd_kernel_code_t* aqlCode_; //! pointer of AQL code to allow host access
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uint32_t aqlCodeSize_; //! size of AQL code
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};
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/**@}*/
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} // namespace gpu
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#endif // HWDBG_GPUDEBGGER_H_
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