German Andryeyev
5319163521
git-subtree-dir: projects/rocr-runtime/libhsakmt/include/impl git-subtree-mainline:55f7d39fa5git-subtree-split:c34ec1e52f
1091 lignes
37 KiB
C++
1091 lignes
37 KiB
C++
#ifndef _WSL_INC_PM4_CMDS_H_
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#define _WSL_INC_PM4_CMDS_H_
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#include <cstdint>
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#define mmCOMPUTE_NUM_THREAD_X 0x2E07
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#define mmCOMPUTE_PGM_LO 0x2E0C
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#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x2E10
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#define mmCOMPUTE_PGM_RSRC1 0x2E12
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#define mmCOMPUTE_PGM_RSRC3 0x2E28
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#define mmCOMPUTE_RESOURCE_LIMITS 0x2E15
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#define mmCOMPUTE_USER_DATA_0 0x2E40
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#define PM4_TYPE_SHIFT 30
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#define PM4_COUNT_SHIFT 16
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#define PM4_OPCODE_SHIFT 8
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#define PM4_SHADER_TYPE_SHIFT 1
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#define PM4_GFX_SHADER 0
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#define PM4_COMPUTE_SHADER 1
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#define PM4_TYPE3_HDR(_opc_, _count_) \
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(uint32_t)((3) << PM4_TYPE_SHIFT | \
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((_count_) - 2) << PM4_COUNT_SHIFT | \
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(_opc_) << PM4_OPCODE_SHIFT) | \
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(PM4_COMPUTE_SHADER << PM4_SHADER_TYPE_SHIFT)
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union PM4_MEC_TYPE_3_HEADER {
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struct {
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uint32_t reserved1 : 8; ///< reserved
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uint32_t opcode : 8; ///< IT opcode
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uint32_t count : 14;///< number of DWORDs - 1 in the information body.
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uint32_t type : 2; ///< packet identifier. It should be 3 for type 3 packets
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};
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uint32_t u32All;
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};
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#define IT_DISPATCH_DIRECT 0x15
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#define IT_ATOMIC_MEM 0x1E
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#define IT_WRITE_DATA 0x37
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#define IT_INDIRECT_BUFFER 0x3F
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#define IT_COPY_DATA 0x40
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#define IT_EVENT_WRITE 0x46
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#define IT_RELEASE_MEM 0x49
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#define IT_ACQUIRE_MEM 0x58
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#define IT_SET_SH_REG 0x76
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struct PM4_MEC_SET_SH_REG {
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union {
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PM4_MEC_TYPE_3_HEADER header;
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uint32_t ordinal1;
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};
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union {
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struct {
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uint32_t reg_offset:16;
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uint32_t reserved1:16;
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} bitfields2;
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uint32_t ordinal2;
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};
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};
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struct PM4_MEC_DISPATCH_DIRECT {
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union {
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PM4_MEC_TYPE_3_HEADER header;
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uint32_t ordinal1;
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};
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uint32_t dim_x;
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uint32_t dim_y;
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uint32_t dim_z;
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uint32_t dispatch_initiator;
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};
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// ------------------------------- MEC_EVENT_WRITE_event_index_enum -------------------------------
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enum MEC_EVENT_WRITE_event_index_enum {
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event_index__mec_event_write__other = 0,
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event_index__mec_event_write__sample_pipelinestat = 2,
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event_index__mec_event_write__cs_partial_flush = 4,
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event_index__mec_event_write__sample_streamoutstats__GFX11 = 8,
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event_index__mec_event_write__sample_streamoutstats1__GFX11 = 9,
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event_index__mec_event_write__sample_streamoutstats2__GFX11 = 10,
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event_index__mec_event_write__sample_streamoutstats3__GFX11 = 11,
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};
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enum VGT_EVENT_TYPE {
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Reserved_0x00 = 0x00000000,
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SAMPLE_STREAMOUTSTATS1 = 0x00000001,
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SAMPLE_STREAMOUTSTATS2 = 0x00000002,
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SAMPLE_STREAMOUTSTATS3 = 0x00000003,
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CACHE_FLUSH_TS = 0x00000004,
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CONTEXT_DONE = 0x00000005,
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CACHE_FLUSH = 0x00000006,
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CS_PARTIAL_FLUSH = 0x00000007,
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VGT_STREAMOUT_SYNC = 0x00000008,
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VGT_STREAMOUT_RESET = 0x0000000a,
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END_OF_PIPE_INCR_DE = 0x0000000b,
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END_OF_PIPE_IB_END = 0x0000000c,
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RST_PIX_CNT = 0x0000000d,
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BREAK_BATCH = 0x0000000e,
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VS_PARTIAL_FLUSH = 0x0000000f,
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PS_PARTIAL_FLUSH = 0x00000010,
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FLUSH_HS_OUTPUT = 0x00000011,
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FLUSH_DFSM = 0x00000012,
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RESET_TO_LOWEST_VGT = 0x00000013,
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CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014,
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CACHE_FLUSH_AND_INV_EVENT = 0x00000016,
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PERFCOUNTER_START = 0x00000017,
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PERFCOUNTER_STOP = 0x00000018,
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PIPELINESTAT_START = 0x00000019,
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PIPELINESTAT_STOP = 0x0000001a,
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PERFCOUNTER_SAMPLE = 0x0000001b,
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SAMPLE_PIPELINESTAT = 0x0000001e,
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SO_VGTSTREAMOUT_FLUSH = 0x0000001f,
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SAMPLE_STREAMOUTSTATS = 0x00000020,
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RESET_VTX_CNT = 0x00000021,
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BLOCK_CONTEXT_DONE = 0x00000022,
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CS_CONTEXT_DONE = 0x00000023,
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VGT_FLUSH = 0x00000024,
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TGID_ROLLOVER = 0x00000025,
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SQ_NON_EVENT = 0x00000026,
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SC_SEND_DB_VPZ = 0x00000027,
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BOTTOM_OF_PIPE_TS = 0x00000028,
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FLUSH_SX_TS = 0x00000029,
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DB_CACHE_FLUSH_AND_INV = 0x0000002a,
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FLUSH_AND_INV_DB_DATA_TS = 0x0000002b,
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FLUSH_AND_INV_DB_META = 0x0000002c,
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FLUSH_AND_INV_CB_DATA_TS = 0x0000002d,
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FLUSH_AND_INV_CB_META = 0x0000002e,
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CS_DONE = 0x0000002f,
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PS_DONE = 0x00000030,
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FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000031,
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SX_CB_RAT_ACK_REQUEST = 0x00000032,
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THREAD_TRACE_START = 0x00000033,
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THREAD_TRACE_STOP = 0x00000034,
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THREAD_TRACE_MARKER = 0x00000035,
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THREAD_TRACE_FINISH = 0x00000037,
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PIXEL_PIPE_STAT_CONTROL = 0x00000038,
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PIXEL_PIPE_STAT_DUMP = 0x00000039,
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PIXEL_PIPE_STAT_RESET = 0x0000003a,
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CONTEXT_SUSPEND = 0x0000003b,
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OFFCHIP_HS_DEALLOC = 0x0000003c,
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ENABLE_NGG_PIPELINE = 0x0000003d,
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SET_FE_ID__GFX09 = 0x00000009,
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Available_0x1c__GFX09 = 0x0000001c,
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Available_0x1d__GFX09 = 0x0000001d,
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THREAD_TRACE_FLUSH__GFX09 = 0x00000036,
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Reserved_0x3f__GFX09 = 0x0000003f,
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ZPASS_DONE__GFX09_10 = 0x00000015,
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ENABLE_LEGACY_PIPELINE__GFX09_10 = 0x0000003e,
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Reserved_0x09__GFX10PLUS = 0x00000009,
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FLUSH_ES_OUTPUT__GFX10PLUS = 0x0000001c,
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BIN_CONF_OVERRIDE_CHECK__GFX10PLUS = 0x0000001d,
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THREAD_TRACE_DRAW__GFX10PLUS = 0x00000036,
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DRAW_DONE__GFX10PLUS = 0x0000003f,
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WAIT_SYNC__GFX11 = 0x00000015,
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ENABLE_PIPELINE_NOT_USED__GFX11 = 0x0000003e,
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};
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struct PM4_MEC_EVENT_WRITE {
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union {
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PM4_MEC_TYPE_3_HEADER header;
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uint32_t ordinal1;
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};
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union {
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struct {
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uint32_t event_type:6;
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uint32_t reserved1:2;
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uint32_t event_index:4;
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uint32_t reserved2:19;
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uint32_t offload_enable:1;
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} bitfields2;
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uint32_t ordinal2;
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};
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};
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struct PM4_MEC_ATOMIC_MEM {
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union {
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PM4_MEC_TYPE_3_HEADER header;
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uint32_t ordinal1;
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};
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union {
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struct {
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uint32_t atomic:7;
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uint32_t reserved1:1;
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uint32_t command:4;
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uint32_t reserved2:13;
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uint32_t cache_policy:2;
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uint32_t reserved3:5;
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} bitfields2;
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uint32_t ordinal2;
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};
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uint32_t addr_lo;
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uint32_t addr_hi;
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uint32_t src_data_lo;
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uint32_t src_data_hi;
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uint32_t cmp_data_lo;
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uint32_t cmp_data_hi;
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union {
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struct {
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uint32_t loop_interval:13;
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uint32_t reserved4:19;
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} bitfields9;
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uint32_t ordinal9;
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};
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};
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struct PM4_MEC_WRITE_DATA {
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union {
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PM4_MEC_TYPE_3_HEADER header;
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uint32_t ordinal1;
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};
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union {
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struct {
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uint32_t reserved1:8;
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uint32_t dst_sel:4;
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uint32_t reserved2:4;
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uint32_t addr_incr:1;
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uint32_t reserved3:2;
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uint32_t resume_vf:1;
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uint32_t wr_confirm:1;
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uint32_t reserved4:4;
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uint32_t cache_policy:2;
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uint32_t reserved5:5;
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} bitfields2;
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uint32_t ordinal2;
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};
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union {
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struct {
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uint32_t dst_mmreg_addr:18;
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uint32_t reserved6:14;
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} bitfields3a;
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struct {
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uint32_t dst_gds_addr:16;
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uint32_t reserved7:16;
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} bitfields3b;
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struct {
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uint32_t reserved8:2;
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uint32_t dst_mem_addr_lo:30;
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} bitfields3c;
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uint32_t ordinal3;
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};
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uint32_t dst_mem_addr_hi;
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uint64_t write_data_value;
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};
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#define PERSISTENT_SPACE_START 0x00002c00
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template <class T>
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void GenerateSetShRegHeader(T* pm4, uint32_t reg_addr) {
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pm4->cmd_set_data.header.u32All = PM4_TYPE3_HDR(IT_SET_SH_REG,
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sizeof(T) / sizeof(uint32_t));
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pm4->cmd_set_data.bitfields2.reg_offset = reg_addr - PERSISTENT_SPACE_START;
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}
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template <class T>
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void GenerateCmdHeader(T* pm4, int op_code) {
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pm4->header.u32All = PM4_TYPE3_HDR(op_code, sizeof(T) / sizeof(uint32_t));
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}
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/// @brief Defines the Gpu command to dispatch a kernel. It embeds
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/// various Gpu hardware specific data structures for initialization
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/// and configuration before a dispatch begins to run
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struct DispatchTemplate {
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/// @brief Structure used to initialize the group dimensions
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/// of a kernel dispatch and if performance counters are enabled
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struct DispatchDimensionRegs {
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PM4_MEC_SET_SH_REG cmd_set_data;
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uint32_t compute_num_thread_x;
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uint32_t compute_num_thread_y;
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uint32_t compute_num_thread_z;
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} dimension_regs;
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struct DispatchProgramRegs {
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PM4_MEC_SET_SH_REG cmd_set_data;
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uint32_t compute_pgm_lo;
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uint32_t compute_pgm_hi;
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} program_regs;
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struct DispatchProgramResourceRegs {
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PM4_MEC_SET_SH_REG cmd_set_data;
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uint32_t compute_pgm_rsrc1;
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uint32_t compute_pgm_rsrc2;
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} program_resource_regs;
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/// @brief Structure used to initialize parameters related to
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/// thread management i.e. number of waves to issue and number
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/// of Compute Units to use
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struct DispatchResourceRegs {
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PM4_MEC_SET_SH_REG cmd_set_data;
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uint32_t compute_resource_limits;
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uint32_t compute_static_thread_mgmt_se0;
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uint32_t compute_static_thread_mgmt_se1;
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uint32_t compute_tmpring_size;
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uint32_t compute_static_thread_mgmt_se2;
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uint32_t compute_static_thread_mgmt_se3;
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} resource_regs;
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/// @brief Structure used to pass handles of the Aql dispatch
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/// packet, Aql queue, Kernel argument address block, Scratch
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/// buffer
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struct DispatchComputeUserDataRegs {
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PM4_MEC_SET_SH_REG cmd_set_data;
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uint32_t compute_user_data[16];
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} compute_user_data_regs;
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/// @brief Structure used to configure Cache flush policy
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/// and dimensions of total work size
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PM4_MEC_DISPATCH_DIRECT dispatch_direct;
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};
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struct DispatchProgramResourceRegs {
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PM4_MEC_SET_SH_REG cmd_set_data;
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uint32_t compute_pgm_rsrc3;
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};
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/// @brief Structure used to issue a programing scratch command for gfx11+
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struct SetScratchTemplate {
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PM4_MEC_SET_SH_REG cmd_set_data;
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uint32_t scratch_lo;
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uint32_t scratch_hi;
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};
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/// @brief Structure used to issue a Gpu Barrier command
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struct BarrierTemplate {
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PM4_MEC_EVENT_WRITE event_write;
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};
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//--------------------MEC_ATOMIC_MEM--------------------
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enum MEC_ATOMIC_MEM_command_enum {
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command__mec_atomic_mem__single_pass_atomic = 0,
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command__mec_atomic_mem__loop_until_compare_satisfied = 1,
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command__mec_atomic_mem__wait_for_write_confirmation = 2,
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command__mec_atomic_mem__send_and_continue = 3,
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};
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enum MEC_ATOMIC_MEM_cache_policy_enum {
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cache_policy__mec_atomic_mem__lru = 0,
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cache_policy__mec_atomic_mem__stream = 1,
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cache_policy__mec_atomic_mem__noa = 2,
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cache_policy__mec_atomic_mem__bypass = 3,
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};
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enum TC_OP {
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TC_OP_READ = 0x00000000,
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TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001,
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TC_OP_ATOMIC_FMIN_RTN_32 = 0x00000002,
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TC_OP_ATOMIC_FMAX_RTN_32 = 0x00000003,
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TC_OP_RESERVED_FOP_RTN_32_0 = 0x00000004,
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TC_OP_RESERVED_FOP_RTN_32_2 = 0x00000006,
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TC_OP_ATOMIC_SWAP_RTN_32 = 0x00000007,
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TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008,
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TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009,
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TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a,
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TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b,
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TC_OP_PROBE_FILTER = 0x0000000c,
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TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e,
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TC_OP_ATOMIC_ADD_RTN_32 = 0x0000000f,
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TC_OP_ATOMIC_SUB_RTN_32 = 0x00000010,
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TC_OP_ATOMIC_SMIN_RTN_32 = 0x00000011,
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TC_OP_ATOMIC_UMIN_RTN_32 = 0x00000012,
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TC_OP_ATOMIC_SMAX_RTN_32 = 0x00000013,
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TC_OP_ATOMIC_UMAX_RTN_32 = 0x00000014,
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TC_OP_ATOMIC_AND_RTN_32 = 0x00000015,
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TC_OP_ATOMIC_OR_RTN_32 = 0x00000016,
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TC_OP_ATOMIC_XOR_RTN_32 = 0x00000017,
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TC_OP_ATOMIC_INC_RTN_32 = 0x00000018,
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TC_OP_ATOMIC_DEC_RTN_32 = 0x00000019,
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TC_OP_WBINVL1_VOL = 0x0000001a,
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TC_OP_WBINVL1_SD = 0x0000001b,
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TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x0000001c,
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TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x0000001d,
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TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x0000001e,
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TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x0000001f,
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TC_OP_WRITE = 0x00000020,
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TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021,
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TC_OP_ATOMIC_FMIN_RTN_64 = 0x00000022,
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TC_OP_ATOMIC_FMAX_RTN_64 = 0x00000023,
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TC_OP_RESERVED_FOP_RTN_64_0 = 0x00000024,
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TC_OP_RESERVED_FOP_RTN_64_1 = 0x00000025,
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TC_OP_RESERVED_FOP_RTN_64_2 = 0x00000026,
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TC_OP_ATOMIC_SWAP_RTN_64 = 0x00000027,
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TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028,
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TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029,
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TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a,
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TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b,
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TC_OP_WBINVL2_SD = 0x0000002c,
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TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x0000002d,
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TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x0000002e,
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TC_OP_ATOMIC_ADD_RTN_64 = 0x0000002f,
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TC_OP_ATOMIC_SUB_RTN_64 = 0x00000030,
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TC_OP_ATOMIC_SMIN_RTN_64 = 0x00000031,
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TC_OP_ATOMIC_UMIN_RTN_64 = 0x00000032,
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TC_OP_ATOMIC_SMAX_RTN_64 = 0x00000033,
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TC_OP_ATOMIC_UMAX_RTN_64 = 0x00000034,
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TC_OP_ATOMIC_AND_RTN_64 = 0x00000035,
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TC_OP_ATOMIC_OR_RTN_64 = 0x00000036,
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TC_OP_ATOMIC_XOR_RTN_64 = 0x00000037,
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TC_OP_ATOMIC_INC_RTN_64 = 0x00000038,
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TC_OP_ATOMIC_DEC_RTN_64 = 0x00000039,
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TC_OP_WBL2_NC = 0x0000003a,
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TC_OP_WBL2_WC = 0x0000003b,
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TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x0000003c,
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TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x0000003d,
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TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x0000003e,
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TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x0000003f,
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TC_OP_WBINVL1 = 0x00000040,
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TC_OP_ATOMIC_FCMPSWAP_32 = 0x00000041,
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TC_OP_ATOMIC_FMIN_32 = 0x00000042,
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TC_OP_ATOMIC_FMAX_32 = 0x00000043,
|
|
TC_OP_RESERVED_FOP_32_0 = 0x00000044,
|
|
TC_OP_RESERVED_FOP_32_2 = 0x00000046,
|
|
TC_OP_ATOMIC_SWAP_32 = 0x00000047,
|
|
TC_OP_ATOMIC_CMPSWAP_32 = 0x00000048,
|
|
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049,
|
|
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a,
|
|
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b,
|
|
TC_OP_INV_METADATA = 0x0000004c,
|
|
TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x0000004e,
|
|
TC_OP_ATOMIC_ADD_32 = 0x0000004f,
|
|
TC_OP_ATOMIC_SUB_32 = 0x00000050,
|
|
TC_OP_ATOMIC_SMIN_32 = 0x00000051,
|
|
TC_OP_ATOMIC_UMIN_32 = 0x00000052,
|
|
TC_OP_ATOMIC_SMAX_32 = 0x00000053,
|
|
TC_OP_ATOMIC_UMAX_32 = 0x00000054,
|
|
TC_OP_ATOMIC_AND_32 = 0x00000055,
|
|
TC_OP_ATOMIC_OR_32 = 0x00000056,
|
|
TC_OP_ATOMIC_XOR_32 = 0x00000057,
|
|
TC_OP_ATOMIC_INC_32 = 0x00000058,
|
|
TC_OP_ATOMIC_DEC_32 = 0x00000059,
|
|
TC_OP_INVL2_NC = 0x0000005a,
|
|
TC_OP_NOP_RTN0 = 0x0000005b,
|
|
TC_OP_RESERVED_NON_FLOAT_32_1 = 0x0000005c,
|
|
TC_OP_RESERVED_NON_FLOAT_32_2 = 0x0000005d,
|
|
TC_OP_RESERVED_NON_FLOAT_32_3 = 0x0000005e,
|
|
TC_OP_RESERVED_NON_FLOAT_32_4 = 0x0000005f,
|
|
TC_OP_WBINVL2 = 0x00000060,
|
|
TC_OP_ATOMIC_FCMPSWAP_64 = 0x00000061,
|
|
TC_OP_ATOMIC_FMIN_64 = 0x00000062,
|
|
TC_OP_ATOMIC_FMAX_64 = 0x00000063,
|
|
TC_OP_RESERVED_FOP_64_0 = 0x00000064,
|
|
TC_OP_RESERVED_FOP_64_1 = 0x00000065,
|
|
TC_OP_RESERVED_FOP_64_2 = 0x00000066,
|
|
TC_OP_ATOMIC_SWAP_64 = 0x00000067,
|
|
TC_OP_ATOMIC_CMPSWAP_64 = 0x00000068,
|
|
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069,
|
|
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a,
|
|
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b,
|
|
TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x0000006c,
|
|
TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x0000006d,
|
|
TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x0000006e,
|
|
TC_OP_ATOMIC_ADD_64 = 0x0000006f,
|
|
TC_OP_ATOMIC_SUB_64 = 0x00000070,
|
|
TC_OP_ATOMIC_SMIN_64 = 0x00000071,
|
|
TC_OP_ATOMIC_UMIN_64 = 0x00000072,
|
|
TC_OP_ATOMIC_SMAX_64 = 0x00000073,
|
|
TC_OP_ATOMIC_UMAX_64 = 0x00000074,
|
|
TC_OP_ATOMIC_AND_64 = 0x00000075,
|
|
TC_OP_ATOMIC_OR_64 = 0x00000076,
|
|
TC_OP_ATOMIC_XOR_64 = 0x00000077,
|
|
TC_OP_ATOMIC_INC_64 = 0x00000078,
|
|
TC_OP_ATOMIC_DEC_64 = 0x00000079,
|
|
TC_OP_WBINVL2_NC = 0x0000007a,
|
|
TC_OP_NOP_ACK = 0x0000007b,
|
|
TC_OP_RESERVED_NON_FLOAT_64_1 = 0x0000007c,
|
|
TC_OP_RESERVED_NON_FLOAT_64_2 = 0x0000007d,
|
|
TC_OP_RESERVED_NON_FLOAT_64_3 = 0x0000007e,
|
|
TC_OP_RESERVED_NON_FLOAT_64_4 = 0x0000007f,
|
|
TC_OP_RESERVED_FOP_RTN_32_1__GFX09_10 = 0x00000005,
|
|
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1__GFX09_10 = 0x0000000d,
|
|
TC_OP_RESERVED_FOP_32_1__GFX09_10 = 0x00000045,
|
|
TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1__GFX09_10 = 0x0000004d,
|
|
TC_OP_RESERVED_FADD_RTN_32__GFX11 = 0x00000005,
|
|
TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32__GFX11 = 0x0000000d,
|
|
TC_OP_RESERVED_FADD_32__GFX11 = 0x00000045,
|
|
TC_OP_ATOMIC_FADD_FLUSH_DENORM_32__GFX11 = 0x0000004d,
|
|
};
|
|
|
|
// Desc: Strucuture used to perform various atomic
|
|
// operations - add, subtract, increment, etc
|
|
struct AtomicTemplate {
|
|
PM4_MEC_ATOMIC_MEM atomic;
|
|
};
|
|
|
|
/// @brief PM4 command to write a 64-bit value into a memory
|
|
/// location accessible to Gpu
|
|
struct WriteDataTemplate {
|
|
PM4_MEC_WRITE_DATA write_data;
|
|
};
|
|
|
|
// ---------------------------------- MEC_COPY_DATA_src_sel_enum ----------------------------------
|
|
enum MEC_COPY_DATA_src_sel_enum {
|
|
src_sel__mec_copy_data__mem_mapped_register = 0,
|
|
src_sel__mec_copy_data__tc_l2_obsolete = 1,
|
|
src_sel__mec_copy_data__tc_l2 = 2,
|
|
src_sel__mec_copy_data__gds = 3,
|
|
src_sel__mec_copy_data__perfcounters = 4,
|
|
src_sel__mec_copy_data__immediate_data = 5,
|
|
src_sel__mec_copy_data__atomic_return_data = 6,
|
|
src_sel__mec_copy_data__gds_atomic_return_data0 = 7,
|
|
src_sel__mec_copy_data__gds_atomic_return_data1 = 8,
|
|
src_sel__mec_copy_data__gpu_clock_count = 9,
|
|
src_sel__mec_copy_data__system_clock_count = 10,
|
|
src_sel__mec_copy_data__ext32perfcntr = 11,
|
|
};
|
|
|
|
// ---------------------------------- MEC_COPY_DATA_dst_sel_enum ----------------------------------
|
|
enum MEC_COPY_DATA_dst_sel_enum {
|
|
dst_sel__mec_copy_data__mem_mapped_register = 0,
|
|
dst_sel__mec_copy_data__tc_l2 = 2,
|
|
dst_sel__mec_copy_data__gds = 3,
|
|
dst_sel__mec_copy_data__perfcounters = 4,
|
|
dst_sel__mec_copy_data__tc_l2_obsolete = 5,
|
|
dst_sel__mec_copy_data__mem_mapped_reg_dc = 6,
|
|
dst_sel__mec_copy_data__ext32perfcntr = 11,
|
|
};
|
|
|
|
// ------------------------------ MEC_COPY_DATA_src_cache_policy_enum ------------------------------
|
|
enum MEC_COPY_DATA_src_cache_policy_enum {
|
|
src_cache_policy__mec_copy_data__lru = 0,
|
|
src_cache_policy__mec_copy_data__stream = 1,
|
|
src_cache_policy__mec_copy_data__noa = 2,
|
|
src_cache_policy__mec_copy_data__bypass = 3,
|
|
};
|
|
|
|
// --------------------------------- MEC_COPY_DATA_count_sel_enum ---------------------------------
|
|
enum MEC_COPY_DATA_count_sel_enum {
|
|
count_sel__mec_copy_data__32_bits_of_data = 0,
|
|
count_sel__mec_copy_data__64_bits_of_data = 1,
|
|
};
|
|
|
|
// --------------------------------- MEC_COPY_DATA_wr_confirm_enum ---------------------------------
|
|
enum MEC_COPY_DATA_wr_confirm_enum {
|
|
wr_confirm__mec_copy_data__do_not_wait_for_confirmation = 0,
|
|
wr_confirm__mec_copy_data__wait_for_confirmation = 1,
|
|
};
|
|
|
|
// ------------------------------ MEC_COPY_DATA_dst_cache_policy_enum ------------------------------
|
|
enum MEC_COPY_DATA_dst_cache_policy_enum {
|
|
dst_cache_policy__mec_copy_data__lru = 0,
|
|
dst_cache_policy__mec_copy_data__stream = 1,
|
|
dst_cache_policy__mec_copy_data__noa = 2,
|
|
dst_cache_policy__mec_copy_data__bypass = 3,
|
|
};
|
|
|
|
// ------------------------------- MEC_COPY_DATA_pq_exe_status_enum -------------------------------
|
|
enum MEC_COPY_DATA_pq_exe_status_enum {
|
|
pq_exe_status__mec_copy_data__default = 0,
|
|
pq_exe_status__mec_copy_data__phase_update = 1,
|
|
};
|
|
|
|
// ------------------------------- MEC_WRITE_DATA_dst_sel_enum -------------------------------
|
|
enum MEC_WRITE_DATA_dst_sel_enum {
|
|
dst_sel__mec_write_data__mem_mapped_register = 0,
|
|
dst_sel__mec_write_data__tc_l2 = 2,
|
|
dst_sel__mec_write_data__gds = 3,
|
|
dst_sel__mec_write_data__memory = 5,
|
|
dst_sel__mec_write_data__memory_mapped_adc_persistent_state = 6 };
|
|
|
|
// ------------------------------- MEC_WRITE_DATA_addr_incr_enum -------------------------------
|
|
enum MEC_WRITE_DATA_addr_incr_enum {
|
|
addr_incr__mec_write_data__increment_address = 0,
|
|
addr_incr__mec_write_data__do_not_increment_address = 1 };
|
|
|
|
// ------------------------------- MEC_WRITE_DATA_wr_confirm_enum -------------------------------
|
|
enum MEC_WRITE_DATA_wr_confirm_enum {
|
|
wr_confirm__mec_write_data__do_not_wait_for_write_confirmation = 0,
|
|
wr_confirm__mec_write_data__wait_for_write_confirmation = 1 };
|
|
|
|
// ------------------------------- MEC_WRITE_DATA_cache_policy_enum -------------------------------
|
|
enum MEC_WRITE_DATA_cache_policy_enum {
|
|
cache_policy__mec_write_data__lru = 0,
|
|
cache_policy__mec_write_data__stream = 1,
|
|
cache_policy__mec_write_data__noa = 2,
|
|
cache_policy__mec_write_data__bypass = 3 };
|
|
|
|
typedef struct PM4_MEC_COPY_DATA {
|
|
union {
|
|
PM4_MEC_TYPE_3_HEADER header; /// header
|
|
uint32_t ordinal1;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t src_sel : 4;
|
|
uint32_t reserved1 : 4;
|
|
uint32_t dst_sel : 4;
|
|
uint32_t reserved2 : 1;
|
|
uint32_t src_cache_policy : 2;
|
|
uint32_t reserved3 : 1;
|
|
uint32_t count_sel : 1;
|
|
uint32_t reserved4 : 3;
|
|
uint32_t wr_confirm : 1;
|
|
uint32_t reserved5 : 4;
|
|
uint32_t dst_cache_policy : 2;
|
|
uint32_t reserved6 : 2;
|
|
uint32_t pq_exe_status : 1;
|
|
uint32_t reserved7 : 2;
|
|
} bitfields2;
|
|
uint32_t ordinal2;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t src_reg_offset : 18;
|
|
uint32_t reserved8 : 14;
|
|
} bitfields3a;
|
|
struct {
|
|
uint32_t reserved9 : 2;
|
|
uint32_t src_32b_addr_lo : 30;
|
|
} bitfields3b;
|
|
struct {
|
|
uint32_t reserved10 : 3;
|
|
uint32_t src_64b_addr_lo : 29;
|
|
} bitfields3c;
|
|
struct {
|
|
uint32_t src_gds_addr_lo : 16;
|
|
uint32_t reserved11 : 16;
|
|
} bitfields3d;
|
|
uint32_t imm_data;
|
|
uint32_t ordinal3;
|
|
};
|
|
union {
|
|
uint32_t src_memtc_addr_hi;
|
|
uint32_t src_imm_data;
|
|
uint32_t ordinal4;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t dst_reg_offset : 18;
|
|
uint32_t reserved12 : 14;
|
|
} bitfields5a;
|
|
struct {
|
|
uint32_t reserved13 : 2;
|
|
uint32_t dst_32b_addr_lo : 30;
|
|
} bitfields5b;
|
|
struct {
|
|
uint32_t reserved14 : 3;
|
|
uint32_t dst_64b_addr_lo : 29;
|
|
} bitfields5c;
|
|
struct {
|
|
uint32_t dst_gds_addr_lo : 16;
|
|
uint32_t reserved15 : 16;
|
|
} bitfields5d;
|
|
uint32_t ordinal5;
|
|
};
|
|
uint32_t dst_addr_hi;
|
|
} PM4MEC_COPY_DATA;
|
|
namespace gfx9 {
|
|
|
|
struct PM4_MEC_ACQUIRE_MEM {
|
|
union {
|
|
PM4_MEC_TYPE_3_HEADER header;
|
|
uint32_t ordinal1;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t coher_cntl:31;
|
|
uint32_t reserved1:1;
|
|
} bitfields2;
|
|
uint32_t ordinal2;
|
|
};
|
|
uint32_t coher_size;
|
|
union {
|
|
struct {
|
|
uint32_t coher_size_hi:8;
|
|
uint32_t reserved2:24;
|
|
} bitfields4;
|
|
uint32_t ordinal4;
|
|
};
|
|
uint32_t coher_base_lo;
|
|
union {
|
|
struct {
|
|
uint32_t coher_base_hi:24;
|
|
uint32_t reserved3:8;
|
|
} bitfields6;
|
|
uint32_t ordinal6;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t poll_interval:16;
|
|
uint32_t reserved4:16;
|
|
} bitfields7;
|
|
uint32_t ordinal7;
|
|
};
|
|
};
|
|
|
|
struct PM4_MEC_RELEASE_MEM {
|
|
union {
|
|
PM4_MEC_TYPE_3_HEADER header;
|
|
uint32_t ordinal1;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t event_type:6;
|
|
uint32_t reserved1:2;
|
|
uint32_t event_index:4;
|
|
uint32_t tcl1_vol_action_ena:1;
|
|
uint32_t tc_vol_action_ena:1;
|
|
uint32_t reserved2:1;
|
|
uint32_t tc_wb_action_ena:1;
|
|
uint32_t tcl1_action_ena:1;
|
|
uint32_t tc_action_ena:1;
|
|
uint32_t reserved3:1;
|
|
uint32_t tc_nc_action_ena:1;
|
|
uint32_t tc_wc_action_ena:1;
|
|
uint32_t tc_md_action_ena:1;
|
|
uint32_t reserved4:3;
|
|
uint32_t cache_policy:2;
|
|
uint32_t reserved5:2;
|
|
uint32_t pq_exe_status:1;
|
|
uint32_t reserved6:2;
|
|
} bitfields2;
|
|
uint32_t ordinal2;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t reserved7:16;
|
|
uint32_t dst_sel:2;
|
|
uint32_t reserved8:6;
|
|
uint32_t int_sel:3;
|
|
uint32_t reserved9:2;
|
|
uint32_t data_sel:3;
|
|
} bitfields3;
|
|
uint32_t ordinal3;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t reserved10:2;
|
|
uint32_t address_lo_32b:30;
|
|
} bitfields4a;
|
|
struct {
|
|
uint32_t reserved11:3;
|
|
uint32_t address_lo_64b:29;
|
|
} bitfields4b;
|
|
uint32_t reserved12;
|
|
uint32_t ordinal4;
|
|
};
|
|
union {
|
|
uint32_t address_hi;
|
|
uint32_t reserved13;
|
|
uint32_t ordinal5;
|
|
};
|
|
union {
|
|
uint32_t data_lo;
|
|
uint32_t cmp_data_lo;
|
|
struct {
|
|
uint32_t dw_offset:16;
|
|
uint32_t num_dwords:16;
|
|
} bitfields6c;
|
|
uint32_t reserved14;
|
|
uint32_t ordinal6;
|
|
};
|
|
union {
|
|
uint32_t data_hi;
|
|
uint32_t cmp_data_hi;
|
|
uint32_t reserved15;
|
|
uint32_t reserved16;
|
|
uint32_t ordinal7;
|
|
};
|
|
uint32_t int_ctxid;
|
|
};
|
|
|
|
struct PM4_MEC_WAIT_REG_MEM64 {
|
|
union {
|
|
PM4_MEC_TYPE_3_HEADER header;
|
|
uint32_t ordinal1;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t function:3;
|
|
uint32_t reserved1:1;
|
|
uint32_t mem_space:2;
|
|
uint32_t operation:2;
|
|
uint32_t reserved2:24;
|
|
} bitfields2;
|
|
uint32_t ordinal2;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t reserved3:3;
|
|
uint32_t mem_poll_addr_lo:29;
|
|
} bitfields3a;
|
|
struct {
|
|
uint32_t reg_poll_addr:18;
|
|
uint32_t reserved4:14;
|
|
} bitfields3b;
|
|
struct {
|
|
uint32_t reg_write_addr1:18;
|
|
uint32_t reserved5:14;
|
|
} bitfields3c;
|
|
uint32_t ordinal3;
|
|
};
|
|
union {
|
|
uint32_t mem_poll_addr_hi;
|
|
struct {
|
|
uint32_t reg_write_addr2:18;
|
|
uint32_t reserved6:14;
|
|
} bitfields4b;
|
|
uint32_t ordinal4;
|
|
};
|
|
uint32_t reference;
|
|
uint32_t reference_hi;
|
|
uint32_t mask;
|
|
uint32_t mask_hi;
|
|
union {
|
|
struct {
|
|
uint32_t poll_interval:16;
|
|
uint32_t reserved7:16;
|
|
} bitfields9;
|
|
uint32_t ordinal9;
|
|
};
|
|
};
|
|
|
|
/// @brief Structure used to configure the flushing of
|
|
/// various caches - instruction, constants, L1 and L2
|
|
struct AcquireMemTemplate {
|
|
PM4_MEC_ACQUIRE_MEM acquire_mem;
|
|
};
|
|
|
|
struct EndofKernelNotifyTemplate {
|
|
PM4_MEC_RELEASE_MEM release_mem;
|
|
};
|
|
|
|
/// @brief PM4 command to wait for a certain event before proceeding
|
|
/// to process another command on the queue
|
|
struct WaitRegMem64Template {
|
|
PM4_MEC_WAIT_REG_MEM64 wait_reg_mem;
|
|
};
|
|
|
|
} // gfx9 namespace
|
|
|
|
namespace gfx10 {
|
|
|
|
struct PM4_MEC_ACQUIRE_MEM {
|
|
union {
|
|
PM4_MEC_TYPE_3_HEADER header;
|
|
uint32_t ordinal1;
|
|
};
|
|
uint32_t reserved1;
|
|
uint32_t coher_size;
|
|
union {
|
|
struct {
|
|
uint32_t coher_size_hi:8;
|
|
uint32_t reserved2:24;
|
|
} bitfields4;
|
|
uint32_t ordinal4;
|
|
};
|
|
uint32_t coher_base_lo;
|
|
union {
|
|
struct {
|
|
uint32_t coher_base_hi:24;
|
|
uint32_t reserved3:8;
|
|
} bitfields6;
|
|
uint32_t ordinal6;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t poll_interval:16;
|
|
uint32_t reserved4:16;
|
|
} bitfields7;
|
|
uint32_t ordinal7;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t gcr_cntl:19;
|
|
uint32_t reserved4:13;
|
|
} bitfields8;
|
|
uint32_t ordinal8;
|
|
};
|
|
};
|
|
|
|
struct PM4_MEC_RELEASE_MEM {
|
|
union {
|
|
PM4_MEC_TYPE_3_HEADER header;
|
|
uint32_t ordinal1;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t event_type:6;
|
|
uint32_t reserved1:2;
|
|
uint32_t event_index:4;
|
|
uint32_t gcr_cntl:12;
|
|
uint32_t reserved2:1;
|
|
uint32_t cache_policy:2;
|
|
uint32_t reserved3:2;
|
|
uint32_t pq_exe_status:1;
|
|
uint32_t reserved4:2;
|
|
} bitfields2;
|
|
uint32_t ordinal2;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t reserved7:16;
|
|
uint32_t dst_sel:2;
|
|
uint32_t reserved8:2;
|
|
uint32_t mes_intr_pipe:2;
|
|
uint32_t mes_action_id:2;
|
|
uint32_t int_sel:3;
|
|
uint32_t reserved9:2;
|
|
uint32_t data_sel:3;
|
|
} bitfields3;
|
|
uint32_t ordinal3;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t reserved10:2;
|
|
uint32_t address_lo_32b:30;
|
|
} bitfields4a;
|
|
struct {
|
|
uint32_t reserved11:3;
|
|
uint32_t address_lo_64b:29;
|
|
} bitfields4b;
|
|
uint32_t reserved12;
|
|
uint32_t ordinal4;
|
|
};
|
|
union {
|
|
uint32_t address_hi;
|
|
uint32_t reserved13;
|
|
uint32_t ordinal5;
|
|
};
|
|
union {
|
|
uint32_t data_lo;
|
|
uint32_t cmp_data_lo;
|
|
struct {
|
|
uint32_t dw_offset:16;
|
|
uint32_t num_dwords:16;
|
|
} bitfields6c;
|
|
uint32_t reserved14;
|
|
uint32_t ordinal6;
|
|
};
|
|
union {
|
|
uint32_t data_hi;
|
|
uint32_t cmp_data_hi;
|
|
uint32_t reserved15;
|
|
uint32_t reserved16;
|
|
uint32_t ordinal7;
|
|
};
|
|
uint32_t int_ctxid;
|
|
};
|
|
|
|
struct PM4_MEC_WAIT_REG_MEM64 {
|
|
union {
|
|
PM4_MEC_TYPE_3_HEADER header; ///header
|
|
uint32_t ordinal1;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t function:3;
|
|
uint32_t reserved1:1;
|
|
uint32_t mem_space:2;
|
|
uint32_t operation:2;
|
|
uint32_t reserved2:14;
|
|
uint32_t mes_intr_pipe:2;
|
|
uint32_t mes_action:1;
|
|
uint32_t cache_policy:2;
|
|
uint32_t reserved3:5;
|
|
} bitfields2;
|
|
uint32_t ordinal2;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t reserved4:3;
|
|
uint32_t mem_poll_addr_lo:29;
|
|
} bitfields3a;
|
|
struct {
|
|
uint32_t reg_poll_addr:18;
|
|
uint32_t reserved5:14;
|
|
} bitfields3b;
|
|
struct {
|
|
uint32_t reg_write_addr1:18;
|
|
uint32_t reserved6:14;
|
|
} bitfields3c;
|
|
uint32_t ordinal3;
|
|
};
|
|
union {
|
|
uint32_t mem_poll_addr_hi;
|
|
struct {
|
|
uint32_t reg_write_addr2:18;
|
|
uint32_t reserved7:14;
|
|
} bitfields4b;
|
|
uint32_t ordinal4;
|
|
};
|
|
uint32_t reference;
|
|
uint32_t reference_hi;
|
|
uint32_t mask;
|
|
uint32_t mask_hi;
|
|
union {
|
|
struct {
|
|
uint32_t poll_interval:16;
|
|
uint32_t reserved8:15;
|
|
uint32_t optimize_ace_offload_mode:1;
|
|
} bitfields9;
|
|
uint32_t ordinal9;
|
|
};
|
|
};
|
|
|
|
/// @brief Structure used to configure the flushing of
|
|
/// various caches - instruction, constants, L1 and L2
|
|
struct AcquireMemTemplate {
|
|
PM4_MEC_ACQUIRE_MEM acquire_mem;
|
|
};
|
|
|
|
struct EndofKernelNotifyTemplate {
|
|
PM4_MEC_RELEASE_MEM release_mem;
|
|
};
|
|
|
|
struct WaitRegMem64Template {
|
|
PM4_MEC_WAIT_REG_MEM64 wait_reg_mem;
|
|
};
|
|
|
|
} // gfx10 namespace
|
|
|
|
namespace gfx11 {
|
|
|
|
struct PM4_MEC_RELEASE_MEM {
|
|
union {
|
|
PM4_MEC_TYPE_3_HEADER header;
|
|
uint32_t ordinal1;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t event_type:6;
|
|
uint32_t reserved1:2;
|
|
uint32_t event_index:4;
|
|
uint32_t gcr_cntl:13;
|
|
uint32_t cache_policy:2;
|
|
uint32_t reserved2:1;
|
|
uint32_t pq_exe_status:1;
|
|
uint32_t reserved3:1;
|
|
uint32_t glk_inv:1;
|
|
uint32_t reserved4:1;
|
|
} bitfields2;
|
|
uint32_t ordinal2;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t reserved5:16;
|
|
uint32_t dst_sel:2;
|
|
uint32_t reserved6:2;
|
|
uint32_t mes_intr_pipe:2;
|
|
uint32_t mes_action_id:2;
|
|
uint32_t int_sel:3;
|
|
uint32_t reserved7:2;
|
|
uint32_t data_sel:3;
|
|
} bitfields3;
|
|
uint32_t ordinal3;
|
|
};
|
|
union {
|
|
struct {
|
|
uint32_t reserved8:2;
|
|
uint32_t address_lo_32b:30;
|
|
} bitfields4a;
|
|
struct {
|
|
uint32_t reserved9:3;
|
|
uint32_t address_lo_64b:29;
|
|
} bitfields4b;
|
|
uint32_t reserved10;
|
|
uint32_t ordinal4;
|
|
};
|
|
union {
|
|
uint32_t address_hi;
|
|
uint32_t reserved11;
|
|
uint32_t ordinal5;
|
|
};
|
|
union {
|
|
uint32_t data_lo;
|
|
uint32_t cmp_data_lo;
|
|
struct {
|
|
uint32_t dw_offset:16;
|
|
uint32_t num_dwords:16;
|
|
} bitfields6c;
|
|
uint32_t reserved12;
|
|
uint32_t ordinal6;
|
|
};
|
|
union {
|
|
uint32_t data_hi;
|
|
uint32_t cmp_data_hi;
|
|
uint32_t reserved13;
|
|
uint32_t reserved14;
|
|
uint32_t ordinal7;
|
|
};
|
|
uint32_t int_ctxid;
|
|
};
|
|
|
|
struct EndofKernelNotifyTemplate {
|
|
PM4_MEC_RELEASE_MEM release_mem;
|
|
};
|
|
|
|
} // gfx11 namespace
|
|
|
|
#endif
|