Pengda Xie
434 righe
13 KiB
C++
434 righe
13 KiB
C++
/* Copyright (c) 2015 - 2021 Advanced Micro Devices, Inc.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE. */
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#include "top.hpp"
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#include "os/os.hpp"
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#include "device/device.hpp"
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#include "device/pal/paldefs.hpp"
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#include "device/pal/palsettings.hpp"
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#include <algorithm>
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#if defined(_WIN32)
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#include "Windows.h"
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#include "VersionHelpers.h"
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#endif
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namespace amd::pal {
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Settings::Settings() {
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// Initialize the GPU device default settings
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oclVersion_ = OpenCL12;
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debugFlags_ = 0;
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remoteAlloc_ = REMOTE_ALLOC;
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stagedXferRead_ = true;
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stagedXferWrite_ = true;
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stagedXferSize_ = GPU_STAGING_BUFFER_SIZE * Mi;
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// We will enable staged read/write if we use local memory
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disablePersistent_ = false;
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imageSupport_ = false;
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hwLDSSize_ = 0;
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// Set this to true when we drop the flag
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doublePrecision_ = ::CL_KHR_FP64;
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// Fill workgroup info size
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maxWorkGroupSize_ = 1024;
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preferredWorkGroupSize_ = 256;
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hostMemDirectAccess_ = HostMemDisable;
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libSelector_ = amd::LibraryUndefined;
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// By default use host blit
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blitEngine_ = BlitEngineHost;
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pinnedXferSize_ = GPU_PINNED_XFER_SIZE * Mi;
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size_t defaultMinXferSize = amd::IS_HIP ? 128 : 4;
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pinnedMinXferSize_ = flagIsDefault(GPU_PINNED_MIN_XFER_SIZE) ? defaultMinXferSize * Mi
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: GPU_PINNED_MIN_XFER_SIZE * Mi;
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// GPU device by default
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apuSystem_ = false;
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// Disable 64 bit pointers support by default
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use64BitPtr_ = false;
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// Max alloc size is 16GB
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maxAllocSize_ = 16 * static_cast<uint64_t>(Gi);
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// Disable memory dependency tracking by default
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numMemDependencies_ = 0;
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// By default cache isn't present
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cacheLineSize_ = 0;
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cacheSize_ = 0;
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// Initialize transfer buffer size to 1MB by default
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xferBufSize_ = 1024 * Ki;
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// Use image DMA if requested
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imageDMA_ = GPU_IMAGE_DMA;
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// Number of compute rings.
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numComputeRings_ = 0;
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// Device enqueuing settings
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numDeviceEvents_ = 1024;
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numWaitEvents_ = 8;
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numScratchWavesPerCu_ = 32;
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// Don't support platform atomics by default.
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svmAtomics_ = false;
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// Use host queue for device enqueuing by default
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useDeviceQueue_ = GPU_USE_DEVICE_QUEUE;
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// Don't support Denormals for single precision by default
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singleFpDenorm_ = false;
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// SQTT buffer size in bytes
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rgpSqttDispCount_ = PAL_RGP_DISP_COUNT;
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rgpSqttWaitIdle_ = true;
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rgpSqttForceDisable_ = false;
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// Sub allocation parameters
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subAllocationMinSize_ = 4 * Ki;
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subAllocationChunkSize_ = 64 * Mi;
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subAllocationMaxSize_ =
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std::min(static_cast<uint64_t>(GPU_MAX_SUBALLOC_SIZE) * Ki, subAllocationChunkSize_);
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maxCmdBuffers_ = 12;
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enableWgpMode_ = false;
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enableWave32Mode_ = false;
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lcWavefrontSize64_ = true;
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enableHwP2P_ = false;
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imageBufferWar_ = false;
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disableSdma_ = PAL_DISABLE_SDMA;
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mallPolicy_ = 0;
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alwaysResident_ = amd::IS_HIP ? true : false;
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prepinnedMinSize_ = 0;
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cpDmaCopySizeMax_ = GPU_CP_DMA_COPY_SIZE * Ki;
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kernel_arg_impl_ = flagIsDefault(HIP_FORCE_DEV_KERNARG) ? KernelArgImpl::DeviceKernelArgs
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: HIP_FORCE_DEV_KERNARG;
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limit_blit_wg_ = 16;
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DEBUG_CLR_GRAPH_PACKET_CAPTURE = false; // disable graph performance optimizations for PAL
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}
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bool Settings::create(const Pal::DeviceProperties& palProp,
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const Pal::GpuMemoryHeapProperties* heaps, const Pal::WorkStationCaps& wscaps,
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const amd::Isa& isa, bool reportAsOCL12Device) {
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uint32_t osVer = 0x0;
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// Disable thread trace by default for all devices
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threadTraceEnable_ = false;
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// APU systems
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if (palProp.gpuType == Pal::GpuType::Integrated) {
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apuSystem_ = true;
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}
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enableXNACK_ = (isa.xnack() == amd::Isa::Feature::Enabled);
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bool useWavefront64 = false;
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std::string appName = {};
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std::string appPathAndName = {};
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amd::Os::getAppPathAndFileName(appName, appPathAndName);
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switch (palProp.revision) {
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// Fall through for Navi4x ...
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case Pal::AsicRevision::Navi44:
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case Pal::AsicRevision::Navi48:
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// Fall through for Navi3x ...
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case Pal::AsicRevision::Navi33:
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case Pal::AsicRevision::Navi32:
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case Pal::AsicRevision::Navi31:
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gwsInitSupported_ = false;
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// Fall through for Navi2x ...
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case Pal::AsicRevision::StrixHalo:
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case Pal::AsicRevision::Strix1:
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case Pal::AsicRevision::Phoenix1:
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case Pal::AsicRevision::Phoenix2:
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case Pal::AsicRevision::HawkPoint1:
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case Pal::AsicRevision::HawkPoint2:
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case Pal::AsicRevision::Raphael:
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case Pal::AsicRevision::Rembrandt:
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case Pal::AsicRevision::Navi24:
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case Pal::AsicRevision::Navi23:
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case Pal::AsicRevision::Navi22:
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case Pal::AsicRevision::Navi21:
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// set wavefront 64 for Geekbench 5
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{
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if (appName == "Geekbench 5.exe" || appName == "geekbench_x86_64.exe" ||
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appName == "geekbench5.exe") {
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useWavefront64 = true;
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}
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}
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// Fall through for Navi1x ...
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case Pal::AsicRevision::Navi14:
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case Pal::AsicRevision::Navi12:
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case Pal::AsicRevision::Navi10:
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enableWgpMode_ = GPU_ENABLE_WGP_MODE;
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enableWave32Mode_ = true;
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if (!flagIsDefault(GPU_ENABLE_WAVE32_MODE)) {
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enableWave32Mode_ = GPU_ENABLE_WAVE32_MODE;
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}
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if (useWavefront64) {
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enableWave32Mode_ = 0;
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}
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lcWavefrontSize64_ = !enableWave32Mode_;
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if (palProp.gfxLevel == Pal::GfxIpLevel::GfxIp10_1) {
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// GFX10.1 HW doesn't support custom pitch. Enable double copy workaround
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imageBufferWar_ = GPU_IMAGE_BUFFER_WAR;
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}
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enableHwP2P_ = true;
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enableCoopGroups_ = IS_LINUX;
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enableCoopMultiDeviceGroups_ = IS_LINUX;
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singleFpDenorm_ = true;
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enableExtension(ClKhrFp16);
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threadTraceEnable_ = AMD_THREAD_TRACE_ENABLE;
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// Cache line size is 64 bytes
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cacheLineSize_ = 64;
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// L1 cache size is 16KB
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cacheSize_ = 16 * Ki;
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libSelector_ = amd::GPU_Library_CI;
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if (LP64_SWITCH(false, true)) {
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oclVersion_ =
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!reportAsOCL12Device ? XCONCAT(OpenCL, XCONCAT(OPENCL_MAJOR, OPENCL_MINOR)) : OpenCL12;
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}
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if (OPENCL_VERSION < 200) {
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oclVersion_ = OpenCL12;
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}
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numComputeRings_ = 8;
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// Cap at OpenCL20 for now
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if (oclVersion_ > OpenCL20) oclVersion_ = OpenCL20;
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use64BitPtr_ = LP64_SWITCH(false, true);
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if (oclVersion_ >= OpenCL20) {
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supportDepthsRGB_ = true;
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}
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if (use64BitPtr_) {
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maxAllocSize_ = 64ULL * Gi;
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} else {
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maxAllocSize_ = 3ULL * Gi;
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}
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supportRA_ = false;
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numMemDependencies_ = GPU_NUM_MEM_DEPENDENCY;
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break;
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default:
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assert(0 && "Unknown ASIC type!");
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return false;
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}
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if (0 == palProp.engineProperties[Pal::EngineTypeDma].engineCount) {
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disableSdma_ = true;
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}
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// Image DMA must be disabled if SDMA is disabled
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imageDMA_ &= !disableSdma_;
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// Enable atomics support
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enableExtension(ClKhrInt64BaseAtomics);
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enableExtension(ClKhrInt64ExtendedAtomics);
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enableExtension(ClKhrGlobalInt32BaseAtomics);
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enableExtension(ClKhrGlobalInt32ExtendedAtomics);
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enableExtension(ClKhrLocalInt32BaseAtomics);
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enableExtension(ClKhrLocalInt32ExtendedAtomics);
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enableExtension(ClKhrByteAddressableStore);
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enableExtension(ClKhr3DImageWrites);
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enableExtension(ClKhrImage2dFromBuffer);
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enableExtension(ClAmdMediaOps);
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enableExtension(ClAmdMediaOps2);
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{
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// Not supported by Unknown device
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enableExtension(ClKhrGlSharing);
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enableExtension(ClKhrGlEvent);
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enableExtension(ClAmdCopyBufferP2P);
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}
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// Enable some platform extensions
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enableExtension(ClAmdDeviceAttributeQuery);
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if (hwLDSSize_ == 0) {
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// Use hardcoded values for now, since PAL properties aren't available with offline devices
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hwLDSSize_ = (IS_LINUX || amd::IS_HIP) ? 64 * Ki : 32 * Ki;
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}
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imageSupport_ = true;
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// Use kernels for blit if appropriate
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blitEngine_ = BlitEngineKernel;
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hostMemDirectAccess_ |= HostMemBuffer;
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// HW doesn't support untiled image writes
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// hostMemDirectAccess_ |= HostMemImage;
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if (doublePrecision_) {
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// Enable KHR double precision extension
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enableExtension(ClKhrFp64);
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}
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if (palProp.gpuMemoryProperties.busAddressableMemSize > 0) {
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// Enable bus addressable memory extension
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enableExtension(ClAMDBusAddressableMemory);
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}
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svmFineGrainSystem_ = palProp.gpuMemoryProperties.flags.iommuv2Support;
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svmAtomics_ = svmFineGrainSystem_;
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// SVM is not currently supported for DX Interop
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#if defined(_WIN32)
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enableExtension(ClKhrD3d9Sharing);
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enableExtension(ClKhrD3d10Sharing);
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enableExtension(ClKhrD3d11Sharing);
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#endif // _WIN32
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// Enable some OpenCL 2.0 extensions
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if (oclVersion_ >= OpenCL20) {
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enableExtension(ClKhrSubGroups);
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enableExtension(ClKhrDepthImages);
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if (GPU_MIPMAP && imageSupport_) {
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enableExtension(ClKhrMipMapImage);
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enableExtension(ClKhrMipMapImageWrites);
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}
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#if defined(_WIN32)
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enableExtension(ClAmdPlanarYuv);
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#endif
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}
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if (apuSystem_ && ((heaps[Pal::GpuHeapLocal].logicalSize +
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heaps[Pal::GpuHeapInvisible].logicalSize) < (150 * Mi))) {
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remoteAlloc_ = true;
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}
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// Update resource cache size
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if (remoteAlloc_) {
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resourceCacheSize_ = std::max((heaps[Pal::GpuHeapGartUswc].logicalSize / 8),
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(uint64_t)GPU_RESOURCE_CACHE_SIZE * Mi);
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} else {
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if (apuSystem_) {
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resourceCacheSize_ = std::max(
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((heaps[Pal::GpuHeapLocal].logicalSize + heaps[Pal::GpuHeapInvisible].logicalSize +
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heaps[Pal::GpuHeapGartUswc].logicalSize) /
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8),
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(uint64_t)GPU_RESOURCE_CACHE_SIZE * Mi);
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} else {
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resourceCacheSize_ = std::max(
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((heaps[Pal::GpuHeapLocal].logicalSize + heaps[Pal::GpuHeapInvisible].logicalSize) / 8),
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(uint64_t)GPU_RESOURCE_CACHE_SIZE * Mi);
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}
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#if !defined(_LP64)
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resourceCacheSize_ = std::min(resourceCacheSize_, 1 * Gi);
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#endif
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}
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// If is Rebar, override prepinned memory size.
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if ((heaps[Pal::GpuHeapInvisible].logicalSize == 0) &&
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(heaps[Pal::GpuHeapLocal].logicalSize > 256 * Mi)) {
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prepinnedMinSize_ = PAL_PREPINNED_MEMORY_SIZE * Ki;
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}
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limit_blit_wg_ = enableWgpMode_ ? palProp.gfxipProperties.shaderCore.numAvailableCus / 2
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: palProp.gfxipProperties.shaderCore.numAvailableCus;
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// Override current device settings
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override();
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return true;
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}
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void Settings::override() {
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// Limit reported workgroup size
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if (GPU_MAX_WORKGROUP_SIZE != 0) {
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preferredWorkGroupSize_ = GPU_MAX_WORKGROUP_SIZE;
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}
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// Override blit engine type
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if (GPU_BLIT_ENGINE_TYPE != BlitEngineDefault) {
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blitEngine_ = GPU_BLIT_ENGINE_TYPE;
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}
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if (!flagIsDefault(DEBUG_GPU_FLAGS)) {
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debugFlags_ = DEBUG_GPU_FLAGS;
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}
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if (!flagIsDefault(GPU_XFER_BUFFER_SIZE)) {
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xferBufSize_ = GPU_XFER_BUFFER_SIZE * Ki;
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}
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if (!flagIsDefault(GPU_NUM_COMPUTE_RINGS)) {
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numComputeRings_ = GPU_NUM_COMPUTE_RINGS;
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}
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if (!flagIsDefault(GPU_RESOURCE_CACHE_SIZE)) {
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resourceCacheSize_ = GPU_RESOURCE_CACHE_SIZE * Mi;
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}
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if (!flagIsDefault(GPU_ENABLE_HW_P2P)) {
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enableHwP2P_ = GPU_ENABLE_HW_P2P;
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}
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if (!flagIsDefault(AMD_GPU_FORCE_SINGLE_FP_DENORM)) {
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switch (AMD_GPU_FORCE_SINGLE_FP_DENORM) {
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case 0:
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singleFpDenorm_ = false;
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break;
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case 1:
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singleFpDenorm_ = true;
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break;
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default:
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break;
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}
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}
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if (!flagIsDefault(GPU_MAX_COMMAND_BUFFERS)) {
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maxCmdBuffers_ = GPU_MAX_COMMAND_BUFFERS;
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}
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if (!flagIsDefault(GPU_ENABLE_COOP_GROUPS)) {
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enableCoopGroups_ = GPU_ENABLE_COOP_GROUPS;
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enableCoopMultiDeviceGroups_ = GPU_ENABLE_COOP_GROUPS;
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}
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if (!flagIsDefault(PAL_MALL_POLICY)) {
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mallPolicy_ = PAL_MALL_POLICY;
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}
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if (!flagIsDefault(PAL_ALWAYS_RESIDENT)) {
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alwaysResident_ = PAL_ALWAYS_RESIDENT;
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}
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if (!flagIsDefault(DEBUG_CLR_LIMIT_BLIT_WG)) {
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limit_blit_wg_ = std::max(DEBUG_CLR_LIMIT_BLIT_WG, 0x1U);
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}
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}
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} // namespace amd::pal
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