foreman
fde741c2b4
SWDEV-189990, SWDEV-190337 - Update OpenCL/PAL gfx10 counter blocks again to match GPUPerfAPI. SWDEV-190337: - Update the GFX10 block list (gfx10BlockIsPal) to match GPUPerfAPI, which expects the OpenCL block lists to match OpenGL (UGL). Note: The list now matches the expectations of GPUPerfAPI. For TA/TD/TCP, nearly all GFX10 ASICs only require 10 or 12 instances (Arden would require 14, Mero would require 8, but not sure if those are supported by OCL), but we are using 16 instances to match UGL. - Make sure the blockIdToIndexSelect array contains all the blocks supported by PAL (add a static_assert to ensure this) - Refactor the PCIndexSelect enum. This enum is used to determine how to sum up counters across multiple block instances. The following types are now supported: Instance -- no autosumming; instances have a one-to-one correlation with PAL ShaderEngine -- the block is instanced per shader engine, and OpenCL will autosum counters across all PAL instances, providing a single value for all of PAL's instances ShaderArray -- the block is instanced per shader array, and OpenCL will autosum counters across shader arrays, providing a single value for each instance within a shader array. For example, if a block has four instances per shader array, PAL would expose 16 instances total on Navi10 (2 SEs, 2 SAs per SE), but OpenCL will expose four instances ComputeUnit -- the block is instanced per compute unit, and OpenCL will autosum counters across shader arrays, providing a single value for each compute-unit-per-shader-array. For example, if a block is instanced per compute unit, then PAL would expose 40 instances on a 40CU Navi10. OpenCL would support 10 instances (2 CUs-per-WGP, 5 WGPs-per-SA), autosummed across shader arrays. SWDEV-189990: - Revert GFX9 and GFX10 tests back to using the MCVML2 counter it was using previously (prior to CL 1766829). This is counter index 2, which the test calls "BigK bank 0 hits". In the aforementioned change list, I updated the counter index from 2 to 14, since index 14 is the actual counter that represents "BigK bank 0 hits". Counter index 2 is the number of hits, not "bigK" hits. This previous change caused a test regression reported in SWDEV-189990. By reverting the code to use counter 2, the expected value in the test should be correct. Perhaps a better update would be to change the description in the source from "BigK bank 0 hits" to "bank 0 hits", but for now, I'm just going to go back to what the test was doing before. Affected files ... ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palcounters.cpp#21 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palcounters.hpp#11 edit ... //depot/stg/opencl/drivers/opencl/tests/ocltst/module/runtime/OCLPerfCounters.cpp#47 edit
792 lines
26 KiB
C++
792 lines
26 KiB
C++
//
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// Copyright (c) 2015 Advanced Micro Devices, Inc. All rights reserved.
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//
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#include "device/pal/palcounters.hpp"
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#include "device/pal/palvirtual.hpp"
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#include <array>
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namespace pal {
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PalCounterReference* PalCounterReference::Create(VirtualGPU& gpu) {
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Pal::Result result;
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// Create performance experiment
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Pal::PerfExperimentCreateInfo createInfo = {};
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createInfo.optionFlags.sampleInternalOperations = 1;
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createInfo.optionFlags.cacheFlushOnCounterCollection = 1;
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createInfo.optionFlags.sqShaderMask = 1;
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createInfo.optionValues.sampleInternalOperations = true;
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createInfo.optionValues.cacheFlushOnCounterCollection = true;
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createInfo.optionValues.sqShaderMask = Pal::PerfShaderMaskCs;
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size_t palExperSize = gpu.dev().iDev()->GetPerfExperimentSize(createInfo, &result);
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if (result != Pal::Result::Success) {
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return nullptr;
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}
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PalCounterReference* memRef = new (palExperSize) PalCounterReference(gpu);
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if (memRef != nullptr) {
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result = gpu.dev().iDev()->CreatePerfExperiment(createInfo, &memRef[1], &memRef->perfExp_);
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if (result != Pal::Result::Success) {
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memRef->release();
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return nullptr;
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}
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}
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return memRef;
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}
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PalCounterReference::~PalCounterReference() {
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// The counter object is always associated with a particular queue,
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// so we have to lock just this queue
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amd::ScopedLock lock(gpu_.execution());
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if (layout_ != nullptr) {
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delete layout_;
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}
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if (memory_ != nullptr) {
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delete memory_;
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}
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if (nullptr != iPerf()) {
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iPerf()->Destroy();
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}
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}
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uint64_t PalCounterReference::result(const std::vector<int>& index) {
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if (index.size() == 0) {
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// These are counters that have no corresponding PalSample created
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return 0;
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}
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if (layout_ == nullptr) {
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return 0;
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}
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uint64_t result = 0;
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for (auto const& i : index) {
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assert(i <= static_cast<int>(layout_->sampleCount) && "index not in range");
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const Pal::GlobalSampleLayout& sample = layout_->samples[i];
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if (sample.dataType == Pal::PerfCounterDataType::Uint32) {
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uint32_t beginVal =
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*reinterpret_cast<uint32_t*>(reinterpret_cast<char*>(cpuAddr_) + sample.beginValueOffset);
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uint32_t endVal =
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*reinterpret_cast<uint32_t*>(reinterpret_cast<char*>(cpuAddr_) + sample.endValueOffset);
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result += (endVal - beginVal);
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} else if (sample.dataType == Pal::PerfCounterDataType::Uint64) {
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uint64_t beginVal =
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*reinterpret_cast<uint64_t*>(reinterpret_cast<char*>(cpuAddr_) + sample.beginValueOffset);
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uint64_t endVal =
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*reinterpret_cast<uint64_t*>(reinterpret_cast<char*>(cpuAddr_) + sample.endValueOffset);
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result += (endVal - beginVal);
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} else {
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assert(0 && "dataType should be either Uint32 or Uint64");
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return 0;
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}
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}
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return result;
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}
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bool PalCounterReference::finalize() {
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Pal::Result result;
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iPerf()->Finalize();
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// Acquire GPU memory for the query from the pool and bind it.
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Pal::GpuMemoryRequirements gpuMemReqs = {};
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iPerf()->GetGpuMemoryRequirements(&gpuMemReqs);
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memory_ = new Memory(gpu().dev(), amd::alignUp(gpuMemReqs.size, gpuMemReqs.alignment));
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if (nullptr == memory_) {
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return false;
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}
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if (!memory_->create(Resource::Remote)) {
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return false;
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}
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cpuAddr_ = memory_->cpuMap(gpu_);
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if (nullptr == cpuAddr_) {
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return false;
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}
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gpu_.queue(gpu_.engineID_).addMemRef(memory_->iMem());
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result = iPerf()->BindGpuMemory(memory_->iMem(), 0);
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if (result == Pal::Result::Success) {
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Pal::GlobalCounterLayout layout = {};
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iPerf()->GetGlobalCounterLayout(&layout);
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assert(layout.sampleCount == numExpCounters_);
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size_t size = sizeof(Pal::GlobalCounterLayout) +
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(sizeof(Pal::GlobalSampleLayout) * (layout.sampleCount - 1));
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layout_ = reinterpret_cast<Pal::GlobalCounterLayout*>(new char[size]);
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if (layout_ != nullptr) {
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layout_->sampleCount = layout.sampleCount;
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iPerf()->GetGlobalCounterLayout(layout_);
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}
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return true;
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} else {
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return false;
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}
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}
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static const std::array<PCIndexSelect, 46> blockIdToIndexSelect = {{
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PCIndexSelect::None, // CPF
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PCIndexSelect::ShaderEngine, // IA
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PCIndexSelect::ShaderEngine, // VGT
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PCIndexSelect::ShaderArray, // PA
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PCIndexSelect::ShaderArray, // SC
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PCIndexSelect::ShaderEngine, // SPI
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PCIndexSelect::ShaderEngine, // SQ
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PCIndexSelect::ShaderArray, // SX
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PCIndexSelect::ComputeUnit, // TA
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PCIndexSelect::ComputeUnit, // TD
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PCIndexSelect::ComputeUnit, // TCP
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PCIndexSelect::Instance, // TCC
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PCIndexSelect::Instance, // TCA
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PCIndexSelect::ShaderArray, // DB
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PCIndexSelect::ShaderArray, // CB
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PCIndexSelect::None, // GDS
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PCIndexSelect::None, // SRBM
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PCIndexSelect::None, // GRBM
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PCIndexSelect::ShaderEngine, // GRBMSE
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PCIndexSelect::None, // RLC
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PCIndexSelect::Instance, // DMA
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PCIndexSelect::None, // MC
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PCIndexSelect::None, // CPG
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PCIndexSelect::None, // CPC
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PCIndexSelect::None, // WD
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PCIndexSelect::None, // TCS
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PCIndexSelect::None, // ATC
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PCIndexSelect::None, // ATCL2
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PCIndexSelect::None, // MCVML2
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PCIndexSelect::Instance, // EA
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PCIndexSelect::None, // RPB
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PCIndexSelect::ShaderArray, // RMI
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PCIndexSelect::Instance, // UMCCH
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PCIndexSelect::Instance, // GE
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PCIndexSelect::ShaderArray, // GL1A
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PCIndexSelect::ShaderArray, // GL1C
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PCIndexSelect::ShaderArray, // GL1CG
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PCIndexSelect::Instance, // GL2A
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PCIndexSelect::Instance, // GL2C
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PCIndexSelect::None, // CHA
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PCIndexSelect::Instance, // CHC
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PCIndexSelect::None, // CHCG
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PCIndexSelect::None, // GUS
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PCIndexSelect::None, // GCR
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PCIndexSelect::None, // PH
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PCIndexSelect::ShaderArray, // UTCL1
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}};
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static_assert(blockIdToIndexSelect.size() == static_cast<size_t>(Pal::GpuBlock::Count), "size of blockIdToIndexSelect does not match GpuBlock::Count");
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// Converting from ORCA cmndefs.h to PAL palPerfExperiment.h
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static const std::array<std::pair<int, int>, 83> ciBlockIdOrcaToPal = {{
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{0x0E, 0}, // CB0
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{0x0E, 1}, // CB1
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{0x0E, 2}, // CB2
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{0x0E, 3}, // CB3
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{0x00, 0}, // CPF
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{0x0D, 0}, // DB0
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{0x0D, 1}, // DB1
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{0x0D, 2}, // DB2
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{0x0D, 3}, // DB3
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{0x11, 0}, // GRBM
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{0x12, 0}, // GRBMSE
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{0x03, 0}, // PA_SU
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{0x04, 0}, // PA_SC
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{0x05, 0}, // SPI
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{0x06, 0}, // SQ
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{0x06, 0}, // SQ_ES
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{0x06, 0}, // SQ_GS
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{0x06, 0}, // SQ_VS
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{0x06, 0}, // SQ_PS
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{0x06, 0}, // SQ_LS
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{0x06, 0}, // SQ_HS
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{0x06, 0}, // SQ_CS
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{0x07, 0}, // SX
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{0x08, 0}, // TA0
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{0x08, 1}, // TA1
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{0x08, 2}, // TA2
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{0x08, 3}, // TA3
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{0x08, 4}, // TA4
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{0x08, 5}, // TA5
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{0x08, 6}, // TA6
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{0x08, 7}, // TA7
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{0x08, 8}, // TA8
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{0x08, 9}, // TA9
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{0x08, 0x0a}, // TA10
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{0x0C, 0}, // TCA0
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{0x0C, 1}, // TCA1
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{0x0B, 0}, // TCC0
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{0x0B, 1}, // TCC1
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{0x0B, 2}, // TCC2
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{0x0B, 3}, // TCC3
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{0x0B, 4}, // TCC4
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{0x0B, 5}, // TCC5
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{0x0B, 6}, // TCC6
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{0x0B, 7}, // TCC7
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{0x0B, 8}, // TCC8
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{0x0B, 9}, // TCC9
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{0x0B, 0x0a}, // TCC10
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{0x0B, 0x0b}, // TCC11
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{0x0B, 0x0c}, // TCC12
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{0x0B, 0x0d}, // TCC13
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{0x0B, 0x0e}, // TCC14
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{0x0B, 0x0f}, // TCC15
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{0x09, 0}, // TD0
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{0x09, 1}, // TD1
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{0x09, 2}, // TD2
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{0x09, 3}, // TD3
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{0x09, 4}, // TD4
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{0x09, 5}, // TD5
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{0x09, 6}, // TD6
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{0x09, 7}, // TD7
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{0x09, 8}, // TD8
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{0x09, 9}, // TD9
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{0x09, 0x0a}, // TD10
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{0x0A, 0}, // TCP0
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{0x0A, 1}, // TCP1
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{0x0A, 2}, // TCP2
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{0x0A, 3}, // TCP3
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{0x0A, 4}, // TCP4
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{0x0A, 5}, // TCP5
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{0x0A, 6}, // TCP6
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{0x0A, 7}, // TCP7
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{0x0A, 8}, // TCP8
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{0x0A, 9}, // TCP9
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{0x0A, 0x0a}, // TCP10
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{0x0F, 0}, // GDS
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{0x02, 0}, // VGT
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{0x01, 0}, // IA
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{0x15, 0}, // MC
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{0x10, 0}, // SRBM
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{0x19, 0}, // TCS
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{0x18, 0}, // WD
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{0x16, 0}, // CPG
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{0x17, 0}, // CPC
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}};
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static const std::array<std::pair<int, int>, 97> viBlockIdOrcaToPal = {{
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{0x0E, 0}, // CB0
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{0x0E, 1}, // CB1
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{0x0E, 2}, // CB2
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{0x0E, 3}, // CB3
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{0x00, 0}, // CPF
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{0x0D, 0}, // DB0
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{0x0D, 1}, // DB1
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{0x0D, 2}, // DB2
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{0x0D, 3}, // DB3
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{0x11, 0}, // GRBM
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{0x12, 0}, // GRBMSE
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{0x03, 0}, // PA_SU
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{0x04, 0}, // PA_SC
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{0x05, 0}, // SPI
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{0x06, 0}, // SQ
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{0x06, 0}, // SQ_ES
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{0x06, 0}, // SQ_GS
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{0x06, 0}, // SQ_VS
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{0x06, 0}, // SQ_PS
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{0x06, 0}, // SQ_LS
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{0x06, 0}, // SQ_HS
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{0x06, 0}, // SQ_CS
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{0x07, 0}, // SX
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{0x08, 0}, // TA0
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{0x08, 1}, // TA1
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{0x08, 2}, // TA2
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{0x08, 3}, // TA3
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{0x08, 4}, // TA4
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{0x08, 5}, // TA5
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{0x08, 6}, // TA6
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{0x08, 7}, // TA7
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{0x08, 8}, // TA8
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{0x08, 9}, // TA9
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{0x08, 0x0a}, // TA10
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{0x08, 0x0b}, // TA11
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{0x08, 0x0c}, // TA12
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{0x08, 0x0d}, // TA13
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{0x08, 0x0e}, // TA14
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{0x08, 0x0f}, // TA15
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{0x0C, 0}, // TCA0
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{0x0C, 1}, // TCA1
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{0x0B, 0}, // TCC0
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{0x0B, 1}, // TCC1
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{0x0B, 2}, // TCC2
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{0x0B, 3}, // TCC3
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{0x0B, 4}, // TCC4
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{0x0B, 5}, // TCC5
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{0x0B, 6}, // TCC6
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{0x0B, 7}, // TCC7
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{0x0B, 8}, // TCC8
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{0x0B, 9}, // TCC9
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{0x0B, 0x0a}, // TCC10
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{0x0B, 0x0b}, // TCC11
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{0x0B, 0x0c}, // TCC12
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{0x0B, 0x0d}, // TCC13
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{0x0B, 0x0e}, // TCC14
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{0x0B, 0x0f}, // TCC15
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{0x09, 0}, // TD0
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{0x09, 1}, // TD1
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{0x09, 2}, // TD2
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{0x09, 3}, // TD3
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{0x09, 4}, // TD4
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{0x09, 5}, // TD5
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{0x09, 6}, // TD6
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{0x09, 7}, // TD7
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{0x09, 8}, // TD8
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{0x09, 9}, // TD9
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{0x09, 0x0a}, // TD10
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{0x09, 0x0b}, // TD11
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{0x09, 0x0c}, // TD12
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{0x09, 0x0d}, // TD13
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{0x09, 0x0e}, // TD14
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{0x09, 0x0f}, // TD15
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{0x0A, 0}, // TCP0
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{0x0A, 1}, // TCP1
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{0x0A, 2}, // TCP2
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{0x0A, 3}, // TCP3
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{0x0A, 4}, // TCP4
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{0x0A, 5}, // TCP5
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{0x0A, 6}, // TCP6
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{0x0A, 7}, // TCP7
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{0x0A, 8}, // TCP8
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{0x0A, 9}, // TCP9
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{0x0A, 0x0a}, // TCP10
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{0x0A, 0x0b}, // TCP11
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{0x0A, 0x0c}, // TCP12
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{0x0A, 0x0d}, // TCP13
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{0x0A, 0x0e}, // TCP14
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{0x0A, 0x0f}, // TCP15
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{0x0F, 0}, // GDS
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{0x02, 0}, // VGT
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{0x01, 0}, // IA
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{0x15, 0}, // MC
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{0x10, 0}, // SRBM
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{0x18, 0}, // WD
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{0x16, 0}, // CPG
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{0x17, 0}, // CPC
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}};
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// The number of counters per block has been increased for gfx9 but this table may not reflect all
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// of them
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// as compute may not use all of them.
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static const std::array<std::pair<int, int>, 123> gfx9BlockIdPal = {{
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{0x0E, 0}, // CB0 - 0
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{0x0E, 1}, // CB1 - 1
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{0x0E, 2}, // CB2 - 2
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{0x0E, 3}, // CB3 - 3
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{0x00, 0}, // CPF - 4
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{0x0D, 0}, // DB0 - 5
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{0x0D, 1}, // DB1 - 6
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{0x0D, 2}, // DB2 - 7
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{0x0D, 3}, // DB3 - 8
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{0x11, 0}, // GRBM - 9
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{0x12, 0}, // GRBMSE - 10
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{0x03, 0}, // PA_SU - 11
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{0x04, 0}, // PA_SC - 12
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{0x05, 0}, // SPI - 13
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{0x06, 0}, // SQ - 14
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{0x06, 0}, // SQ_ES - 15
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{0x06, 0}, // SQ_GS - 16
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{0x06, 0}, // SQ_VS - 17
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{0x06, 0}, // SQ_PS - 18
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{0x06, 0}, // SQ_LS - 19
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{0x06, 0}, // SQ_HS - 20
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{0x06, 0}, // SQ_CS - 21
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{0x07, 0}, // SX - 22
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{0x08, 0}, // TA0 - 23
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{0x08, 1}, // TA1 - 24
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{0x08, 2}, // TA2 - 25
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{0x08, 3}, // TA3 - 26
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{0x08, 4}, // TA4 - 27
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{0x08, 5}, // TA5 - 28
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{0x08, 6}, // TA6 - 29
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{0x08, 7}, // TA7 - 30
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{0x08, 8}, // TA8 - 31
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{0x08, 9}, // TA9 - 32
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{0x08, 0x0a}, // TA10 - 33
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{0x08, 0x0b}, // TA11 - 34
|
|
{0x08, 0x0c}, // TA12 - 35
|
|
{0x08, 0x0d}, // TA13 - 36
|
|
{0x08, 0x0e}, // TA14 - 37
|
|
{0x08, 0x0f}, // TA15 - 38
|
|
{0x0C, 0}, // TCA0 - 39
|
|
{0x0C, 1}, // TCA1 - 40
|
|
{0x0B, 0}, // TCC0 - 41
|
|
{0x0B, 1}, // TCC1 - 42
|
|
{0x0B, 2}, // TCC2 - 43
|
|
{0x0B, 3}, // TCC3 - 44
|
|
{0x0B, 4}, // TCC4 - 45
|
|
{0x0B, 5}, // TCC5 - 46
|
|
{0x0B, 6}, // TCC6 - 47
|
|
{0x0B, 7}, // TCC7 - 48
|
|
{0x0B, 8}, // TCC8 - 49
|
|
{0x0B, 9}, // TCC9 - 50
|
|
{0x0B, 0x0a}, // TCC10 - 51
|
|
{0x0B, 0x0b}, // TCC11 - 52
|
|
{0x0B, 0x0c}, // TCC12 - 53
|
|
{0x0B, 0x0d}, // TCC13 - 54
|
|
{0x0B, 0x0e}, // TCC14 - 55
|
|
{0x0B, 0x0f}, // TCC15 - 56
|
|
{0x09, 0}, // TD0 - 57
|
|
{0x09, 1}, // TD1 - 58
|
|
{0x09, 2}, // TD2 - 59
|
|
{0x09, 3}, // TD3 - 60
|
|
{0x09, 4}, // TD4 - 61
|
|
{0x09, 5}, // TD5 - 62
|
|
{0x09, 6}, // TD6 - 63
|
|
{0x09, 7}, // TD7 - 64
|
|
{0x09, 8}, // TD8 - 65
|
|
{0x09, 9}, // TD9 - 66
|
|
{0x09, 0x0a}, // TD10 - 67
|
|
{0x09, 0x0b}, // TD11 - 68
|
|
{0x09, 0x0c}, // TD12 - 69
|
|
{0x09, 0x0d}, // TD13 - 70
|
|
{0x09, 0x0e}, // TD14 - 71
|
|
{0x09, 0x0f}, // TD15 - 72
|
|
{0x0A, 0}, // TCP0 - 73
|
|
{0x0A, 1}, // TCP1 - 74
|
|
{0x0A, 2}, // TCP2 - 75
|
|
{0x0A, 3}, // TCP3 - 76
|
|
{0x0A, 4}, // TCP4 - 77
|
|
{0x0A, 5}, // TCP5 - 78
|
|
{0x0A, 6}, // TCP6 - 79
|
|
{0x0A, 7}, // TCP7 - 80
|
|
{0x0A, 8}, // TCP8 - 81
|
|
{0x0A, 9}, // TCP9 - 82
|
|
{0x0A, 0x0a}, // TCP10 - 83
|
|
{0x0A, 0x0b}, // TCP11 - 84
|
|
{0x0A, 0x0c}, // TCP12 - 85
|
|
{0x0A, 0x0d}, // TCP13 - 86
|
|
{0x0A, 0x0e}, // TCP14 - 87
|
|
{0x0A, 0x0f}, // TCP15 - 88
|
|
{0x0F, 0}, // GDS - 89
|
|
{0x02, 0}, // VGT - 90
|
|
{0x01, 0}, // IA - 91
|
|
{0x18, 0}, // WD - 92
|
|
{0x16, 0}, // CPG - 93
|
|
{0x17, 0}, // CPC - 94
|
|
{0x1A, 0}, // ATC - 95
|
|
{0x1B, 0}, // ATCL2 - 96
|
|
{0x1C, 0}, // MCVML2 - 97
|
|
{0x1D, 0}, // EA0 - 98
|
|
{0x1D, 1}, // EA1 - 99
|
|
{0x1D, 2}, // EA2 - 100
|
|
{0x1D, 3}, // EA3 - 101
|
|
{0x1D, 4}, // EA4 - 102
|
|
{0x1D, 5}, // EA5 - 103
|
|
{0x1D, 6}, // EA6 - 104
|
|
{0x1D, 7}, // EA7 - 105
|
|
{0x1D, 8}, // EA8 - 106
|
|
{0x1D, 9}, // EA9 - 107
|
|
{0x1D, 0x0a}, // EA10 - 108
|
|
{0x1D, 0x0b}, // EA11 - 109
|
|
{0x1D, 0x0c}, // EA12 - 110
|
|
{0x1D, 0x0d}, // EA13 - 111
|
|
{0x1D, 0x0e}, // EA14 - 112
|
|
{0x1D, 0x0f}, // EA15 - 113
|
|
{0x1E, 0}, // RPB - 114
|
|
{0x1F, 0}, // RMI0 - 115
|
|
{0x1F, 1}, // RMI1 - 116
|
|
{0x1F, 2}, // RMI2 - 117
|
|
{0x1F, 3}, // RMI3 - 118
|
|
{0x1F, 4}, // RMI4 - 119
|
|
{0x1F, 5}, // RMI5 - 120
|
|
{0x1F, 6}, // RMI6 - 121
|
|
{0x1F, 7}, // RMI7 - 122
|
|
}};
|
|
|
|
static const std::array<std::pair<int, int>, 151> gfx10BlockIdPal = {{
|
|
{0x0E, 0}, // CB0 - 0
|
|
{0x0E, 1}, // CB1 - 1
|
|
{0x0E, 2}, // CB2 - 2
|
|
{0x0E, 3}, // CB3 - 3
|
|
{0x00, 0}, // CPF - 4
|
|
{0x0D, 0}, // DB0 - 5
|
|
{0x0D, 1}, // DB1 - 6
|
|
{0x0D, 2}, // DB2 - 7
|
|
{0x0D, 3}, // DB3 - 8
|
|
{0x11, 0}, // GRBM - 9
|
|
{0x12, 0}, // GRBMSE - 10
|
|
{0x03, 0}, // PA_SU - 11
|
|
{0x04, 0}, // PA_SC0 - 12
|
|
{0x04, 1}, // PA_SC1 - 13
|
|
{0x05, 0}, // SPI - 14
|
|
{0x06, 0}, // SQ - 15
|
|
{0x06, 0}, // SQ_ES - 16
|
|
{0x06, 0}, // SQ_GS - 17
|
|
{0x06, 0}, // SQ_VS - 18
|
|
{0x06, 0}, // SQ_PS - 19
|
|
{0x06, 0}, // SQ_LS - 20
|
|
{0x06, 0}, // SQ_HS - 21
|
|
{0x06, 0}, // SQ_CS - 22
|
|
{0x07, 0}, // SX - 23
|
|
{0x08, 0}, // TA0 - 24
|
|
{0x08, 1}, // TA1 - 25
|
|
{0x08, 2}, // TA2 - 26
|
|
{0x08, 3}, // TA3 - 27
|
|
{0x08, 4}, // TA4 - 28
|
|
{0x08, 5}, // TA5 - 29
|
|
{0x08, 6}, // TA6 - 30
|
|
{0x08, 7}, // TA7 - 31
|
|
{0x08, 8}, // TA8 - 32
|
|
{0x08, 9}, // TA9 - 33
|
|
{0x08, 0x0a}, // TA10 - 34
|
|
{0x08, 0x0b}, // TA11 - 35
|
|
{0x08, 0x0c}, // TA12 - 36
|
|
{0x08, 0x0d}, // TA13 - 37
|
|
{0x08, 0x0e}, // TA14 - 38
|
|
{0x08, 0x0f}, // TA15 - 39
|
|
{0x09, 0}, // TD0 - 40
|
|
{0x09, 1}, // TD1 - 41
|
|
{0x09, 2}, // TD2 - 42
|
|
{0x09, 3}, // TD3 - 43
|
|
{0x09, 4}, // TD4 - 44
|
|
{0x09, 5}, // TD5 - 45
|
|
{0x09, 6}, // TD6 - 46
|
|
{0x09, 7}, // TD7 - 47
|
|
{0x09, 8}, // TD8 - 48
|
|
{0x09, 9}, // TD9 - 49
|
|
{0x09, 0x0a}, // TD10 - 60
|
|
{0x09, 0x0b}, // TD11 - 61
|
|
{0x09, 0x0c}, // TD12 - 62
|
|
{0x09, 0x0d}, // TD13 - 63
|
|
{0x09, 0x0e}, // TD14 - 64
|
|
{0x09, 0x0f}, // TD15 - 65
|
|
{0x0A, 0}, // TCP0 - 66
|
|
{0x0A, 1}, // TCP1 - 67
|
|
{0x0A, 2}, // TCP2 - 68
|
|
{0x0A, 3}, // TCP3 - 69
|
|
{0x0A, 4}, // TCP4 - 70
|
|
{0x0A, 5}, // TCP5 - 71
|
|
{0x0A, 6}, // TCP6 - 72
|
|
{0x0A, 7}, // TCP7 - 73
|
|
{0x0A, 8}, // TCP8 - 74
|
|
{0x0A, 9}, // TCP9 - 75
|
|
{0x0A, 0x0a}, // TCP10 - 76
|
|
{0x0A, 0x0b}, // TCP11 - 77
|
|
{0x0A, 0x0c}, // TCP12 - 78
|
|
{0x0A, 0x0d}, // TCP13 - 79
|
|
{0x0A, 0x0e}, // TCP14 - 80
|
|
{0x0A, 0x0f}, // TCP15 - 81
|
|
{0x0F, 0}, // GDS - 82
|
|
{0x16, 0}, // CPG - 83
|
|
{0x17, 0}, // CPC - 84
|
|
{0x1A, 0}, // ATC - 85
|
|
{0x1B, 0}, // ATCL2 - 86
|
|
{0x1C, 0}, // MCVML2 - 87
|
|
{0x1D, 0}, // EA0 - 88
|
|
{0x1D, 1}, // EA1 - 89
|
|
{0x1D, 2}, // EA2 - 90
|
|
{0x1D, 3}, // EA3 - 91
|
|
{0x1D, 4}, // EA4 - 92
|
|
{0x1D, 5}, // EA5 - 93
|
|
{0x1D, 6}, // EA6 - 94
|
|
{0x1D, 7}, // EA7 - 95
|
|
{0x1D, 8}, // EA8 - 96
|
|
{0x1D, 9}, // EA9 - 97
|
|
{0x1D, 0x0a}, // EA10 - 98
|
|
{0x1D, 0x0b}, // EA11 - 99
|
|
{0x1D, 0x0c}, // EA12 - 100
|
|
{0x1D, 0x0d}, // EA13 - 101
|
|
{0x1D, 0x0e}, // EA14 - 102
|
|
{0x1D, 0x0f}, // EA15 - 103
|
|
{0x1E, 0}, // RPB - 104
|
|
{0x1F, 0}, // RMI0 - 105
|
|
{0x1F, 1}, // RMI1 - 106
|
|
{0x21, 0}, // GE - 107
|
|
{0x22, 0}, // GL1A - 108
|
|
{0x23, 0}, // GL1C - 109
|
|
{0x24, 0}, // GL1CG0 - 110
|
|
{0x24, 1}, // GL1CG1 - 111
|
|
{0x24, 2}, // GL1CG2 - 112
|
|
{0x24, 3}, // GL1CG3 - 113
|
|
{0x25, 0}, // GL2A0 - 114
|
|
{0x25, 1}, // GL2A1 - 115
|
|
{0x25, 2}, // GL2A2 - 116
|
|
{0x25, 3}, // GL2A3 - 117
|
|
{0x26, 0}, // GL2C0 - 118
|
|
{0x26, 1}, // GL2C1 - 119
|
|
{0x26, 2}, // GL2C2 - 120
|
|
{0x26, 3}, // GL2C3 - 121
|
|
{0x26, 4}, // GL2C4 - 122
|
|
{0x26, 5}, // GL2C5 - 123
|
|
{0x26, 6}, // GL2C6 - 124
|
|
{0x26, 7}, // GL2C7 - 125
|
|
{0x26, 8}, // GL2C8 - 126
|
|
{0x26, 9}, // GL2C9 - 127
|
|
{0x26, 0x0a}, // GL2C10 - 128
|
|
{0x26, 0x0b}, // GL2C11 - 129
|
|
{0x26, 0x0c}, // GL2C12 - 130
|
|
{0x26, 0x0d}, // GL2C13 - 131
|
|
{0x26, 0x0e}, // GL2C14 - 132
|
|
{0x26, 0x0f}, // GL2C15 - 133
|
|
{0x26, 0x10}, // GL2C16 - 134
|
|
{0x26, 0x11}, // GL2C17 - 135
|
|
{0x26, 0x12}, // GL2C18 - 136
|
|
{0x26, 0x13}, // GL2C19 - 137
|
|
{0x26, 0x14}, // GL2C20 - 138
|
|
{0x26, 0x15}, // GL2C21 - 139
|
|
{0x26, 0x16}, // GL2C22 - 140
|
|
{0x26, 0x17}, // GL2C23 - 141
|
|
{0x27, 0}, // CHA - 142
|
|
{0x28, 0}, // CHC0 - 143
|
|
{0x28, 1}, // CHC1 - 144
|
|
{0x28, 2}, // CHC2 - 145
|
|
{0x28, 3}, // CHC3 - 146
|
|
{0x29, 0}, // CHCG - 147
|
|
{0x2A, 0}, // GUS - 148
|
|
{0x2B, 0}, // GCR - 149
|
|
{0x2C, 0}, // PH - 150
|
|
}};
|
|
|
|
void PerfCounter::convertInfo() {
|
|
switch (dev().ipLevel()) {
|
|
case Pal::GfxIpLevel::GfxIp7:
|
|
if (info_.blockIndex_ < ciBlockIdOrcaToPal.size()) {
|
|
auto p = ciBlockIdOrcaToPal[info_.blockIndex_];
|
|
info_.blockIndex_ = std::get<0>(p);
|
|
info_.counterIndex_ = std::get<1>(p);
|
|
}
|
|
break;
|
|
case Pal::GfxIpLevel::GfxIp8:
|
|
if (info_.blockIndex_ < viBlockIdOrcaToPal.size()) {
|
|
auto p = viBlockIdOrcaToPal[info_.blockIndex_];
|
|
info_.blockIndex_ = std::get<0>(p);
|
|
info_.counterIndex_ = std::get<1>(p);
|
|
}
|
|
break;
|
|
case Pal::GfxIpLevel::GfxIp9:
|
|
if (info_.blockIndex_ < gfx9BlockIdPal.size()) {
|
|
auto p = gfx9BlockIdPal[info_.blockIndex_];
|
|
info_.blockIndex_ = std::get<0>(p);
|
|
info_.counterIndex_ = std::get<1>(p);
|
|
}
|
|
break;
|
|
case Pal::GfxIpLevel::GfxIp10:
|
|
case Pal::GfxIpLevel::GfxIp10_1:
|
|
if (info_.blockIndex_ < gfx10BlockIdPal.size()) {
|
|
auto p = gfx10BlockIdPal[info_.blockIndex_];
|
|
info_.blockIndex_ = std::get<0>(p);
|
|
info_.counterIndex_ = std::get<1>(p);
|
|
}
|
|
break;
|
|
default:
|
|
Unimplemented();
|
|
break;
|
|
}
|
|
|
|
assert(info_.blockIndex_ < blockIdToIndexSelect.size());
|
|
info_.indexSelect_ = blockIdToIndexSelect.at(info_.blockIndex_);
|
|
}
|
|
|
|
PerfCounter::~PerfCounter() {
|
|
if (palRef_ == nullptr) {
|
|
return;
|
|
}
|
|
|
|
// Release the counter reference object
|
|
palRef_->release();
|
|
}
|
|
|
|
bool PerfCounter::create() {
|
|
palRef_->retain();
|
|
|
|
// Initialize the counter
|
|
Pal::PerfCounterInfo counterInfo = {};
|
|
counterInfo.counterType = Pal::PerfCounterType::Global;
|
|
counterInfo.block = static_cast<Pal::GpuBlock>(info_.blockIndex_);
|
|
counterInfo.eventId = info_.eventIndex_;
|
|
|
|
Pal::PerfExperimentProperties perfExpProps;
|
|
Pal::Result result;
|
|
result = dev().iDev()->GetPerfExperimentProperties(&perfExpProps);
|
|
if (result != Pal::Result::Success) {
|
|
return false;
|
|
}
|
|
|
|
const auto& blockProps = perfExpProps.blocks[static_cast<uint32_t>(counterInfo.block)];
|
|
uint32_t counter_start, counter_step;
|
|
|
|
switch (info_.indexSelect_) {
|
|
case PCIndexSelect::ShaderEngine:
|
|
case PCIndexSelect::None:
|
|
counter_start = 0;
|
|
counter_step = 1;
|
|
break;
|
|
|
|
case PCIndexSelect::ShaderArray:
|
|
if (info_.counterIndex_ >=
|
|
(dev().properties().gfxipProperties.shaderCore.numShaderArrays * dev().properties().gfxipProperties.shaderCore.numShaderEngines)) {
|
|
return true;
|
|
}
|
|
counter_start = info_.counterIndex_;
|
|
counter_step = dev().properties().gfxipProperties.shaderCore.numShaderArrays * dev().properties().gfxipProperties.shaderCore.numShaderEngines;
|
|
break;
|
|
|
|
case PCIndexSelect::ComputeUnit:
|
|
if (info_.counterIndex_ >=
|
|
dev().properties().gfxipProperties.shaderCore.maxCusPerShaderArray) {
|
|
return true;
|
|
}
|
|
counter_start = info_.counterIndex_;
|
|
counter_step = dev().properties().gfxipProperties.shaderCore.maxCusPerShaderArray;
|
|
break;
|
|
|
|
case PCIndexSelect::Instance:
|
|
counter_start = info_.counterIndex_;
|
|
counter_step = blockProps.instanceCount;
|
|
break;
|
|
|
|
default:
|
|
assert(0 && "Unknown indexSelect_");
|
|
return true;
|
|
}
|
|
|
|
for (uint32_t i = counter_start; i < blockProps.instanceCount; i += counter_step) {
|
|
counterInfo.instance = i;
|
|
result = iPerf()->AddCounter(counterInfo);
|
|
if (result == Pal::Result::Success) {
|
|
index_.push_back(palRef_->getPalCounterIndex());
|
|
} else {
|
|
// Get here when there's no HW PerfCounter matching the counterInfo
|
|
assert(0 && "AddCounter() failed");
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
uint64_t PerfCounter::getInfo(uint64_t infoType) const {
|
|
switch (infoType) {
|
|
case CL_PERFCOUNTER_GPU_BLOCK_INDEX: {
|
|
// Return the GPU block index
|
|
return info()->blockIndex_;
|
|
}
|
|
case CL_PERFCOUNTER_GPU_COUNTER_INDEX: {
|
|
// Return the GPU counter index
|
|
return info()->counterIndex_;
|
|
}
|
|
case CL_PERFCOUNTER_GPU_EVENT_INDEX: {
|
|
// Return the GPU event index
|
|
return info()->eventIndex_;
|
|
}
|
|
case CL_PERFCOUNTER_DATA: {
|
|
return palRef_->result(index_);
|
|
}
|
|
default:
|
|
LogError("Wrong PerfCounter::getInfo parameter");
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
} // namespace pal
|