foreman
480 righe
17 KiB
C++
480 righe
17 KiB
C++
//
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// Copyright (c) 2008 Advanced Micro Devices, Inc. All rights reserved.
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//
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#include "device/gpu/gpukernel.hpp"
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#include <string>
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#include <fstream>
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#include <sstream>
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#include <iostream>
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#include <ctime>
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#include "acl.h"
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#define R900_BUILD 1
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#include "SCShadersR800.h"
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#include "r8xx_r9xx_merged__offset.h"
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#include "r8xx_r9xx_merged__typedef.h"
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namespace gpu {
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#define NUM_R800_CS_INFOS (0x22+SC_R800_MAX_UAV+ \
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3+ /* globalReturnBuffer flag plus numUavs and numGlobalReturnBuffers */ \
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1+ /* extendedCaching flag */ \
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3+ /* globalReturnBuffer sizes for dword, shorts and bytes */ \
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3*SC_R800_MAX_UAV+ /* offsetmap, cached and uncached fetch consts */ \
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2*SC_R800_MAX_UAV+ /* 64- and 128-bit cached fetch consts */ \
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2*R800_GLOBAL_RTN_BUF_LAST /* global return buffer fetch consts and type */ )
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struct Options {
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uint numClauseTemps_;
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uint numGPRs_;
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uint numThreads_;
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uint numStackEntries_;
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uint ldsSize_;
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Options(CALtarget target) {
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numClauseTemps_ = 4;
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switch (target) {
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case CAL_TARGET_DEVASTATOR:
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case CAL_TARGET_SCRAPPER:
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case CAL_TARGET_CAYMAN:
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case CAL_TARGET_KAUAI:
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numClauseTemps_ = 0;
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numStackEntries_ = 512;
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numThreads_ = 248;
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break;
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case CAL_TARGET_SUPERSUMO:
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case CAL_TARGET_TURKS:
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case CAL_TARGET_REDWOOD:
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numStackEntries_ = 256;
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numThreads_ = 248;
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break;
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case CAL_TARGET_WRESTLER:
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case CAL_TARGET_SUMO:
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case CAL_TARGET_CAICOS:
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case CAL_TARGET_CEDAR:
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numStackEntries_ = 256;
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numThreads_ = 192;
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break;
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case CAL_TARGET_CYPRESS:
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case CAL_TARGET_BARTS:
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case CAL_TARGET_JUNIPER:
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numStackEntries_ = 512;
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numThreads_ = 248;
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break;
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default:
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numStackEntries_ = 512;
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numThreads_ = 248;
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LogError("Unknown ASIC type");
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}
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numGPRs_ = 256 - 2 * numClauseTemps_;
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ldsSize_ = 32*1024;
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}
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private:
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Options();
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Options(const Options&);
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Options& operator=(const Options&);
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};
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static const uint UncachedFetchConst[SC_R800_MAX_UAV] =
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{ 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 173 };
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static const uint CachedFetchConst[SC_R800_MAX_UAV] =
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{ 144, 145, 146, 148, 149, 150, 151, 152, 0, 0, 0, 153 };
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static const uint GlobalReturnFetchConst[R800_GLOBAL_RTN_BUF_LAST] =
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{ 165, 166, 167, 168, 169, 170, 171, 172 };
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static const uint GlobalReturnBufferType[R800_GLOBAL_RTN_BUF_LAST] =
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{ AMU_ABI_UAV_FORMAT_TYPELESS, AMU_ABI_UAV_FORMAT_FLOAT,
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AMU_ABI_UAV_FORMAT_UNORM, AMU_ABI_UAV_FORMAT_SNORM, AMU_ABI_UAV_FORMAT_UINT,
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AMU_ABI_UAV_FORMAT_SINT, AMU_ABI_UAV_FORMAT_SHORT, AMU_ABI_UAV_FORMAT_BYTE };
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static const uint CachedFetchConst64[SC_R800_MAX_UAV] =
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 174 };
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static const uint CachedFetchConst128[SC_R800_MAX_UAV] =
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 175 };
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bool
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NullKernel::r800CreateHwInfo(const void* shader, AMUabiAddEncoding& encoding)
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{
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CALProgramInfoEntry* newInfos;
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const Options options(nullDev().calTarget());
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uint i = 0;
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uint numShaderEngines = 1;
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if ((nullDev().calTarget() == CAL_TARGET_CAYMAN) ||
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(nullDev().calTarget() == CAL_TARGET_CYPRESS) ||
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(nullDev().calTarget() == CAL_TARGET_BARTS)) {
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numShaderEngines = 2;
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}
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uint infoCount = NUM_R800_CS_INFOS;
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SC_R800CSHWSHADER* cShader = (SC_R800CSHWSHADER *)shader;
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if (cShader->u32NumThreadPerGroup == 0) {
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return false;
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}
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newInfos = new CALProgramInfoEntry[infoCount];
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encoding.progInfos = newInfos;
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if (encoding.progInfos == 0) {
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infoCount = 0;
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return false;
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}
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memset(newInfos, 0, infoCount * sizeof(CALProgramInfoEntry));
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newInfos[i].address = mmSQ_PGM_START_LS;
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newInfos[i].value = 0x0;
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i++;
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newInfos[i].address = mmSQ_PGM_RESOURCES_LS;
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cShader->sqPgmResourcesCs.bits.UNCACHED_FIRST_INST = 1;
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cShader->sqPgmResourcesCs.bits.PRIME_CACHE_ENABLE = 1;
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cShader->sqPgmResourcesCs.bits.PRIME_CACHE_ON_CONST = 0;
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newInfos[i].value = cShader->sqPgmResourcesCs.u32All;
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i++;
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newInfos[i].address = mmSQ_PGM_RESOURCES_2_LS;
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newInfos[i].value = cShader->sqPgmResources2Cs.u32All;
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i++;
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newInfos[i].address = mmSPI_THREAD_GROUPING;
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regSPI_THREAD_GROUPING spi_thread_grouping;
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spi_thread_grouping.u32All = 0;
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spi_thread_grouping.bits.PS_GROUPING = 0;
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spi_thread_grouping.bits.VS_GROUPING = 0;
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spi_thread_grouping.bits.ES_GROUPING = 0;
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spi_thread_grouping.bits.GS_GROUPING = 0;
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// dyn_gpr_mgmt if CS_GROUPING = 1.
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spi_thread_grouping.bits.CS_GROUPING = 0;
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newInfos[i].value = spi_thread_grouping.u32All;
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i++;
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const unsigned int numSharedGPR = cShader->u32NumSharedGprTotal;
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newInfos[i].address = mmSQ_DYN_GPR_CNTL_PS_FLUSH_REQ;
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regSQ_DYN_GPR_CNTL_PS_FLUSH_REQ sq_dyn_gpr_cntl_ps_flush_req;
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sq_dyn_gpr_cntl_ps_flush_req.u32All = 0;
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sq_dyn_gpr_cntl_ps_flush_req.bits.RING0_OFFSET = numSharedGPR;
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newInfos[i].value = sq_dyn_gpr_cntl_ps_flush_req.u32All;
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i++;
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const unsigned int numClauseTemps = options.numClauseTemps_;
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const unsigned int MaxNumGPRsAvail = options.numGPRs_;
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newInfos[i].address = mmSQ_GPR_RESOURCE_MGMT_1;
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regSQ_GPR_RESOURCE_MGMT_1 sq_gpr_resource_mgmt_1;
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sq_gpr_resource_mgmt_1.u32All = 0;
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sq_gpr_resource_mgmt_1.bits.NUM_CLAUSE_TEMP_GPRS = numClauseTemps;
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newInfos[i].value = sq_gpr_resource_mgmt_1.u32All;
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i++;
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newInfos[i].address = mmSQ_GPR_RESOURCE_MGMT_3__EG;
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regSQ_GPR_RESOURCE_MGMT_3__EG sq_gpr_resource_mgmt_3;
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sq_gpr_resource_mgmt_3.u32All = 0;
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{
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const unsigned int numWavefrontPerSIMD = 1 ; // ?? cShader->u32NumWavefrontPerSIMD;
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if ((cShader->u32NumSharedGprUser != cShader->u32NumSharedGprTotal)) // cShader->bIsMaxNumWavePerSIMD)
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{
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// if running with a barrier, need to limit the number of wavefronts on a SIMD.
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// force max wavefronts run on a simd by adjusting the num_es_gprs pool that all es programs can
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// allocate from. (# of gprs the program uses * numWavefrontsPerSIMD)
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sq_gpr_resource_mgmt_3.bits.NUM_LS_GPRS = cShader->sqPgmResourcesCs.bits.NUM_GPRS * numWavefrontPerSIMD;
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}
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else
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{
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sq_gpr_resource_mgmt_3.bits.NUM_LS_GPRS = MaxNumGPRsAvail - numSharedGPR;
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}
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}
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newInfos[i].value = sq_gpr_resource_mgmt_3.u32All;
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i++;
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newInfos[i].address = mmSPI_GPR_MGMT;
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regSPI_GPR_MGMT spi_gpr_mgmt;
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spi_gpr_mgmt.u32All = 0;
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{
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const unsigned int numWavefrontPerSIMD = 1 ; // ?? cShader->u32NumWavefrontPerSIMD;
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if ((cShader->u32NumSharedGprUser != cShader->u32NumSharedGprTotal)) // cShader->bIsMaxNumWavePerSIMD)
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{
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// if running with a barrier, need to limit the number of wavefronts on a SIMD.
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// force max wavefronts run on a simd by adjusting the num_es_gprs pool that all es programs can
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// allocate from. (# of gprs the program uses * numWavefrontsPerSIMD)
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spi_gpr_mgmt.bits.NUM_LS_GPRS = (cShader->sqPgmResourcesCs.bits.NUM_GPRS * numWavefrontPerSIMD) >> 3;
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}
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else
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{
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spi_gpr_mgmt.bits.NUM_LS_GPRS = (MaxNumGPRsAvail - numSharedGPR) >> 3;
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}
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}
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newInfos[i].value = spi_gpr_mgmt.u32All;
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i++;
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newInfos[i].address = mmSPI_WAVE_MGMT_1;
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regSPI_WAVE_MGMT_1 spi_wave_mgmt_1;
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spi_wave_mgmt_1.u32All = 0;
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newInfos[i].value = spi_wave_mgmt_1.u32All;
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i++;
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newInfos[i].address = mmSPI_WAVE_MGMT_2;
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regSPI_WAVE_MGMT_2 spi_wave_mgmt_2;
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spi_wave_mgmt_2.u32All = 0;
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spi_wave_mgmt_2.bits.NUM_CS_WAVES_ONE_RING = (options.numThreads_) >> 3;
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newInfos[i].value = spi_wave_mgmt_2.u32All;
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i++;
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newInfos[i].address = mmSQ_THREAD_RESOURCE_MGMT__EG;
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regSQ_THREAD_RESOURCE_MGMT__EG sq_thread_resource_mgmt;
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sq_thread_resource_mgmt.u32All = 0;
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sq_thread_resource_mgmt.bits.NUM_PS_THREADS = 0;
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sq_thread_resource_mgmt.bits.NUM_VS_THREADS = 0;
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sq_thread_resource_mgmt.bits.NUM_GS_THREADS = 0;
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sq_thread_resource_mgmt.bits.NUM_ES_THREADS = 0;
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newInfos[i].value = sq_thread_resource_mgmt.u32All;
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i++;
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newInfos[i].address = mmSQ_THREAD_RESOURCE_MGMT_2__EG;
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regSQ_THREAD_RESOURCE_MGMT_2__EG sq_thread_resource_mgmt_2;
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sq_thread_resource_mgmt_2.u32All = 0;
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sq_thread_resource_mgmt_2.bits.NUM_HS_THREADS = 0;
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sq_thread_resource_mgmt_2.bits.NUM_LS_THREADS = options.numThreads_;
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newInfos[i].value = sq_thread_resource_mgmt_2.u32All;
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i++;
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regSPI_COMPUTE_INPUT_CNTL spi_dompute_input_cntl;
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spi_dompute_input_cntl.u32All = 0;
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spi_dompute_input_cntl.bits.DISABLE_INDEX_PACK = 1;
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spi_dompute_input_cntl.bits.TID_IN_GROUP_ENA = 1;
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spi_dompute_input_cntl.bits.TGID_ENA = 1;
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newInfos[i].address = mmSPI_COMPUTE_INPUT_CNTL;
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newInfos[i].value = spi_dompute_input_cntl.u32All;
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i++;
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newInfos[i].address = mmSQ_LDS_ALLOC;
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newInfos[i].value = cShader->sqLdsAllocCs.u32All;
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i++;
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//This is information passed from SC to GSL, there is no valid address, so make up one.
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newInfos[i].address = AMU_ABI_CS_MAX_SCRATCH_REGS;
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newInfos[i].value = cShader->MaxScratchRegsNeeded;
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i++;
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newInfos[i].address = AMU_ABI_CS_NUM_SHARED_GPR_USER;
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newInfos[i].value = cShader->u32NumSharedGprUser;
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i++;
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newInfos[i].address = AMU_ABI_CS_NUM_SHARED_GPR_TOTAL;
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newInfos[i].value = cShader->u32NumSharedGprTotal;
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i++;
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newInfos[i].address = AMU_ABI_NUM_THREAD_PER_GROUP;
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newInfos[i].value = cShader->u32NumThreadPerGroup;
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i++;
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newInfos[i].address = AMU_ABI_NUM_THREAD_PER_GROUP_X;
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newInfos[i].value = cShader->u32NumThreadPerGroup_x;
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i++;
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newInfos[i].address = AMU_ABI_NUM_THREAD_PER_GROUP_Y;
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newInfos[i].value = cShader->u32NumThreadPerGroup_y;
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i++;
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newInfos[i].address = AMU_ABI_NUM_THREAD_PER_GROUP_Z;
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newInfos[i].value = cShader->u32NumThreadPerGroup_z;
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i++;
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newInfos[i].address = AMU_ABI_TOTAL_NUM_THREAD_GROUP;
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newInfos[i].value = cShader->u32TotalNumThreadGroup;
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i++;
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newInfos[i].address = AMU_ABI_NUM_WAVEFRONT_PER_SIMD;
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newInfos[i].value = 1;
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i++;
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newInfos[i].address = AMU_ABI_IS_MAX_NUM_WAVE_PER_SIMD;
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newInfos[i].value = 0; // ??
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i++;
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newInfos[i].address = AMU_ABI_SET_BUFFER_FOR_NUM_GROUP;
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newInfos[i].value = cShader->bSetBufferForNumGroup;
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i++;
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newInfos[i].address = AMU_ABI_RAT_OP_IS_USED;
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newInfos[i].value = cShader->u32RatOpIsUsed;
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i++;
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newInfos[i].address = AMU_ABI_RAT_ATOMIC_OP_IS_USED;
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newInfos[i].value = cShader->u32RatAtomicOpIsUsed;
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i++;
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newInfos[i].address = AMU_ABI_WAVEFRONT_SIZE;
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newInfos[i].value = nullDev().hwInfo()->simdWidth_ * 4;
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i++;
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newInfos[i].address = AMU_ABI_NUM_GPR_AVAIL;
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newInfos[i].value = options.numGPRs_;
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i++;
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newInfos[i].address = AMU_ABI_NUM_GPR_USED;
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newInfos[i].value = cShader->sqPgmResourcesCs.bits.NUM_GPRS;
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i++;
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newInfos[i].address = AMU_ABI_LDS_SIZE_AVAIL;
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newInfos[i].value = options.ldsSize_;
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i++;
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newInfos[i].address = AMU_ABI_LDS_SIZE_USED;
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newInfos[i].value = cShader->sqLdsAllocCs.bits.SIZE;
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i++;
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newInfos[i].address = AMU_ABI_STACK_SIZE_AVAIL;
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newInfos[i].value = options.numStackEntries_;
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i++;
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newInfos[i].address = AMU_ABI_STACK_SIZE_USED;
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newInfos[i].value = cShader->sqPgmResourcesCs.bits.STACK_SIZE;
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i++;
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for (unsigned int j = 0;j <SC_R800_MAX_UAV; j++)
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{
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unsigned int bufferSize = cShader->scUavRtnBufInfoTbl[j].stride;
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bufferSize *= 4; // convert from DWORDS to bytes
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//
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// multiply by the maximum number of threads in flight at one time
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//
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// 256 waves * 64 threads/wave * 2 shader engines (for 870)
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//
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bufferSize *= nullDev().hwInfo()->simdWidth_ * 4; // threads/wave
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bufferSize *= 256 * 4; // maximum number of waves
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bufferSize *= numShaderEngines;
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newInfos[i].address = AMU_ABI_SET_BUFFER_FOR_UAV_RET_BUFFER0 + j;
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newInfos[i].value = bufferSize;
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i++;
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}
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newInfos[i].address = AMU_ABI_GLOBAL_RETURN_BUFFER;
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newInfos[i].value = true;
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i++;
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// Always use extended caching with global return buffer
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newInfos[i].address = AMU_ABI_EXTENDED_CACHING;
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newInfos[i].value = true;
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i++;
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newInfos[i].address = AMU_ABI_NUM_GLOBAL_UAV;
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newInfos[i].value = SC_R800_MAX_UAV;
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i++;
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newInfos[i].address = AMU_ABI_NUM_GLOBAL_RETURN_BUFFER;
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newInfos[i].value = R800_GLOBAL_RTN_BUF_LAST;
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i++;
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{
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unsigned int bufferSize = cShader->u32GlobalRtnBufSlot;
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bufferSize *= 4; // convert from DWORDS to bytes
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//
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// multiply by the maximum number of threads in flight at one time
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//
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// 256 waves * 64 threads/wave * 2 shader engines (for 870)
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//
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bufferSize *= nullDev().hwInfo()->simdWidth_ * 4; // threads/wave
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bufferSize *= 256 * 4; // maximum number of waves
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bufferSize *= numShaderEngines;
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newInfos[i].address = AMU_ABI_GLOBAL_RETURN_BUFFER_SIZE;
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newInfos[i].value = bufferSize;
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i++;
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}
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{
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unsigned int bufferSize = cShader->u32GlobalRtnBufSlotShort;
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bufferSize *= 4; // convert from DWORDS to bytes
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//
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// multiply by the maximum number of threads in flight at one time
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//
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// 256 waves * 64 threads/wave * 2 shader engines (for 870)
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//
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bufferSize *= nullDev().hwInfo()->simdWidth_ * 4; // threads/wave
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bufferSize *= 256 * 4; // maximum number of waves
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bufferSize *= numShaderEngines;
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newInfos[i].address = AMU_ABI_GLOBAL_RETURN_BUFFER_SIZE_SHORT;
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newInfos[i].value = bufferSize;
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i++;
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}
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{
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unsigned int bufferSize = cShader->u32GlobalRtnBufSlotByte;
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bufferSize *= 4; // convert from DWORDS to bytes
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//
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// multiply by the maximum number of threads in flight at one time
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//
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// 256 waves * 64 threads/wave * 2 shader engines (for 870)
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//
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bufferSize *= nullDev().hwInfo()->simdWidth_ * 4; // threads/wave
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bufferSize *= 256 * 4; // maximum number of waves
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bufferSize *= numShaderEngines;
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newInfos[i].address = AMU_ABI_GLOBAL_RETURN_BUFFER_SIZE_BYTE;
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newInfos[i].value = bufferSize;
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i++;
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}
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for (unsigned int j = 0; j < SC_R800_MAX_UAV; j++)
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{
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newInfos[i].address = AMU_ABI_OFFSET_TO_UAV0+j;
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newInfos[i].value = j;
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i++;
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}
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for (unsigned int j = 0; j < SC_R800_MAX_UAV; j++)
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{
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// Set up UAV->fetch constant mapping for uncached
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newInfos[i].address = AMU_ABI_UNCACHED_FETCH_CONST_UAV0+j;
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newInfos[i].value = UncachedFetchConst[j];
|
|
i++;
|
|
}
|
|
for (unsigned int j = 0; j < SC_R800_MAX_UAV; j++)
|
|
{
|
|
newInfos[i].address = AMU_ABI_CACHED_FETCH_CONST_UAV0+j;
|
|
newInfos[i].value = CachedFetchConst[j];
|
|
i++;
|
|
}
|
|
for (unsigned int j = 0; j < R800_GLOBAL_RTN_BUF_LAST; j++)
|
|
{
|
|
newInfos[i].address = AMU_ABI_GLOBAL_RETURN_FETCH_CONST0+j;
|
|
newInfos[i].value = GlobalReturnFetchConst[j];
|
|
i++;
|
|
}
|
|
for (unsigned int j = 0; j < R800_GLOBAL_RTN_BUF_LAST; j++)
|
|
{
|
|
newInfos[i].address = AMU_ABI_GLOBAL_RETURN_BUFFER_TYPE0+j;
|
|
newInfos[i].value = GlobalReturnBufferType[j];
|
|
i++;
|
|
}
|
|
for (unsigned int j = 0; j < SC_R800_MAX_UAV; j++)
|
|
{
|
|
newInfos[i].address = AMU_ABI_CACHED_FETCH_CONST64_UAV0+j;
|
|
newInfos[i].value = CachedFetchConst64[j];
|
|
i++;
|
|
}
|
|
for (unsigned int j = 0; j < SC_R800_MAX_UAV; j++)
|
|
{
|
|
newInfos[i].address = AMU_ABI_CACHED_FETCH_CONST128_UAV0+j;
|
|
newInfos[i].value = CachedFetchConst128[j];
|
|
i++;
|
|
}
|
|
|
|
assert(i == infoCount);
|
|
encoding.progInfosCount = infoCount;
|
|
|
|
encoding.uavMask.mask[0] = cShader->u32RatOpIsUsed;
|
|
encoding.textData = HWSHADER_Get(cShader, hShaderMemHandle);
|
|
encoding.textSize = cShader->CodeLenInByte;
|
|
instructionCnt_ = encoding.textSize / sizeof(uint32_t);
|
|
encoding.scratchRegisterCount = cShader->MaxScratchRegsNeeded;
|
|
|
|
uint bufferSize = 0;
|
|
bufferSize = cShader->u32GlobalRtnBufSlot +
|
|
cShader->u32GlobalRtnBufSlotShort + cShader->u32GlobalRtnBufSlotByte;
|
|
bufferSize *= 4; // convert from DWORDS to bytes
|
|
|
|
//
|
|
// multiply by the maximum number of threads in flight at one time
|
|
//
|
|
// 256 waves * 64 threads/wave * 2 shader engines (for 870)
|
|
//
|
|
bufferSize *= nullDev().hwInfo()->simdWidth_ * 4; // threads/wave
|
|
bufferSize *= 256 * 4; // maximum number of waves
|
|
|
|
bufferSize *= numShaderEngines;
|
|
encoding.UAVReturnBufferTotalSize = bufferSize;
|
|
|
|
return true;
|
|
}
|
|
|
|
} // namespace gpu
|
|
|