Jatin Chaudhary
273 строки
10 KiB
C++
273 строки
10 KiB
C++
/*
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Copyright (c) 2022 Advanced Micro Devices, Inc. All rights reserved.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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/* Test Case Description:
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Scenario 1: The test validates if fine grain
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behavior is observed or not with memory allocated using hipHostMalloc()
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Scenario 2: The test validates if fine grain
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behavior is observed or not with memory allocated using hipMallocManaged()
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Scenario 3: The test validates if memory access is fine
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with memory allocated using hipMallocManaged() and CoarseGrain Advise
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Scenario 4: The test validates if memory access is fine
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with memory allocated using hipMalloc() and CoarseGrain Advise
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Scenario 5: The test validates if fine grain
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behavior is observed or not with memory allocated using
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hipExtMallocWithFlags()*/
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#include <hip_test_common.hh>
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#include <chrono>
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__global__ void CoherentTst(int* ptr) { // ptr was set to 1
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atomicAdd(ptr, 1); // now ptr is 2
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while (atomicCAS(ptr, 3, 4) != 3) { // wait till ptr is 3, then change it to 4
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}
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}
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__global__ void SquareKrnl(int *ptr) {
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// ptr value squared here
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*ptr = (*ptr) * (*ptr);
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}
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// The variable below will work as signal to decide pass/fail
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static bool YES_COHERENT = false;
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// The function tests the coherency of allocated memory
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// If this test hangs, means there is issue in coherency
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static void TstCoherency(int* ptr, bool hmmMem) {
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int* dptr = nullptr;
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hipStream_t stream{};
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HIP_CHECK(hipStreamCreate(&stream));
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// storing value 1 in the memory created above
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*ptr = 1;
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if (!hmmMem) {
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HIP_CHECK(hipHostGetDevicePointer(reinterpret_cast<void**>(&dptr), ptr, 0));
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CoherentTst<<<1, 1, 0, stream>>>(dptr);
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} else {
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CoherentTst<<<1, 1, 0, stream>>>(ptr);
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}
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std::chrono::steady_clock::time_point start = std::chrono::steady_clock::now();
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while (std::chrono::duration_cast<std::chrono::seconds>(std::chrono::steady_clock::now() - start)
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.count() < 3 &&
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*ptr == 2) {
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} // wait till ptr is 2 from kernel or 3 seconds
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*ptr += 1; // increment it to 3
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HIP_CHECK(hipStreamSynchronize(stream));
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HIP_CHECK(hipStreamDestroy(stream));
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if (*ptr == 4) {
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YES_COHERENT = true;
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}
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}
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/* Test case description: The following test validates if fine grain
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behavior is observed or not with memory allocated using hipHostMalloc()*/
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// The following tests are disabled for Nvidia as they are not consistently
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// passing
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#if HT_AMD
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TEST_CASE("Unit_hipHostMalloc_CoherentTst") {
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int *Ptr = nullptr, SIZE = sizeof(int), Pageable = 0;
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bool HmmMem = false;
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YES_COHERENT = false;
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HIP_CHECK(hipDeviceGetAttribute(&Pageable,
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hipDeviceAttributePageableMemoryAccess, 0));
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INFO("hipDeviceAttributePageableMemoryAccess: " << Pageable);
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if (Pageable == 1) {
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// Allocating hipHostMalloc() memory with hipHostMallocCoherent flag
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SECTION("hipHostMalloc with hipHostMallocCoherent flag") {
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HIP_CHECK(hipHostMalloc(&Ptr, SIZE, hipHostMallocCoherent));
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}
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SECTION("hipHostMalloc with Default flag") {
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HIP_CHECK(hipHostMalloc(&Ptr, SIZE));
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}
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SECTION("hipHostMalloc with hipHostMallocMapped flag") {
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HIP_CHECK(hipHostMalloc(&Ptr, SIZE, hipHostMallocMapped));
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}
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TstCoherency(Ptr, HmmMem);
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HIP_CHECK(hipHostFree(Ptr));
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REQUIRE(YES_COHERENT);
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} else {
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SUCCEED("GPU 0 doesn't support hipDeviceAttributePageableMemoryAccess "
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"attribute. Hence skipping the test with Pass result.\n");
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}
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}
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#endif
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/* Test case description: The following test validates if fine grain
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behavior is observed or not with memory allocated using hipMallocManaged()*/
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// The following tests are disabled for Nvidia as they are not consistently
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// passing
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#if HT_AMD
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TEST_CASE("Unit_hipMallocManaged_CoherentTst") {
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int *Ptr = nullptr, SIZE = sizeof(int), Pageable = 0, managed = 0;
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bool HmmMem = true;
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YES_COHERENT = false;
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HIP_CHECK(hipDeviceGetAttribute(&Pageable,
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hipDeviceAttributePageableMemoryAccess, 0));
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INFO("hipDeviceAttributePageableMemoryAccess: " << Pageable);
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HIP_CHECK(hipDeviceGetAttribute(&managed, hipDeviceAttributeManagedMemory,
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0));
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INFO("hipDeviceAttributeManagedMemory: " << managed);
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if (managed == 1 && Pageable == 1) {
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// Allocating hipMallocManaged() memory
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SECTION("hipMallocManaged with hipMemAttachGlobal flag") {
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HIP_CHECK(hipMallocManaged(&Ptr, SIZE, hipMemAttachGlobal));
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}
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SECTION("hipMallocManaged with hipMemAttachHost flag") {
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HIP_CHECK(hipMallocManaged(&Ptr, SIZE, hipMemAttachHost));
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}
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TstCoherency(Ptr, HmmMem);
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HIP_CHECK(hipFree(Ptr));
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REQUIRE(YES_COHERENT);
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} else {
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SUCCEED("GPU 0 doesn't support ManagedMemory or PageableMemoryAccess"
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"device attribute. Hence skipping the test with Pass result.\n");
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}
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}
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#endif
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/* Test case description: The following test validates if memory access is fine
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with memory allocated using hipMallocManaged() and CoarseGrain Advise*/
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TEST_CASE("Unit_hipMallocManaged_CoherentTstWthAdvise") {
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int *Ptr = nullptr, SIZE = sizeof(int), managed = 0;
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YES_COHERENT = false;
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HIP_CHECK(hipDeviceGetAttribute(&managed, hipDeviceAttributeManagedMemory,
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0));
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INFO("hipDeviceAttributeManagedMemory: " << managed);
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if (managed == 1) {
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// Allocating hipMallocManaged() memory
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SECTION("hipMallocManaged with hipMemAttachGlobal flag") {
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HIP_CHECK(hipMallocManaged(&Ptr, SIZE, hipMemAttachGlobal));
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}
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SECTION("hipMallocManaged with hipMemAttachHost flag") {
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HIP_CHECK(hipMallocManaged(&Ptr, SIZE, hipMemAttachHost));
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}
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#if HT_AMD
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HIP_CHECK(hipMemAdvise(Ptr, SIZE, hipMemAdviseSetCoarseGrain, 0));
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#endif
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// Initializing Ptr memory with 9
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*Ptr = 9;
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hipStream_t strm;
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HIP_CHECK(hipStreamCreate(&strm));
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SquareKrnl<<<1, 1, 0, strm>>>(Ptr);
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HIP_CHECK(hipStreamSynchronize(strm));
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if (*Ptr == 81) {
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YES_COHERENT = true;
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}
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HIP_CHECK(hipFree(Ptr));
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HIP_CHECK(hipStreamDestroy(strm));
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REQUIRE(YES_COHERENT);
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} else {
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SUCCEED("GPU 0 doesn't support hipDeviceAttributeManagedMemory "
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"attribute. Hence skipping the test with Pass result.\n");
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}
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}
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/* Test case description: The following test validates if memory allocated
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using hipMalloc() are of type Coarse Grain*/
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// The following tests are disabled for Nvidia as they are not applicable
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#if HT_AMD
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TEST_CASE("Unit_hipMalloc_CoherentTst") {
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int *Ptr = nullptr, SIZE = sizeof(int);
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uint32_t svm_attrib = 0;
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bool IfTstPassed = false;
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// Allocating hipMalloc() memory
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HIP_CHECK(hipMalloc(&Ptr, SIZE));
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HIP_CHECK(hipMemRangeGetAttribute(&svm_attrib, sizeof(svm_attrib),
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hipMemRangeAttributeCoherencyMode, Ptr, SIZE));
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if (svm_attrib == hipMemRangeCoherencyModeCoarseGrain) {
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IfTstPassed = true;
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}
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HIP_CHECK(hipFree(Ptr));
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REQUIRE(IfTstPassed);
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}
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#endif
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/* Test case description: The following test validates if fine grain
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behavior is observed or not with memory allocated using
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hipExtMallocWithFlags()*/
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#if HT_AMD
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TEST_CASE("Unit_hipExtMallocWithFlags_CoherentTst") {
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int *Ptr = nullptr, SIZE = sizeof(int), InitVal = 9, Pageable = 0, managed = 0;
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bool FineGrain = true;
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YES_COHERENT = false;
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HIP_CHECK(hipDeviceGetAttribute(&Pageable,
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hipDeviceAttributePageableMemoryAccess, 0));
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INFO("hipDeviceAttributePageableMemoryAccess: " << Pageable);
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HIP_CHECK(hipDeviceGetAttribute(&managed, hipDeviceAttributeManagedMemory,
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0));
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INFO("hipDeviceAttributeManagedMemory: " << managed);
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if (managed == 1 && Pageable == 1) {
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// Allocating hipExtMallocWithFlags() memory with flags
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SECTION("hipExtMallocWithFlags with hipDeviceMallocFinegrained flag") {
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HIP_CHECK(hipExtMallocWithFlags(reinterpret_cast<void**>(&Ptr), SIZE*2,
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hipDeviceMallocFinegrained));
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}
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SECTION("hipExtMallocWithFlags with hipDeviceMallocSignalMemory flag") {
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// for hipMallocSignalMemory flag the size of memory must be 8
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HIP_CHECK(hipExtMallocWithFlags(reinterpret_cast<void**>(&Ptr), SIZE*2,
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hipMallocSignalMemory));
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}
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SECTION("hipExtMallocWithFlags with hipDeviceMallocDefault flag") {
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/* hipExtMallocWithFlags() with flag
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hipDeviceMallocDefault allocates CoarseGrain memory */
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FineGrain = false;
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HIP_CHECK(hipExtMallocWithFlags(reinterpret_cast<void**>(&Ptr), SIZE*2,
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hipDeviceMallocDefault));
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}
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if (FineGrain) {
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TstCoherency(Ptr, FineGrain);
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} else {
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*Ptr = InitVal;
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hipStream_t strm;
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HIP_CHECK(hipStreamCreate(&strm));
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SquareKrnl<<<1, 1, 0, strm>>>(Ptr);
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HIP_CHECK(hipStreamSynchronize(strm));
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if (*Ptr == (InitVal * InitVal)) {
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YES_COHERENT = true;
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}
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}
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HIP_CHECK(hipFree(Ptr));
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REQUIRE(YES_COHERENT);
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} else {
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SUCCEED("GPU 0 doesn't support ManagedMemory or PageableMemoryAccess"
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"device attribute. Hence skipping the test with Pass result.\n");
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}
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}
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#endif
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