Ma, Bing
a75174f855
* Clean up obsolete SPM logics
* Add PERFCOUNTER_SELECT1 to CounterRegInfo
* Add RLC_SPM_PERFMON_SAMPLE_DELAY_MAX
[ROCm/aqlprofile commit: 6f236ffb5f]
445 lines
20 KiB
C++
445 lines
20 KiB
C++
// MIT License
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//
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// Copyright (c) 2017-2025 Advanced Micro Devices, Inc.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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#ifndef _GFX11_BLOCKTABLE_H_
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#define _GFX11_BLOCKTABLE_H_
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namespace gfxip {
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namespace gfx11 {
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/*
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* CPC CORRECT
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*/
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static const CounterRegInfo CpcCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER1_HI), REG_32B_NULL}};
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/*
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* CPF CORRECT
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*/
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static const CounterRegInfo CpfCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER1_HI), REG_32B_NULL}};
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/*
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* GDS CORRECT
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*/
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static const CounterRegInfo GdsCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER1_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER2_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER3_HI), REG_32B_NULL}};
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/*
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* GRBM CORRECT
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*/
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static const CounterRegInfo GrbmCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER1_HI), REG_32B_NULL}};
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/*
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* GRBM_SE CORRECT
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*/
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static const CounterRegInfo GrbmSeCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regGRBM_SE0_PERFCOUNTER_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGRBM_SE0_PERFCOUNTER_LO),
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REG_32B_ADDR(GC, 0, regGRBM_SE0_PERFCOUNTER_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGRBM_SE1_PERFCOUNTER_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGRBM_SE1_PERFCOUNTER_LO),
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REG_32B_ADDR(GC, 0, regGRBM_SE1_PERFCOUNTER_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGRBM_SE2_PERFCOUNTER_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGRBM_SE2_PERFCOUNTER_LO),
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REG_32B_ADDR(GC, 0, regGRBM_SE2_PERFCOUNTER_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGRBM_SE3_PERFCOUNTER_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGRBM_SE3_PERFCOUNTER_LO),
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REG_32B_ADDR(GC, 0, regGRBM_SE3_PERFCOUNTER_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGRBM_SE4_PERFCOUNTER_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGRBM_SE4_PERFCOUNTER_LO),
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REG_32B_ADDR(GC, 0, regGRBM_SE4_PERFCOUNTER_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGRBM_SE5_PERFCOUNTER_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGRBM_SE5_PERFCOUNTER_LO),
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REG_32B_ADDR(GC, 0, regGRBM_SE5_PERFCOUNTER_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGRBM_SE6_PERFCOUNTER_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGRBM_SE6_PERFCOUNTER_LO),
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REG_32B_ADDR(GC, 0, regGRBM_SE6_PERFCOUNTER_HI), REG_32B_NULL}};
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/*
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* SPI CORRECT
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*/
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static const CounterRegInfo SpiCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER1_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER2_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER3_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER4_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER4_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER5_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER5_HI), REG_32B_NULL}};
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/*
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* SQ CORRECT
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*/
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static const CounterRegInfo SqCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER0_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER0_LO), REG_32B_NULL, REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER2_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER1_LO), REG_32B_NULL, REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER4_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER2_LO), REG_32B_NULL, REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER6_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER3_LO), REG_32B_NULL, REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER8_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER4_LO), REG_32B_NULL, REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER10_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER5_LO), REG_32B_NULL, REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER12_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER6_LO), REG_32B_NULL, REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER14_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER7_LO), REG_32B_NULL, REG_32B_NULL}};
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/*
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* SX CORRECT
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*/
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static const CounterRegInfo SxCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER1_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER2_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER3_HI), REG_32B_NULL}};
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/*
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* GCEA
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*/
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static const CounterRegInfo GceaCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER0_CFG),
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REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_RSLT_CNTL),
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REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER1_CFG),
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REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_RSLT_CNTL),
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REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_HI), REG_32B_NULL}};
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// Define GFX10 specific blocks table entries like GC caches blocks
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/*
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* GCR CORRECT
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*/
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static const CounterRegInfo GcrCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regGCR_PERFCOUNTER0_SELECT), REG_32B_ADDR(GC, 0, regGCR_GENERAL_CNTL),
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REG_32B_ADDR(GC, 0, regGCR_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGCR_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGCR_PERFCOUNTER1_SELECT), REG_32B_ADDR(GC, 0, regGCR_GENERAL_CNTL),
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REG_32B_ADDR(GC, 0, regGCR_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGCR_PERFCOUNTER1_HI), REG_32B_NULL}};
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/*
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* TCP
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*/
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static const CounterRegInfo TcpCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER1_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER2_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER3_HI), REG_32B_NULL}};
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/*
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* GL1A CORRECT
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*/
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static const CounterRegInfo Gl1aCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER1_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER2_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER3_HI), REG_32B_NULL},
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};
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/*
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* GL1C CORRECT
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*/
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static const CounterRegInfo Gl1cCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER1_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER2_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER3_HI), REG_32B_NULL},
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};
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/*
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* GL2A CORRECT
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*/
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static const CounterRegInfo Gl2aCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER1_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER2_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER3_HI), REG_32B_NULL},
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};
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/*
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* GL2C CORRECT
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*/
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static const CounterRegInfo Gl2cCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER1_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER2_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER3_HI), REG_32B_NULL},
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};
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/*
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* GUS ????? need more investigations
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*/
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static const CounterRegInfo GusCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regGUS_PERFCOUNTER0_CFG),
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REG_32B_ADDR(GC, 0, regGUS_PERFCOUNTER_RSLT_CNTL), REG_32B_ADDR(GC, 0, regGUS_PERFCOUNTER_LO),
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REG_32B_ADDR(GC, 0, regGUS_PERFCOUNTER_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGUS_PERFCOUNTER1_CFG),
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REG_32B_ADDR(GC, 0, regGUS_PERFCOUNTER_RSLT_CNTL), REG_32B_ADDR(GC, 0, regGUS_PERFCOUNTER2_LO),
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REG_32B_ADDR(GC, 0, regGUS_PERFCOUNTER2_HI), REG_32B_NULL},
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};
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/*
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* TA CORRECT
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*/
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static const CounterRegInfo TaCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER1_HI), REG_32B_NULL}};
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// Counter block CPC
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static const GpuBlockInfo CpcCounterBlockInfo = {
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|
"CPC",
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CpcCounterBlockId,
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1,
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|
CpcCounterBlockMaxEvent,
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|
CpcCounterBlockNumCounters,
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|
CpcCounterRegAddr,
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gfx11_cntx_prim::select_value_CPC_PERFCOUNTER0_SELECT,
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CounterBlockDfltAttr | CounterBlockSpmGlobalAttr,
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|
BLOCK_DELAY_NONE};
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// Counter block CPF
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static const GpuBlockInfo CpfCounterBlockInfo = {
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"CPF",
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CpfCounterBlockId,
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1,
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CpfCounterBlockMaxEvent,
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|
CpfCounterBlockNumCounters,
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|
CpfCounterRegAddr,
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gfx11_cntx_prim::select_value_CPF_PERFCOUNTER0_SELECT,
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CounterBlockDfltAttr | CounterBlockSpmGlobalAttr,
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|
BLOCK_DELAY_NONE};
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// Counter block GDS
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static const GpuBlockInfo GdsCounterBlockInfo = {
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"GDS",
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GdsCounterBlockId,
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1,
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GdsCounterBlockMaxEvent,
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|
GdsCounterBlockNumCounters,
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|
GdsCounterRegAddr,
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gfx11_cntx_prim::select_value_GDS_PERFCOUNTER0_SELECT,
|
|
CounterBlockDfltAttr | CounterBlockSpmGlobalAttr,
|
|
BLOCK_DELAY_NONE};
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|
// Counter block GRBM
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static const GpuBlockInfo GrbmCounterBlockInfo = {
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"GRBM",
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|
GrbmCounterBlockId,
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|
1,
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GrbmCounterBlockMaxEvent,
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|
GrbmCounterBlockNumCounters,
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|
GrbmCounterRegAddr,
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|
gfx11_cntx_prim::select_value_GRBM_PERFCOUNTER0_SELECT,
|
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CounterBlockDfltAttr | CounterBlockGRBMAttr,
|
|
BLOCK_DELAY_NONE};
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|
// Counter block GRBMSE
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|
static const GpuBlockInfo GrbmSeCounterBlockInfo = {
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|
"GRBM_SE",
|
|
GrbmSeCounterBlockId,
|
|
1,
|
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GrbmSeCounterBlockMaxEvent,
|
|
GrbmSeCounterBlockNumCounters,
|
|
GrbmSeCounterRegAddr,
|
|
gfx11_cntx_prim::select_value_GRBM_SE0_PERFCOUNTER_SELECT,
|
|
CounterBlockDfltAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block SPI
|
|
static const GpuBlockInfo SpiCounterBlockInfo = {
|
|
"SPI",
|
|
SpiCounterBlockId,
|
|
1,
|
|
SpiCounterBlockMaxEvent,
|
|
SpiCounterBlockNumCounters,
|
|
SpiCounterRegAddr,
|
|
gfx11_cntx_prim::select_value_SPI_PERFCOUNTER0_SELECT,
|
|
CounterBlockSeAttr | CounterBlockSPIAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block SQ
|
|
static const GpuBlockInfo SqCounterBlockInfo = {
|
|
"SQ",
|
|
SqCounterBlockId,
|
|
1,
|
|
SqCounterBlockMaxEvent,
|
|
SqCounterBlockNumCounters,
|
|
SqCounterRegAddr,
|
|
gfx11_cntx_prim::sq_select_value,
|
|
CounterBlockSeAttr | CounterBlockSqAttr | CounterBlockSaAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block SX
|
|
static const GpuBlockInfo SxCounterBlockInfo = {
|
|
"SX",
|
|
SxCounterBlockId,
|
|
1,
|
|
SxCounterBlockMaxEvent,
|
|
SxCounterBlockNumCounters,
|
|
SxCounterRegAddr,
|
|
gfx11_cntx_prim::select_value_SX_PERFCOUNTER0_SELECT,
|
|
CounterBlockSeAttr | CounterBlockCleanAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block GCEA
|
|
static const GpuBlockInfo GceaCounterBlockInfo = {
|
|
"GCEA",
|
|
GceaCounterBlockId,
|
|
GceaCounterBlockNumInstances,
|
|
GceaCounterBlockMaxEvent,
|
|
GceaCounterBlockNumCounters,
|
|
GceaCounterRegAddr,
|
|
gfx11_cntx_prim::mc_select_value_GCEA_PERFCOUNTER0_CFG,
|
|
CounterBlockMcAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block TCP
|
|
static const GpuBlockInfo TcpCounterBlockInfo = {
|
|
"TCP",
|
|
TcpCounterBlockId,
|
|
16,
|
|
TcpCounterBlockMaxEvent,
|
|
TcpCounterBlockNumCounters,
|
|
TcpCounterRegAddr,
|
|
gfx11_cntx_prim::select_value_TCP_PERFCOUNTER0_SELECT,
|
|
CounterBlockDfltAttr | CounterBlockSeAttr | CounterBlockSaAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block GL1A
|
|
static const GpuBlockInfo Gl1aCounterBlockInfo = {
|
|
"GL1A",
|
|
Gl1aCounterBlockId,
|
|
4,
|
|
Gl1aCounterBlockMaxEvent,
|
|
Gl1aCounterBlockNumCounters,
|
|
Gl1aCounterRegAddr,
|
|
gfx11_cntx_prim::select_value_TCP_PERFCOUNTER0_SELECT,
|
|
CounterBlockDfltAttr | CounterBlockSeAttr | CounterBlockSaAttr | CounterBlockTcAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block GL1C
|
|
static const GpuBlockInfo Gl1cCounterBlockInfo = {
|
|
"GL1C",
|
|
Gl1cCounterBlockId,
|
|
4,
|
|
Gl1cCounterBlockMaxEvent,
|
|
Gl1cCounterBlockNumCounters,
|
|
Gl1cCounterRegAddr,
|
|
gfx11_cntx_prim::select_value_TCP_PERFCOUNTER0_SELECT,
|
|
CounterBlockDfltAttr | CounterBlockSeAttr | CounterBlockSaAttr | CounterBlockTcAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block GL2A
|
|
static const GpuBlockInfo Gl2aCounterBlockInfo = {
|
|
"GL2A",
|
|
Gl2aCounterBlockId,
|
|
32,
|
|
Gl2aCounterBlockMaxEvent,
|
|
Gl2aCounterBlockNumCounters,
|
|
Gl2aCounterRegAddr,
|
|
gfx11_cntx_prim::select_value_TCP_PERFCOUNTER0_SELECT,
|
|
CounterBlockDfltAttr | CounterBlockTcAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block GL2C
|
|
static const GpuBlockInfo Gl2cCounterBlockInfo = {
|
|
"GL2C",
|
|
Gl2cCounterBlockId,
|
|
32,
|
|
Gl2cCounterBlockMaxEvent,
|
|
Gl2cCounterBlockNumCounters,
|
|
Gl2cCounterRegAddr,
|
|
gfx11_cntx_prim::select_value_TCP_PERFCOUNTER0_SELECT,
|
|
CounterBlockDfltAttr | CounterBlockTcAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block GCR
|
|
static const GpuBlockInfo GcrCounterBlockInfo = {
|
|
"GCR",
|
|
GcrCounterBlockId,
|
|
1,
|
|
GcrCounterBlockMaxEvent,
|
|
GcrCounterBlockNumCounters,
|
|
GcrCounterRegAddr,
|
|
gfx11_cntx_prim::select_value_TCP_PERFCOUNTER0_SELECT,
|
|
CounterBlockTcAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block GUS
|
|
static const GpuBlockInfo GusCounterBlockInfo = {
|
|
"GUS",
|
|
GusCounterBlockId,
|
|
1,
|
|
GusCounterBlockMaxEvent,
|
|
GusCounterBlockNumCounters,
|
|
GusCounterRegAddr,
|
|
gfx11_cntx_prim::mc_select_value_RPB_PERFCOUNTER0_CFG,
|
|
CounterBlockGusAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block TA
|
|
static const GpuBlockInfo TaCounterBlockInfo = {
|
|
"TA",
|
|
TaCounterBlockId,
|
|
TaCounterBlockNumInstances,
|
|
235 /*TaCounterBlockMaxEvent*/,
|
|
TaCounterBlockNumCounters,
|
|
TaCounterRegAddr,
|
|
gfx11_cntx_prim::select_value_TA_PERFCOUNTER0_SELECT,
|
|
CounterBlockSeAttr | CounterBlockTcAttr,
|
|
BLOCK_DELAY_NONE};
|
|
|
|
} // namespace gfx11
|
|
} // namespace gfxip
|
|
|
|
#endif // _GFX11_BLOCKTABLE_H_
|