foreman
c19449d03c
SWDEV-95919 - Correct PerfCounters BlockIndex for gfx9. Affected files ... ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palcounters.cpp#12 edit ... //depot/stg/opencl/drivers/opencl/tests/ocltst/module/runtime/OCLPerfCounters.cpp#37 edit
584 строки
16 KiB
C++
584 строки
16 KiB
C++
//
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// Copyright (c) 2015 Advanced Micro Devices, Inc. All rights reserved.
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//
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#include "device/pal/palcounters.hpp"
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#include "device/pal/palvirtual.hpp"
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#include <array>
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namespace pal {
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PalCounterReference* PalCounterReference::Create(VirtualGPU& gpu) {
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Pal::Result result;
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// Create performance experiment
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Pal::PerfExperimentCreateInfo createInfo = {};
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createInfo.optionFlags.sampleInternalOperations = 1;
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createInfo.optionFlags.cacheFlushOnCounterCollection = 1;
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createInfo.optionFlags.sqShaderMask = 1;
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createInfo.optionValues.sampleInternalOperations = true;
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createInfo.optionValues.cacheFlushOnCounterCollection = true;
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createInfo.optionValues.sqShaderMask = Pal::PerfShaderMaskCs;
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size_t palExperSize = gpu.dev().iDev()->GetPerfExperimentSize(createInfo, &result);
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if (result != Pal::Result::Success) {
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return nullptr;
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}
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PalCounterReference* memRef = new (palExperSize) PalCounterReference(gpu);
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if (memRef != nullptr) {
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result = gpu.dev().iDev()->CreatePerfExperiment(createInfo, &memRef[1], &memRef->perfExp_);
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if (result != Pal::Result::Success) {
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memRef->release();
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return nullptr;
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}
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}
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return memRef;
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}
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PalCounterReference::~PalCounterReference() {
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// The counter object is always associated with a particular queue,
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// so we have to lock just this queue
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amd::ScopedLock lock(gpu_.execution());
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if (layout_ != nullptr) {
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delete layout_;
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}
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if (memory_ != nullptr) {
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delete memory_;
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}
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if (nullptr != iPerf()) {
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iPerf()->Destroy();
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}
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}
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uint64_t PalCounterReference::result(const std::vector<int>& index) {
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if (index.size() == 0) {
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// These are counters that have no corresponding PalSample created
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return 0;
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}
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if (layout_ == nullptr) {
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return 0;
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}
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uint64_t result = 0;
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for (auto const& i : index) {
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assert(i <= static_cast<int>(layout_->sampleCount) && "index not in range");
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const Pal::GlobalSampleLayout& sample = layout_->samples[i];
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if (sample.dataType == Pal::PerfCounterDataType::Uint32) {
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uint32_t beginVal =
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*reinterpret_cast<uint32_t*>(reinterpret_cast<char*>(cpuAddr_) + sample.beginValueOffset);
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uint32_t endVal =
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*reinterpret_cast<uint32_t*>(reinterpret_cast<char*>(cpuAddr_) + sample.endValueOffset);
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result += (endVal - beginVal);
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} else if (sample.dataType == Pal::PerfCounterDataType::Uint64) {
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uint64_t beginVal =
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*reinterpret_cast<uint64_t*>(reinterpret_cast<char*>(cpuAddr_) + sample.beginValueOffset);
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uint64_t endVal =
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*reinterpret_cast<uint64_t*>(reinterpret_cast<char*>(cpuAddr_) + sample.endValueOffset);
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result += (endVal - beginVal);
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} else {
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assert(0 && "dataType should be either Uint32 or Uint64");
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return 0;
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}
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}
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return result;
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}
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bool PalCounterReference::finalize() {
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Pal::Result result;
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iPerf()->Finalize();
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// Acquire GPU memory for the query from the pool and bind it.
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Pal::GpuMemoryRequirements gpuMemReqs = {};
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iPerf()->GetGpuMemoryRequirements(&gpuMemReqs);
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memory_ = new Memory(gpu().dev(), amd::alignUp(gpuMemReqs.size, gpuMemReqs.alignment));
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if (nullptr == memory_) {
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return false;
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}
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if (!memory_->create(Resource::Remote)) {
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return false;
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}
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cpuAddr_ = memory_->cpuMap(gpu_);
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if (nullptr == cpuAddr_) {
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return false;
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}
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gpu_.queue(gpu_.engineID_).addMemRef(memory_->iMem());
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result = iPerf()->BindGpuMemory(memory_->iMem(), 0);
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if (result == Pal::Result::Success) {
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Pal::GlobalCounterLayout layout = {};
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iPerf()->GetGlobalCounterLayout(&layout);
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assert(layout.sampleCount == numExpCounters_);
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size_t size = sizeof(Pal::GlobalCounterLayout) +
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(sizeof(Pal::GlobalSampleLayout) * (layout.sampleCount - 1));
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layout_ = reinterpret_cast<Pal::GlobalCounterLayout*>(new char[size]);
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if (layout_ != nullptr) {
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layout_->sampleCount = layout.sampleCount;
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iPerf()->GetGlobalCounterLayout(layout_);
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}
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return true;
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} else {
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return false;
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}
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}
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static const std::array<PCIndexSelect, 0x20> blockIdToIndexSelect = {{
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PCIndexSelect::None, // CPF
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PCIndexSelect::ShaderEngine, // IA
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PCIndexSelect::ShaderEngine, // VGT
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PCIndexSelect::ShaderEngine, // PA
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PCIndexSelect::ShaderEngine, // SC
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PCIndexSelect::ShaderEngine, // SPI
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PCIndexSelect::ShaderEngine, // SQ
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PCIndexSelect::ShaderEngine, // SX
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PCIndexSelect::ShaderEngineAndInstance, // TA
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PCIndexSelect::ShaderEngineAndInstance, // TD
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PCIndexSelect::ShaderEngineAndInstance, // TCP
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PCIndexSelect::Instance, // TCC
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PCIndexSelect::Instance, // TCA
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PCIndexSelect::ShaderEngineAndInstance, // DB
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PCIndexSelect::ShaderEngineAndInstance, // CB
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PCIndexSelect::None, // GDS
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PCIndexSelect::None, // SRBM
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PCIndexSelect::None, // GRBM
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PCIndexSelect::None, // GRBMSE
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PCIndexSelect::None, // RLC
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PCIndexSelect::None, // DMA
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PCIndexSelect::None, // MC
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PCIndexSelect::None, // CPG
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PCIndexSelect::None, // CPC
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PCIndexSelect::None, // WD
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PCIndexSelect::None, // TCS
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PCIndexSelect::None, // UTC12
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}};
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// Converting from ORCA cmndefs.h to PAL palPerfExperiment.h
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static const std::array<std::pair<int, int>, 83> ciBlockIdOrcaToPal = {{
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{0x0E, 0}, // CB0
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{0x0E, 1}, // CB1
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{0x0E, 2}, // CB2
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{0x0E, 3}, // CB3
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{0x00, 0}, // CPF
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{0x0D, 0}, // DB0
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{0x0D, 1}, // DB1
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{0x0D, 2}, // DB2
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{0x0D, 3}, // DB3
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{0x11, 0}, // GRBM
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{0x12, 0}, // GRBMSE
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{0x03, 0}, // PA_SU
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{0x03, 0}, // PA_SC
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{0x05, 0}, // SPI
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{0x06, 0}, // SQ
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{0x06, 0}, // SQ_ES
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{0x06, 0}, // SQ_GS
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{0x06, 0}, // SQ_VS
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{0x06, 0}, // SQ_PS
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{0x06, 0}, // SQ_LS
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{0x06, 0}, // SQ_HS
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{0x06, 0}, // SQ_CS
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{0x07, 0}, // SX
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{0x08, 0}, // TA0
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{0x08, 1}, // TA1
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{0x08, 2}, // TA2
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{0x08, 3}, // TA3
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{0x08, 4}, // TA4
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{0x08, 5}, // TA5
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{0x08, 6}, // TA6
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{0x08, 7}, // TA7
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{0x08, 8}, // TA8
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{0x08, 9}, // TA9
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{0x08, 0x0a}, // TA10
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{0x0C, 0}, // TCA0
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{0x0C, 1}, // TCA1
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{0x0B, 0}, // TCC0
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{0x0B, 1}, // TCC1
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{0x0B, 2}, // TCC2
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{0x0B, 3}, // TCC3
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{0x0B, 4}, // TCC4
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{0x0B, 5}, // TCC5
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{0x0B, 6}, // TCC6
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{0x0B, 7}, // TCC7
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{0x0B, 8}, // TCC8
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{0x0B, 9}, // TCC9
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{0x0B, 0x0a}, // TCC10
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{0x0B, 0x0b}, // TCC11
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{0x0B, 0x0c}, // TCC12
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{0x0B, 0x0d}, // TCC13
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{0x0B, 0x0e}, // TCC14
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{0x0B, 0x0f}, // TCC15
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{0x09, 0}, // TD0
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{0x09, 1}, // TD1
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{0x09, 2}, // TD2
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{0x09, 3}, // TD3
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{0x09, 4}, // TD4
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{0x09, 5}, // TD5
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{0x09, 6}, // TD6
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{0x09, 7}, // TD7
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{0x09, 8}, // TD8
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{0x09, 9}, // TD9
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{0x09, 0x0a}, // TD10
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{0x0A, 0}, // TCP0
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{0x0A, 1}, // TCP1
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{0x0A, 2}, // TCP2
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{0x0A, 3}, // TCP3
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{0x0A, 4}, // TCP4
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{0x0A, 5}, // TCP5
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{0x0A, 6}, // TCP6
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{0x0A, 7}, // TCP7
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{0x0A, 8}, // TCP8
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{0x0A, 9}, // TCP9
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{0x0A, 0x0a}, // TCP10
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{0x0F, 0}, // GDS
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{0x02, 0}, // VGT
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{0x01, 0}, // IA
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{0x15, 0}, // MC
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{0x10, 0}, // SRBM
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{0x19, 0}, // TCS
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{0x18, 0}, // WD
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{0x16, 0}, // CPG
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{0x17, 0}, // CPC
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}};
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static const std::array<std::pair<int, int>, 97> viBlockIdOrcaToPal = {{
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{0x0E, 0}, // CB0
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{0x0E, 1}, // CB1
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{0x0E, 2}, // CB2
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{0x0E, 3}, // CB3
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{0x00, 0}, // CPF
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{0x0D, 0}, // DB0
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{0x0D, 1}, // DB1
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{0x0D, 2}, // DB2
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{0x0D, 3}, // DB3
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{0x11, 0}, // GRBM
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{0x12, 0}, // GRBMSE
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{0x03, 0}, // PA_SU
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{0x03, 0}, // PA_SC
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{0x05, 0}, // SPI
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{0x06, 0}, // SQ
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{0x06, 0}, // SQ_ES
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{0x06, 0}, // SQ_GS
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{0x06, 0}, // SQ_VS
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{0x06, 0}, // SQ_PS
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{0x06, 0}, // SQ_LS
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{0x06, 0}, // SQ_HS
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{0x06, 0}, // SQ_CS
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{0x07, 0}, // SX
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{0x08, 0}, // TA0
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{0x08, 1}, // TA1
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{0x08, 2}, // TA2
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{0x08, 3}, // TA3
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{0x08, 4}, // TA4
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{0x08, 5}, // TA5
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{0x08, 6}, // TA6
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{0x08, 7}, // TA7
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{0x08, 8}, // TA8
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{0x08, 9}, // TA9
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{0x08, 0x0a}, // TA10
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{0x08, 0x0b}, // TA11
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{0x08, 0x0c}, // TA12
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{0x08, 0x0d}, // TA13
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{0x08, 0x0e}, // TA14
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{0x08, 0x0f}, // TA15
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{0x0C, 0}, // TCA0
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{0x0C, 1}, // TCA1
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{0x0B, 0}, // TCC0
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{0x0B, 1}, // TCC1
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{0x0B, 2}, // TCC2
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{0x0B, 3}, // TCC3
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{0x0B, 4}, // TCC4
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{0x0B, 5}, // TCC5
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{0x0B, 6}, // TCC6
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{0x0B, 7}, // TCC7
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{0x0B, 8}, // TCC8
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{0x0B, 9}, // TCC9
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{0x0B, 0x0a}, // TCC10
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{0x0B, 0x0b}, // TCC11
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{0x0B, 0x0c}, // TCC12
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{0x0B, 0x0d}, // TCC13
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{0x0B, 0x0e}, // TCC14
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{0x0B, 0x0f}, // TCC15
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{0x09, 0}, // TD0
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{0x09, 1}, // TD1
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{0x09, 2}, // TD2
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{0x09, 3}, // TD3
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{0x09, 4}, // TD4
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{0x09, 5}, // TD5
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{0x09, 6}, // TD6
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{0x09, 7}, // TD7
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{0x09, 8}, // TD8
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{0x09, 9}, // TD9
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{0x09, 0x0a}, // TD10
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{0x09, 0x0b}, // TD11
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{0x09, 0x0c}, // TD12
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{0x09, 0x0d}, // TD13
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{0x09, 0x0e}, // TD14
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{0x09, 0x0f}, // TD15
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{0x0A, 0}, // TCP0
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{0x0A, 1}, // TCP1
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{0x0A, 2}, // TCP2
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{0x0A, 3}, // TCP3
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{0x0A, 4}, // TCP4
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{0x0A, 5}, // TCP5
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{0x0A, 6}, // TCP6
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{0x0A, 7}, // TCP7
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{0x0A, 8}, // TCP8
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{0x0A, 9}, // TCP9
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{0x0A, 0x0a}, // TCP10
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{0x0A, 0x0b}, // TCP11
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{0x0A, 0x0c}, // TCP12
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{0x0A, 0x0d}, // TCP13
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{0x0A, 0x0e}, // TCP14
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{0x0A, 0x0f}, // TCP15
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{0x0F, 0}, // GDS
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{0x02, 0}, // VGT
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{0x01, 0}, // IA
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{0x15, 0}, // MC
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{0x10, 0}, // SRBM
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{0x18, 0}, // WD
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{0x16, 0}, // CPG
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{0x17, 0}, // CPC
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}};
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// The number of counters per block has been increased for gfx9 but this table may not reflect all
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// of them
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// as compute may not use all of them.
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static const std::array<std::pair<int, int>, 97> gfx9BlockIdPal = {{
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{0x0E, 0}, // CB0
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{0x0E, 1}, // CB1
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{0x0E, 2}, // CB2
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{0x0E, 3}, // CB3
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{0x00, 0}, // CPF
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{0x0D, 0}, // DB0
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{0x0D, 1}, // DB1
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{0x0D, 2}, // DB2
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{0x0D, 3}, // DB3
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{0x11, 0}, // GRBM
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{0x12, 0}, // GRBMSE
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{0x03, 0}, // PA_SU
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{0x03, 0}, // PA_SC
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{0x05, 0}, // SPI
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{0x06, 0}, // SQ
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{0x06, 0}, // SQ_ES
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{0x06, 0}, // SQ_GS
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{0x06, 0}, // SQ_VS
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{0x06, 0}, // SQ_PS
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{0x06, 0}, // SQ_LS
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{0x06, 0}, // SQ_HS
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{0x06, 0}, // SQ_CS
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{0x07, 0}, // SX
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{0x08, 0}, // TA0
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{0x08, 1}, // TA1
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{0x08, 2}, // TA2
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{0x08, 3}, // TA3
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{0x08, 4}, // TA4
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{0x08, 5}, // TA5
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{0x08, 6}, // TA6
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{0x08, 7}, // TA7
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{0x08, 8}, // TA8
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{0x08, 9}, // TA9
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{0x08, 0x0a}, // TA10
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{0x08, 0x0b}, // TA11
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{0x08, 0x0c}, // TA12
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{0x08, 0x0d}, // TA13
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{0x08, 0x0e}, // TA14
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{0x08, 0x0f}, // TA15
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{0x0C, 0}, // TCA0
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{0x0C, 1}, // TCA1
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{0x0B, 0}, // TCC0
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{0x0B, 1}, // TCC1
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{0x0B, 2}, // TCC2
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{0x0B, 3}, // TCC3
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{0x0B, 4}, // TCC4
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{0x0B, 5}, // TCC5
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{0x0B, 6}, // TCC6
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{0x0B, 7}, // TCC7
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{0x0B, 8}, // TCC8
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{0x0B, 9}, // TCC9
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{0x0B, 0x0a}, // TCC10
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{0x0B, 0x0b}, // TCC11
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{0x0B, 0x0c}, // TCC12
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{0x0B, 0x0d}, // TCC13
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{0x0B, 0x0e}, // TCC14
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{0x0B, 0x0f}, // TCC15
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{0x09, 0}, // TD0
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{0x09, 1}, // TD1
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{0x09, 2}, // TD2
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{0x09, 3}, // TD3
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{0x09, 4}, // TD4
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{0x09, 5}, // TD5
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{0x09, 6}, // TD6
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{0x09, 7}, // TD7
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{0x09, 8}, // TD8
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{0x09, 9}, // TD9
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{0x09, 0x0a}, // TD10
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{0x09, 0x0b}, // TD11
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{0x09, 0x0c}, // TD12
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{0x09, 0x0d}, // TD13
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{0x09, 0x0e}, // TD14
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{0x09, 0x0f}, // TD15
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{0x0A, 0}, // TCP0
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{0x0A, 1}, // TCP1
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{0x0A, 2}, // TCP2
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{0x0A, 3}, // TCP3
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{0x0A, 4}, // TCP4
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{0x0A, 5}, // TCP5
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{0x0A, 6}, // TCP6
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{0x0A, 7}, // TCP7
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{0x0A, 8}, // TCP8
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{0x0A, 9}, // TCP9
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{0x0A, 0x0a}, // TCP10
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{0x0A, 0x0b}, // TCP11
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{0x0A, 0x0c}, // TCP12
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{0x0A, 0x0d}, // TCP13
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{0x0A, 0x0e}, // TCP14
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{0x0A, 0x0f}, // TCP15
|
|
{0x0F, 0}, // GDS
|
|
{0x02, 0}, // VGT
|
|
{0x01, 0}, // IA
|
|
{0x15, 0}, // MC
|
|
{0x10, 0}, // SRBM
|
|
{0x18, 0}, // WD
|
|
{0x16, 0}, // CPG
|
|
{0x17, 0}, // CPC
|
|
}};
|
|
|
|
void PerfCounter::convertInfo() {
|
|
switch (dev().ipLevel()) {
|
|
case Pal::GfxIpLevel::GfxIp7:
|
|
if (info_.blockIndex_ < ciBlockIdOrcaToPal.size()) {
|
|
auto p = ciBlockIdOrcaToPal[info_.blockIndex_];
|
|
info_.blockIndex_ = std::get<0>(p);
|
|
info_.counterIndex_ = std::get<1>(p);
|
|
}
|
|
break;
|
|
case Pal::GfxIpLevel::GfxIp8:
|
|
if (info_.blockIndex_ < viBlockIdOrcaToPal.size()) {
|
|
auto p = viBlockIdOrcaToPal[info_.blockIndex_];
|
|
info_.blockIndex_ = std::get<0>(p);
|
|
info_.counterIndex_ = std::get<1>(p);
|
|
}
|
|
break;
|
|
case Pal::GfxIpLevel::GfxIp9:
|
|
if (info_.blockIndex_ < gfx9BlockIdPal.size()) {
|
|
auto p = gfx9BlockIdPal[info_.blockIndex_];
|
|
info_.blockIndex_ = std::get<0>(p);
|
|
info_.counterIndex_ = std::get<1>(p);
|
|
}
|
|
break;
|
|
default:
|
|
Unimplemented();
|
|
break;
|
|
}
|
|
|
|
assert(info_.blockIndex_ < blockIdToIndexSelect.size());
|
|
info_.indexSelect_ = blockIdToIndexSelect.at(info_.blockIndex_);
|
|
}
|
|
|
|
PerfCounter::~PerfCounter() {
|
|
if (palRef_ == nullptr) {
|
|
return;
|
|
}
|
|
|
|
// Release the counter reference object
|
|
palRef_->release();
|
|
}
|
|
|
|
bool PerfCounter::create() {
|
|
palRef_->retain();
|
|
|
|
// Initialize the counter
|
|
Pal::PerfCounterInfo counterInfo = {};
|
|
counterInfo.counterType = Pal::PerfCounterType::Global;
|
|
counterInfo.block = static_cast<Pal::GpuBlock>(info_.blockIndex_);
|
|
counterInfo.eventId = info_.eventIndex_;
|
|
|
|
Pal::PerfExperimentProperties perfExpProps;
|
|
Pal::Result result;
|
|
result = dev().iDev()->GetPerfExperimentProperties(&perfExpProps);
|
|
if (result != Pal::Result::Success) {
|
|
return false;
|
|
}
|
|
|
|
const auto& blockProps = perfExpProps.blocks[static_cast<uint32_t>(counterInfo.block)];
|
|
uint32_t counter_start, counter_step;
|
|
|
|
switch (info_.indexSelect_) {
|
|
case PCIndexSelect::ShaderEngine:
|
|
case PCIndexSelect::None:
|
|
counter_start = 0;
|
|
counter_step = 1;
|
|
break;
|
|
|
|
case PCIndexSelect::ShaderEngineAndInstance:
|
|
if (info_.counterIndex_ >=
|
|
dev().properties().gfxipProperties.shaderCore.maxCusPerShaderArray) {
|
|
return true;
|
|
}
|
|
counter_start = info_.counterIndex_;
|
|
counter_step = dev().properties().gfxipProperties.shaderCore.maxCusPerShaderArray;
|
|
break;
|
|
|
|
case PCIndexSelect::Instance:
|
|
counter_start = info_.counterIndex_;
|
|
counter_step = blockProps.instanceCount;
|
|
break;
|
|
|
|
default:
|
|
assert(0 && "Unknown indexSelect_");
|
|
return true;
|
|
}
|
|
|
|
for (uint32_t i = counter_start; i < blockProps.instanceCount; i += counter_step) {
|
|
counterInfo.instance = i;
|
|
result = iPerf()->AddCounter(counterInfo);
|
|
if (result == Pal::Result::Success) {
|
|
index_.push_back(palRef_->getPalCounterIndex());
|
|
} else {
|
|
// Get here when there's no HW PerfCounter matching the counterInfo
|
|
assert(0 && "AddCounter() failed");
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
uint64_t PerfCounter::getInfo(uint64_t infoType) const {
|
|
switch (infoType) {
|
|
case CL_PERFCOUNTER_GPU_BLOCK_INDEX: {
|
|
// Return the GPU block index
|
|
return info()->blockIndex_;
|
|
}
|
|
case CL_PERFCOUNTER_GPU_COUNTER_INDEX: {
|
|
// Return the GPU counter index
|
|
return info()->counterIndex_;
|
|
}
|
|
case CL_PERFCOUNTER_GPU_EVENT_INDEX: {
|
|
// Return the GPU event index
|
|
return info()->eventIndex_;
|
|
}
|
|
case CL_PERFCOUNTER_DATA: {
|
|
return palRef_->result(index_);
|
|
}
|
|
default:
|
|
LogError("Wrong PerfCounter::getInfo parameter");
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
} // namespace pal
|