5c742f3e5e
This test has been intermittently failing for various reasons and was already disabled on all chips except Ellesmere. It stresses memory management in unusual ways by having lots of memory allocated but +# not mapped, which is not relevant to compute applications over ROCr. Change-Id: I6b791ca7e2e0fcfe93fc720063b4b56acfded751 Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>