7bc6aac5d2
Each SE must be assigned equal numbers of slots and slots must be assigned in units of whole groups. Change-Id: I8f3677237fa6f2e2d25e3e78210c5a7a0ad792f3
193 行
5.7 KiB
C++
193 行
5.7 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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//
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// The University of Illinois/NCSA
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// Open Source License (NCSA)
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//
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// Copyright (c) 2020-2020, Advanced Micro Devices, Inc. All rights reserved.
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//
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// Developed by:
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//
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// AMD Research and AMD HSA Software Development
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//
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// Advanced Micro Devices, Inc.
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//
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// www.amd.com
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to
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// deal with the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimers.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimers in
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// the documentation and/or other materials provided with the distribution.
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// - Neither the names of Advanced Micro Devices, Inc,
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// nor the names of its contributors may be used to endorse or promote
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// products derived from this Software without specific prior written
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// permission.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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// DEALINGS WITH THE SOFTWARE.
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//
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////////////////////////////////////////////////////////////////////////////////
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#ifndef HSA_RUNTIME_CORE_INC_SCRATCH_CACHE_H_
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#define HSA_RUNTIME_CORE_INC_SCRATCH_CACHE_H_
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#include "core/inc/amd_gpu_agent.h"
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#include "core/util/locks.h"
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#include "core/util/utils.h"
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#include <map>
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#include <functional>
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namespace rocr {
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namespace AMD {
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class ScratchCache {
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public:
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struct node {
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enum STATE { FREE = 0, ALLOC = 1, TRIM = 2, STEAL = 4 };
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void* base;
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bool large;
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uint32_t state;
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node() : base(nullptr), state(FREE) {}
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bool isFree() const { return state == FREE; }
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bool trimPending() const { return state == (ALLOC | TRIM); }
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void trim() {
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assert(!isFree() && "Trim of free scratch node.");
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state |= TRIM;
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}
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void free() {
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assert(!isFree() && "Free of free scratch node.");
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state = FREE;
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}
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void alloc() {
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assert(isFree() && "Alloc of non-free scratch node.");
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state = ALLOC;
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}
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};
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typedef ::std::multimap<size_t, node> map_t;
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typedef map_t::iterator ref_t;
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typedef ::std::function<void(void*, size_t, bool)> deallocator_t;
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// @brief Contains scratch memory information.
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struct ScratchInfo {
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void* queue_base;
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// Size to fill the machine with size_per_thread
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size_t size;
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// Size to satisfy the present dispatch without throttling.
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size_t dispatch_size;
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size_t size_per_thread;
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uint32_t lanes_per_wave;
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uint32_t waves_per_group;
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ptrdiff_t queue_process_offset;
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bool large;
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bool retry;
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hsa_signal_t queue_retry;
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uint64_t wanted_slots;
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ScratchCache::ref_t scratch_node;
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};
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ScratchCache(const ScratchCache& rhs) = delete;
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ScratchCache(ScratchCache&& rhs) = delete;
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ScratchCache& operator=(const ScratchCache& rhs) = delete;
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ScratchCache& operator=(ScratchCache&& rhs) = delete;
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ScratchCache(deallocator_t deallocator) : dealloc(deallocator) {}
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~ScratchCache() { assert(map.empty() && "ScratchCache not empty at shutdown."); }
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bool alloc(ScratchInfo& info) {
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ref_t it = map.upper_bound(info.size - 1);
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if (it == map.end()) return false;
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// Small requests must have an exact size match and be small.
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if (!info.large) {
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while ((it != map.end()) && (it->first == info.size)) {
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if (it->second.isFree() && (!it->second.large)) {
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it->second.alloc();
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info.queue_base = it->second.base;
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info.scratch_node = it;
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return true;
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}
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it++;
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}
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return false;
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}
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// Large requests may use a small allocation and do not require an exact size match.
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while (it != map.end()) {
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if (it->second.isFree()) {
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it->second.alloc();
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info.queue_base = it->second.base;
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info.size = it->first;
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info.scratch_node = it;
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return true;
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}
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it++;
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}
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return false;
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}
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void free(ScratchInfo& info) {
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assert(!info.scratch_node->second.isFree() && "free called on free scratch node.");
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auto it = info.scratch_node;
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if (it->second.trimPending()) {
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dealloc(it->second.base, it->first, it->second.large);
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map.erase(it);
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return;
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}
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it->second.free();
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}
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bool trim(bool trim_nodes_in_use) {
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bool ret = !map.empty();
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auto it = map.begin();
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while (it != map.end()) {
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if (it->second.isFree()) {
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dealloc(it->second.base, it->first, it->second.large);
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auto temp = it;
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it++;
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map.erase(temp);
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} else {
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if (trim_nodes_in_use) it->second.trim();
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it++;
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}
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}
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return ret;
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}
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void insert(ScratchInfo& info) {
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node n;
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n.base = info.queue_base;
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n.large = info.large;
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n.alloc();
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auto it = map.insert(std::make_pair(info.size, n));
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info.scratch_node = it;
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}
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private:
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map_t map;
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deallocator_t dealloc;
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};
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} // namespace AMD
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} // namespace rocr
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#endif // header guard
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