Ma, Bing
a75174f855
* Clean up obsolete SPM logics
* Add PERFCOUNTER_SELECT1 to CounterRegInfo
* Add RLC_SPM_PERFMON_SAMPLE_DELAY_MAX
[ROCm/aqlprofile commit: 6f236ffb5f]
143 lines
4.0 KiB
C
143 lines
4.0 KiB
C
// MIT License
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//
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// Copyright (c) 2017-2025 Advanced Micro Devices, Inc.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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#ifndef SRC_DEF_GPU_BLOCK_INFO_H_
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#define SRC_DEF_GPU_BLOCK_INFO_H_
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#include <stdint.h>
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#include "util/reg_offsets.h"
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// Counter Block attributes
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enum CounterBlockAttr {
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// Default block attribute
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CounterBlockDfltAttr = 1,
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// Per ShaderEngine blocks
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CounterBlockSeAttr = 2,
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// SQ blocks
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CounterBlockSqAttr = 4,
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// Need to clean counter registers
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CounterBlockCleanAttr = 8,
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// MC Block
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CounterBlockMcAttr = 0x10,
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// CP PERFMON controllable blocks
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CounterBlockCpmonAttr = 0x1f,
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// SDMA block
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CounterBlockSdmaAttr = 0x100,
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// Texture cache
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CounterBlockTcAttr = 0x400,
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// Explicitly indexed blocks
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CounterBlockExplInstAttr = 0x800,
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// SPM blocks
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CounterBlockSpmGlobalAttr = 0x1000,
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CounterBlockSpmSeAttr = 0x2000,
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// GUS block
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CounterBlockGusAttr = 0x4000,
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// GRBM block
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CounterBlockGRBMAttr = 0x8000,
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// UMC block
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CounterBlockUmcAttr = 0x10000,
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// SE and SA-dependent blocks
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CounterBlockSaAttr = 0x20000,
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// MI300 AID blocks
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CounterBlockAidAttr = 0x40000,
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// SPI special
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CounterBlockSPIAttr = 0x80000,
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// Blocks within WGP
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CounterBlockWgpAttr = 0x100000,
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// RPB block
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CounterBlockRpbAttr = 0x200000,
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// ATC block
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CounterBlockAtcAttr = 0x400000,
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};
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// Register address corresponding to each counter
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struct CounterRegInfo {
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// counter select register address
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Register select_addr;
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// counter control register address
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Register control_addr;
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// counter register address low
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Register register_addr_lo;
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// counter register address high
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Register register_addr_hi;
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// counter select1 register address (for SPM)
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Register select1_addr;
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};
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struct BlockDelayInfo {
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Register reg;
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const uint32_t* val; // Layout: val[SA][SE][instance]
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};
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#define BLOCK_DELAY_NONE { REG_32B_NULL, nullptr }
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struct counter_des_t;
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// GPU Block info definition
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struct GpuBlockInfo {
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// Unique string identifier of the block.
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const char* name;
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// Block ID
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uint32_t id;
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// Maximum number of block instances in the group per shader array
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uint32_t instance_count;
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// Maximum counter event ID
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uint32_t event_id_max;
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// Maximum number of counters that can be enabled at once
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uint32_t counter_count;
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// Counter registers addresses
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const CounterRegInfo* counter_reg_info;
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// Counter select value function
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uint32_t (*select_value)(const counter_des_t&);
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// Block attributes mask
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uint32_t attr;
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// Block delay info
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BlockDelayInfo delay_info;
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// SPM block id
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uint32_t spm_block_id;
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};
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// Block descriptor
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struct block_des_t {
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uint32_t id;
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uint32_t index;
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};
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// block_des_t less then functor
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struct lt_block_des {
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bool operator()(const block_des_t& a1, const block_des_t& a2) const {
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return (a1.id < a2.id) || ((a1.id == a2.id) && (a1.index < a2.index));
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}
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};
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// Counter descriptor
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struct counter_des_t {
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uint32_t id;
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uint32_t index;
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block_des_t block_des;
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const GpuBlockInfo* block_info;
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};
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#endif // SRC_DEF_GPU_BLOCK_INFO_H_
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