German Andryeyev
d9397590de
The change reuses HSA signals for dispatches as a wait signal. Skipping the barrier requires to disable L2 cache for sysmem allocations and extra tracking for HDP access with the large bar. ROC_BARRIER_SYNC=0 activates the new logic. Barrier sync is still used by default. ROC_ACTIVE_WAIT=1 enables unconditional active wait in ROCr. The change also consolidated ROCr wait logic under single function. Change-Id: I6bd1be30aa88258da1b1f9de319ef5a45852afd8
108 sor
3.8 KiB
C++
108 sor
3.8 KiB
C++
/* Copyright (c) 2010-present Advanced Micro Devices, Inc.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE. */
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#pragma once
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#ifndef WITHOUT_HSA_BACKEND
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#include "library.hpp"
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/*! \addtogroup HSA OCL Stub Implementation
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* @{
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*/
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//! HSA OCL STUB Implementation
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namespace roc {
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//! Device settings
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class Settings : public device::Settings {
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public:
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enum Hmm : uint32_t {
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EnableSystemMemory = 0x01, //!< Forces system memory preference by default
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EnableMallocPrefetch = 0x02, //!< Skips default prefetch after allocation
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EnableSvmTracking = 0x04, //!< Enables SW SVM tracking
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EnableDebugSvm = 0x08 //!< Extra debug flag (reserved for runtime developers)
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};
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union {
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struct {
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uint doublePrecision_ : 1; //!< Enables double precision support
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uint enableLocalMemory_ : 1; //!< Enable GPUVM memory
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uint enableCoarseGrainSVM_ : 1; //!< Enable device memory for coarse grain SVM allocations
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uint enableNCMode_ : 1; //!< Enable Non Coherent mode for system memory
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uint imageDMA_ : 1; //!< Enable direct image DMA transfers
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uint stagedXferRead_ : 1; //!< Uses a staged buffer read
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uint stagedXferWrite_ : 1; //!< Uses a staged buffer write
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uint imageBufferWar_ : 1; //!< Image buffer workaround for Gfx10
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uint barrier_sync_ : 1; //!< Use AQL barrier command to sync with CPU
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uint reserved_ : 23;
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};
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uint value_;
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};
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//! Default max workgroup size for 1D
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int maxWorkGroupSize_;
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//! Preferred workgroup size
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uint preferredWorkGroupSize_;
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//! Default max workgroup sizes for 2D
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int maxWorkGroupSize2DX_;
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int maxWorkGroupSize2DY_;
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//! Default max workgroup sizes for 3D
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int maxWorkGroupSize3DX_;
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int maxWorkGroupSize3DY_;
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int maxWorkGroupSize3DZ_;
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uint kernargPoolSize_;
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uint numDeviceEvents_; //!< The number of device events
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uint numWaitEvents_; //!< The number of wait events for device enqueue
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size_t xferBufSize_; //!< Transfer buffer size for image copy optimization
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size_t stagedXferSize_; //!< Staged buffer size
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size_t pinnedXferSize_; //!< Pinned buffer size for transfer
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size_t pinnedMinXferSize_; //!< Minimal buffer size for pinned transfer
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size_t sdmaCopyThreshold_; //!< Use SDMA to copy above this size
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uint32_t hmmFlags_; //!< HMM functionality control flags
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//! Default constructor
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Settings();
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//! Creates settings
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bool create(bool fullProfile, int gfxipMajor, int gfxipMinor, bool coop_groups = false);
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private:
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//! Disable copy constructor
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Settings(const Settings&);
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//! Disable assignment
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Settings& operator=(const Settings&);
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//! Overrides current settings based on registry/environment
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void override();
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};
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/*@}*/} // namespace roc
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#endif /*WITHOUT_HSA_BACKEND*/
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