P4 to Git Change 1057571 by gandryey@gera-dev-w7 on 2014/07/21 18:35:02

ECR #304775 - Device enqueuing
	- Add L2 cache flush after the scheduler execution. Although CP has to work with L2 cache, it seems some functionality relies on direct memory access and without explicit L2 flush CP can pick old values in the template.

Affected files ...

... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuvirtual.cpp#324 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gslbe/src/rt/GSLContext.cpp#61 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gslbe/src/rt/GSLContext.h#35 edit


[ROCm/clr commit: 4599bd0d4a]

projects/clr/rocclr/runtime/device/gpu/gpuvirtual.cpp

@@ -87,7 +87,7 @@ VirtualGPU::MemoryDependency::validate(
 
     if (flushL1Cache) {
         // Flush cache
-        gpu.flushL1Cache();
+        gpu.flushCUCaches();
 
         // Clear memory dependency state
         const static bool All = true;
@@ -1724,8 +1724,6 @@ VirtualGPU::submitKernelInternalHSA(
     if (hsaKernel.dynamicParallelism()) {
         // Make sure exculsive access to the device queue
         amd::ScopedLock(defQueue->lock());
-        //! \todo Remove flush. We start parent earlier.
-        flushDMA(MainEngine);
 
         if (GPU_PRINT_CHILD_KERNEL != 0) {
             waitForEvent(&gpuEvent);
@@ -1819,6 +1817,8 @@ VirtualGPU::submitKernelInternalHSA(
             *gpuDefQueue->virtualQueue_,
             *gpuDefQueue->schedParams_, gpuDefQueue->schedParamIdx_,
             gpuDefQueue->vqHeader_->aql_slot_num);
+        const static bool FlushL2 = true;
+        gpuDefQueue->flushCUCaches(FlushL2);
 
         // Get the address of PM4 template and add write it to params
         //! @note DMA flush must not occur between patch and the scheduler
@@ -3290,7 +3290,7 @@ VirtualGPU::processMemObjectsHSA(
                     *reinterpret_cast<void* const*>(params + desc.offset_));
                 if (!svmMem) {
                     //!\todo Do we have to sync cache coherency or wait for SDMA?
-                    flushL1Cache();
+                    flushCUCaches();
                     break;
                 }
             }

projects/clr/rocclr/runtime/device/gpu/gslbe/src/rt/GSLContext.cpp

@@ -464,9 +464,9 @@ CALGSLContext::flushIOCaches() const
 }
 
 void
-CALGSLContext::flushL1Cache() const
+CALGSLContext::flushCUCaches(bool flushL2) const
 {
-    m_cs->FlushL1Cache();
+    m_cs->FlushCUCaches(flushL2);
 }
 
 gslProgramObject

projects/clr/rocclr/runtime/device/gpu/gslbe/src/rt/GSLContext.h

@@ -51,7 +51,7 @@ public:
     bool             isDone(GpuEvent* event);
     void             waitForEvent(GpuEvent* event);
     void             flushIOCaches() const;
-    void             flushL1Cache() const;
+    void             flushCUCaches(bool flushL2 = false) const;
     void             eventBegin(EngineType engId)
     {
         m_eventQueue[engId].begin();