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Update IsaRegistry for backend changes

Ver Código-Fonte 
Changes in the compiler are being made to add controls for XNACK and SRAM ECC
for all targets which can support these features. By default the conservatively
correct settings of XNACK on and SRAM ECC on will be used. This change is to
facilitate these backend updates.

Change-Id: I2fd6b6bc1d32937737e7f56d8e08c70fe781c745


[ROCm/ROCR-Runtime commit: 87202d4408]
Esse commit está contido em:
Austin Kerbow
2020-02-28 22:45:33 -08:00
pai 9319b029f2
commit 3e9e830351
1 arquivos alterados com 15 adições e 1 exclusões
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projects/rocr-runtime/runtime/hsa-runtime/core/runtime/isa.cpp
+15 -1
Ver Arquivo
@@ -207,20 +207,34 @@ const IsaRegistry::IsaMap IsaRegistry::GetSupportedIsas() {
ISAREG_ENTRY_GEN(7, 0, 0, false, false)
ISAREG_ENTRY_GEN(7, 0, 1, false, false)
ISAREG_ENTRY_GEN(7, 0, 2, false, false)
ISAREG_ENTRY_GEN(8, 0, 1, false, false)
ISAREG_ENTRY_GEN(8, 0, 1, true, false)
ISAREG_ENTRY_GEN(8, 0, 2, false, false)
ISAREG_ENTRY_GEN(8, 0, 2, true, false)
ISAREG_ENTRY_GEN(8, 0, 3, false, false)
ISAREG_ENTRY_GEN(8, 0, 3, true, false)
ISAREG_ENTRY_GEN(8, 1, 0, false, false)
ISAREG_ENTRY_GEN(8, 1, 0, true, false)
ISAREG_ENTRY_GEN(9, 0, 0, false, false)
ISAREG_ENTRY_GEN(9, 0, 0, true, false)
ISAREG_ENTRY_GEN(9, 0, 2, false, false)
ISAREG_ENTRY_GEN(9, 0, 2, true, false)
ISAREG_ENTRY_GEN(9, 0, 4, false, false)
ISAREG_ENTRY_GEN(9, 0, 4, true, false)
ISAREG_ENTRY_GEN(9, 0, 6, false, false)
ISAREG_ENTRY_GEN(9, 0, 6, true, false)
ISAREG_ENTRY_GEN(9, 0, 6, false, true )
ISAREG_ENTRY_GEN(9, 0, 8, false, true )
ISAREG_ENTRY_GEN(9, 0, 6, true, true )
ISAREG_ENTRY_GEN(9, 0, 8, false, false)
ISAREG_ENTRY_GEN(9, 0, 8, true, false)
ISAREG_ENTRY_GEN(9, 0, 8, false, true )
ISAREG_ENTRY_GEN(9, 0, 8, true, true )
ISAREG_ENTRY_GEN(10, 1, 0, false, false)
ISAREG_ENTRY_GEN(10, 1, 0, true, false)
ISAREG_ENTRY_GEN(10, 1, 1, false, false)
ISAREG_ENTRY_GEN(10, 1, 1, true, false)
ISAREG_ENTRY_GEN(10, 1, 2, false, false)
ISAREG_ENTRY_GEN(10, 1, 2, true, false)
return supported_isas;
}