Update addrLib to support gfx11
This library was taken from public MESA library: https://gitlab.freedesktop.org/mesa/mesa/-/tree/main/src/amd/addrlib with top commit: 2866ae32da0348caf71ad2d11c353321df626ff4 Removing macros.h as it is no longer used by addrlib Change-Id: I0fdabfe48b74c259b4d29d81beae89604bbc141a
Este cometimento está contido em:
David Yat Sin
cometido por
David Yat Sin
David Yat Sin
ascendente
c2a60a4d5d
cometimento
a742b7e830
@@ -1,28 +1,27 @@
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/*
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* Copyright © 2007-2019 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
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* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
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************************************************************************************************************************
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*
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* Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE
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*
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***********************************************************************************************************************/
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/**
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****************************************************************************************************
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@@ -33,6 +32,7 @@
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#ifndef __ADDR_INTERFACE_H__
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#define __ADDR_INTERFACE_H__
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// Includes should be before extern "C"
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#include "addrtypes.h"
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namespace rocr {
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@@ -174,6 +174,7 @@ typedef struct _ADDR_EQUATION
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///< stacked vertically prior to swizzling
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} ADDR_EQUATION;
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/**
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****************************************************************************************************
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* @brief Alloc system memory flags.
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@@ -305,8 +306,9 @@ typedef union _ADDR_CREATE_FLAGS
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UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment
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UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize
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UINT_32 forceDccAndTcCompat : 1; ///< Force enable DCC and TC compatibility
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UINT_32 nonPower2MemConfig : 1; ///< Physical video memory size is not power of 2
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UINT_32 reserved : 23; ///< Reserved bits for future use
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UINT_32 nonPower2MemConfig : 1; ///< Video memory bit width is not power of 2
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UINT_32 enableAltTiling : 1; ///< Enable alt tile mode
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UINT_32 reserved : 22; ///< Reserved bits for future use
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};
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UINT_32 value;
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@@ -404,6 +406,8 @@ ADDR_E_RETURNCODE ADDR_API AddrCreate(
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const ADDR_CREATE_INPUT* pAddrCreateIn,
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ADDR_CREATE_OUTPUT* pAddrCreateOut);
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/**
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****************************************************************************************************
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* AddrDestroy
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@@ -418,6 +422,8 @@ ADDR_E_RETURNCODE ADDR_API AddrCreate(
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ADDR_E_RETURNCODE ADDR_API AddrDestroy(
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ADDR_HANDLE hLib);
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// Surface functions
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////////////////////////////////////////////////////////////////////////////////////////////////////
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@@ -649,6 +655,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo(
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const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
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ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
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@@ -737,6 +745,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceAddrFromCoord(
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const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
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ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT
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@@ -918,6 +928,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeHtileInfo(
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const ADDR_COMPUTE_HTILE_INFO_INPUT* pIn,
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ADDR_COMPUTE_HTILE_INFO_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
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@@ -980,6 +992,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeHtileAddrFromCoord(
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const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
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ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT
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@@ -1040,6 +1054,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr(
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const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
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ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// C-mask functions
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////////////////////////////////////////////////////////////////////////////////////////////////////
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@@ -1127,6 +1143,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskInfo(
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const ADDR_COMPUTE_CMASK_INFO_INPUT* pIn,
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ADDR_COMPUTE_CMASK_INFO_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
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@@ -1187,6 +1205,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskAddrFromCoord(
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const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
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ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT
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@@ -1245,6 +1265,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr(
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const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
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ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut);
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// F-mask functions
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////////////////////////////////////////////////////////////////////////////////////////////////////
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@@ -1325,6 +1347,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskInfo(
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const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
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ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
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@@ -1401,6 +1425,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskAddrFromCoord(
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const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
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ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT
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@@ -1474,6 +1500,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr(
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const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
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ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut);
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// Element/utility functions
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////////////////////////////////////////////////////////////////////////////////////////////////////
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@@ -1562,6 +1590,7 @@ ADDR_E_RETURNCODE ADDR_API AddrExtractBankPipeSwizzle(
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const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn,
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ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT
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@@ -1619,6 +1648,8 @@ ADDR_E_RETURNCODE ADDR_API AddrCombineBankPipeSwizzle(
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const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT* pIn,
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ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR_COMPUTE_SLICESWIZZLE_INPUT
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@@ -1645,6 +1676,8 @@ typedef struct _ADDR_COMPUTE_SLICESWIZZLE_INPUT
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///< README: When tileIndex is not -1, this must be valid
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} ADDR_COMPUTE_SLICESWIZZLE_INPUT;
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/**
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****************************************************************************************************
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* ADDR_COMPUTE_SLICESWIZZLE_OUTPUT
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@@ -1675,6 +1708,7 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeSliceSwizzle(
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const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn,
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ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* AddrSwizzleGenOption
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@@ -1765,6 +1799,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeBaseSwizzle(
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const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn,
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ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ELEM_GETEXPORTNORM_INPUT
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@@ -1805,6 +1841,8 @@ BOOL_32 ADDR_API ElemGetExportNorm(
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ADDR_HANDLE hLib,
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const ELEM_GETEXPORTNORM_INPUT* pIn);
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/**
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****************************************************************************************************
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* ELEM_FLT32TODEPTHPIXEL_INPUT
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@@ -1860,6 +1898,8 @@ ADDR_E_RETURNCODE ADDR_API ElemFlt32ToDepthPixel(
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const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,
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ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ELEM_FLT32TOCOLORPIXEL_INPUT
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@@ -1986,6 +2026,8 @@ ADDR_E_RETURNCODE ADDR_API AddrConvertTileInfoToHW(
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const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
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ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR_CONVERT_TILEINDEX_INPUT
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@@ -2110,6 +2152,8 @@ ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex1(
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const ADDR_CONVERT_TILEINDEX1_INPUT* pIn,
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ADDR_CONVERT_TILEINDEX_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR_GET_TILEINDEX_INPUT
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@@ -2155,6 +2199,8 @@ ADDR_E_RETURNCODE ADDR_API AddrGetTileIndex(
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const ADDR_GET_TILEINDEX_INPUT* pIn,
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ADDR_GET_TILEINDEX_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR_PRT_INFO_INPUT
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@@ -2199,6 +2245,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo(
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const ADDR_PRT_INFO_INPUT* pIn,
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ADDR_PRT_INFO_OUTPUT* pOut);
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// DCC key functions
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////////////////////////////////////////////////////////////////////////////////////////////////////
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@@ -2259,6 +2307,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
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const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
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ADDR_COMPUTE_DCCINFO_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR_GET_MAX_ALIGNMENTS_OUTPUT
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@@ -2267,7 +2317,7 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
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* Output structure of AddrGetMaxAlignments
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****************************************************************************************************
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*/
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typedef struct _ADDR_GET_MAX_ALIGNMENTS_OUTPUT
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typedef struct ADDR_GET_MAX_ALINGMENTS_OUTPUT
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{
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UINT_32 size; ///< Size of this structure in bytes
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UINT_32 baseAlign; ///< Maximum base alignment in bytes
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@@ -2322,6 +2372,7 @@ ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
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*
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**/
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// Surface functions for Gfx9
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////////////////////////////////////////////////////////////////////////////////////////////////////
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@@ -2485,6 +2536,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceInfo(
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const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
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ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
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@@ -2551,6 +2604,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceAddrFromCoord(
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const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
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ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT
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@@ -2616,6 +2671,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceCoordFromAddr(
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const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
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ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut);
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// HTile functions for Gfx9
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////////////////////////////////////////////////////////////////////////////////////////////////////
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@@ -2664,6 +2721,7 @@ typedef struct _ADDR2_META_MIP_INFO
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UINT_32 depth;
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};
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// GFX10
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struct
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{
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UINT_32 offset; ///< Metadata offset within one slice,
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@@ -2696,6 +2754,7 @@ typedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT
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UINT_32 firstMipIdInTail; /// Id of the first mip in tail,
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/// if no mip is in tail, it should be set to
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/// number of mip levels
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/// Only for GFX10
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} ADDR2_COMPUTE_HTILE_INFO_INPUT;
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/**
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@@ -2722,6 +2781,10 @@ typedef struct _ADDR2_COMPUTE_HTILE_INFO_OUTPUT
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UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
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ADDR2_META_MIP_INFO* pMipInfo; ///< HTILE mip information
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struct {
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UINT_16* gfx10_bits; /* 72 2-byte elements */
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} equation;
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} ADDR2_COMPUTE_HTILE_INFO_OUTPUT;
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/**
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@@ -2737,6 +2800,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileInfo(
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const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
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ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
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@@ -2794,6 +2859,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileAddrFromCoord(
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const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
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ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT
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@@ -2852,6 +2919,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileCoordFromAddr(
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const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
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ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// C-mask functions for Gfx9
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////////////////////////////////////////////////////////////////////////////////////////////////////
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@@ -2878,8 +2947,23 @@ typedef struct _ADDR2_COMPUTE_CMASKINFO_INPUT
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UINT_32 numMipLevels; ///< Number of mip levels
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UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail,
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/// it should be number of mip levels
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/// Only for GFX10
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} ADDR2_COMPUTE_CMASK_INFO_INPUT;
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/* DCC addr meta equation for GFX9. */
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struct gfx9_addr_meta_equation {
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UINT_8 num_bits;
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struct {
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struct {
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UINT_8 dim; /* 0..4 as index, 5 means invalid */
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UINT_8 ord; /* 0..31 */
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} coord[8]; /* 0..num_coords */
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} bit[32]; /* 0..num_bits */
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UINT_8 numPipeBits;
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};
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/**
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****************************************************************************************************
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* ADDR2_COMPUTE_CMASK_INFO_OUTPUT
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@@ -2906,6 +2990,21 @@ typedef struct _ADDR2_COMPUTE_CMASK_INFO_OUTPUT
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UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
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ADDR2_META_MIP_INFO* pMipInfo; ///< CMASK mip information
|
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|
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/* The equation for doing CMASK address computations in shaders. */
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union {
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/* This is chip-specific, and it varies with:
|
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* - resource type
|
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* - swizzle_mode
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* - bpp
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* - pipe_aligned
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* - rb_aligned
|
||||
*/
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struct gfx9_addr_meta_equation gfx9;
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/* This is chip-specific, it requires 64KB_Z_X. */
|
||||
UINT_16 *gfx10_bits; /* 68 2-byte elements */
|
||||
} equation;
|
||||
} ADDR2_COMPUTE_CMASK_INFO_OUTPUT;
|
||||
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||||
/**
|
||||
@@ -2922,6 +3021,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskInfo(
|
||||
const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
|
||||
@@ -2983,6 +3084,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskAddrFromCoord(
|
||||
const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT
|
||||
@@ -3041,6 +3144,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskCoordFromAddr(
|
||||
const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
|
||||
ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut);
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// F-mask functions for Gfx9
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -3123,6 +3228,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskInfo(
|
||||
const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
|
||||
@@ -3182,6 +3289,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskAddrFromCoord(
|
||||
const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT
|
||||
@@ -3240,6 +3349,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskCoordFromAddr(
|
||||
const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
|
||||
ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut);
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// DCC key functions for Gfx9
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -3270,6 +3381,7 @@ typedef struct _ADDR2_COMPUTE_DCCINFO_INPUT
|
||||
///< useful in meta linear case
|
||||
UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail,
|
||||
/// it should be number of mip levels
|
||||
/// Only for GFX10
|
||||
} ADDR2_COMPUTE_DCCINFO_INPUT;
|
||||
|
||||
/**
|
||||
@@ -3298,7 +3410,7 @@ typedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT
|
||||
UINT_32 metaBlkWidth; ///< DCC meta block width
|
||||
UINT_32 metaBlkHeight; ///< DCC meta block height
|
||||
UINT_32 metaBlkDepth; ///< DCC meta block depth
|
||||
|
||||
UINT_32 metaBlkSize; ///< DCC meta block size in bytes
|
||||
UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
|
||||
|
||||
union
|
||||
@@ -3307,9 +3419,29 @@ typedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT
|
||||
UINT_32 dccRamSliceSize; ///< DCC ram size per slice. For mipmap, it's
|
||||
/// the slize size of a mip chain, the thickness of a
|
||||
/// a slice is meta block depth
|
||||
/// Only for GFX10
|
||||
};
|
||||
|
||||
ADDR2_META_MIP_INFO* pMipInfo; ///< DCC mip information
|
||||
|
||||
/* The equation for doing DCC address computations in shaders. */
|
||||
union {
|
||||
/* This is chip-specific, and it varies with:
|
||||
* - resource type
|
||||
* - swizzle_mode
|
||||
* - bpp
|
||||
* - number of fragments
|
||||
* - pipe_aligned
|
||||
* - rb_aligned
|
||||
*/
|
||||
struct gfx9_addr_meta_equation gfx9;
|
||||
|
||||
/* This is chip-specific, it requires 64KB_R_X, and it varies with:
|
||||
* - bpp
|
||||
* - pipe_aligned
|
||||
*/
|
||||
UINT_16 *gfx10_bits; /* 68 2-byte elements */
|
||||
} equation;
|
||||
} ADDR2_COMPUTE_DCCINFO_OUTPUT;
|
||||
|
||||
/**
|
||||
@@ -3326,6 +3458,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccInfo(
|
||||
const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut);
|
||||
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
|
||||
@@ -3346,9 +3479,12 @@ typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
|
||||
UINT_32 mipId; ///< mipmap level id
|
||||
|
||||
ADDR2_META_FLAGS dccKeyFlags; ///< DCC flags
|
||||
ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
|
||||
AddrResourceType resourceType; ///< Color surface type
|
||||
AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode
|
||||
UINT_32 bpp; ///< Color surface bits per pixel
|
||||
UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
|
||||
UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
|
||||
UINT_32 numSlices; ///< Color surface original slices (of mip0)
|
||||
UINT_32 numMipLevels; ///< Color surface mipmap levels
|
||||
UINT_32 numFrags; ///< Color surface fragment number
|
||||
@@ -3459,6 +3595,7 @@ typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT
|
||||
UINT_32 size; ///< Size of this structure in bytes
|
||||
AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
|
||||
AddrResourceType resourceType; ///< Surface resource type
|
||||
UINT_32 bpe; ///< bits per element (e.g. block size for BCn format)
|
||||
UINT_32 basePipeBankXor; ///< Base pipe bank xor
|
||||
UINT_32 slice; ///< Slice id
|
||||
UINT_32 numSamples; ///< Number of samples
|
||||
@@ -3538,6 +3675,62 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern(
|
||||
const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut);
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT
|
||||
*
|
||||
* @brief
|
||||
* Input structure of Addr2ComputeNonBlockCompressedView
|
||||
****************************************************************************************************
|
||||
*/
|
||||
typedef struct _ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT
|
||||
{
|
||||
UINT_32 size; ///< Size of this structure in bytes
|
||||
ADDR2_SURFACE_FLAGS flags; ///< Surface flags
|
||||
AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Gfx9
|
||||
AddrResourceType resourceType; ///< Surface type
|
||||
AddrFormat format; ///< Surface format
|
||||
UINT_32 width; ///< Width of mip0 in texels (not in compressed block)
|
||||
UINT_32 height; ///< Height of mip0 in texels (not in compressed block)
|
||||
UINT_32 numSlices; ///< Number surface slice/depth of mip0
|
||||
UINT_32 numMipLevels; ///< Total mipmap levels.
|
||||
UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation
|
||||
UINT_32 slice; ///< Index of slice to view
|
||||
UINT_32 mipId; ///< Id of mip to view
|
||||
} ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT;
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT
|
||||
*
|
||||
* @brief
|
||||
* Output structure of Addr2ComputeNonBlockCompressedView
|
||||
****************************************************************************************************
|
||||
*/
|
||||
typedef struct _ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT
|
||||
{
|
||||
UINT_32 size; ///< Size of this structure in bytes
|
||||
UINT_64 offset; ///< Offset shifted from resource base for the view
|
||||
UINT_32 pipeBankXor; ///< Pipe bank xor for the view
|
||||
UINT_32 unalignedWidth; ///< Mip0 width (in element) for the view
|
||||
UINT_32 unalignedHeight; ///< Mip0 height (in element) for the view
|
||||
UINT_32 numMipLevels; ///< Total mipmap levels for the view
|
||||
UINT_32 mipId; ///< Mip ID for the view
|
||||
} ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT;
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* Addr2ComputeNonBlockCompressedView
|
||||
*
|
||||
* @brief
|
||||
* Compute non-block-compressed view for a given mipmap level/slice
|
||||
****************************************************************************************************
|
||||
*/
|
||||
ADDR_E_RETURNCODE ADDR_API Addr2ComputeNonBlockCompressedView(
|
||||
ADDR_HANDLE hLib,
|
||||
const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn,
|
||||
ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut);
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* ADDR2_BLOCK_SET
|
||||
@@ -3556,10 +3749,19 @@ typedef union _ADDR2_BLOCK_SET
|
||||
UINT_32 macroThin64KB : 1; // Thin 64KB for 2D/3D resource
|
||||
UINT_32 macroThick64KB : 1; // Thick 64KB for 3D resource
|
||||
UINT_32 var : 1; // VAR block
|
||||
UINT_32 : 1;
|
||||
UINT_32 linear : 1; // Linear block
|
||||
UINT_32 reserved : 25;
|
||||
UINT_32 reserved : 24;
|
||||
};
|
||||
|
||||
struct
|
||||
{
|
||||
UINT_32 : 5;
|
||||
UINT_32 thin256KB : 1; // Thin 256KB block
|
||||
UINT_32 thick256KB : 1; // Thick 256KB block
|
||||
UINT_32 : 25;
|
||||
} gfx11;
|
||||
|
||||
UINT_32 value;
|
||||
} ADDR2_BLOCK_SET;
|
||||
|
||||
@@ -3609,10 +3811,10 @@ typedef union _ADDR2_SWMODE_SET
|
||||
UINT_32 sw64KB_S : 1;
|
||||
UINT_32 sw64KB_D : 1;
|
||||
UINT_32 sw64KB_R : 1;
|
||||
UINT_32 swReserved0 : 1;
|
||||
UINT_32 swReserved1 : 1;
|
||||
UINT_32 swReserved2 : 1;
|
||||
UINT_32 swReserved3 : 1;
|
||||
UINT_32 swMiscDef12 : 1;
|
||||
UINT_32 swMiscDef13 : 1;
|
||||
UINT_32 swMiscDef14 : 1;
|
||||
UINT_32 swMiscDef15 : 1;
|
||||
UINT_32 sw64KB_Z_T : 1;
|
||||
UINT_32 sw64KB_S_T : 1;
|
||||
UINT_32 sw64KB_D_T : 1;
|
||||
@@ -3625,12 +3827,29 @@ typedef union _ADDR2_SWMODE_SET
|
||||
UINT_32 sw64KB_S_X : 1;
|
||||
UINT_32 sw64KB_D_X : 1;
|
||||
UINT_32 sw64KB_R_X : 1;
|
||||
UINT_32 swVar_Z_X : 1;
|
||||
UINT_32 swReserved4 : 1;
|
||||
UINT_32 swReserved5 : 1;
|
||||
UINT_32 swVar_R_X : 1;
|
||||
UINT_32 swMiscDef28 : 1;
|
||||
UINT_32 swMiscDef29 : 1;
|
||||
UINT_32 swMiscDef30 : 1;
|
||||
UINT_32 swMiscDef31 : 1;
|
||||
};
|
||||
|
||||
struct
|
||||
{
|
||||
UINT_32 : 28;
|
||||
UINT_32 swVar_Z_X : 1;
|
||||
UINT_32 : 2;
|
||||
UINT_32 swVar_R_X : 1;
|
||||
} gfx10;
|
||||
|
||||
struct
|
||||
{
|
||||
UINT_32 : 28;
|
||||
UINT_32 sw256KB_Z_X : 1;
|
||||
UINT_32 sw256KB_S_X : 1;
|
||||
UINT_32 sw256KB_D_X : 1;
|
||||
UINT_32 sw256KB_R_X : 1;
|
||||
} gfx11;
|
||||
|
||||
UINT_32 value;
|
||||
} ADDR2_SWMODE_SET;
|
||||
|
||||
@@ -3666,6 +3885,8 @@ typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
|
||||
UINT_32 maxAlign; ///< maximum base/size alignment requested by client
|
||||
UINT_32 minSizeAlign; ///< memory allocated for surface in client driver will
|
||||
/// be padded to multiple of this value (in bytes)
|
||||
DOUBLE memoryBudget; ///< Memory consumption ratio based on minimum possible
|
||||
/// size.
|
||||
} ADDR2_GET_PREFERRED_SURF_SETTING_INPUT;
|
||||
|
||||
/**
|
||||
@@ -3708,14 +3929,14 @@ ADDR_E_RETURNCODE ADDR_API Addr2GetPreferredSurfaceSetting(
|
||||
* Addr2IsValidDisplaySwizzleMode
|
||||
*
|
||||
* @brief
|
||||
* Return whether the swizzle mode is supported by DCE / DCN.
|
||||
* Return whether the swizzle mode is supported by display engine
|
||||
****************************************************************************************************
|
||||
*/
|
||||
ADDR_E_RETURNCODE ADDR_API Addr2IsValidDisplaySwizzleMode(
|
||||
ADDR_HANDLE hLib,
|
||||
AddrSwizzleMode swizzleMode,
|
||||
UINT_32 bpp,
|
||||
bool *result);
|
||||
BOOL_32 *pResult);
|
||||
|
||||
} // rocr
|
||||
|
||||
|
||||
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