updating Pytest mark and tests/workloads

Signed-off-by: Jose Santos <josantos@login1.hpcfund>
2024-02-21 12:49:32 -06:00
parent 4f96837157
commit b018d9207f
116 changed files with 499 additions and 1 deletions
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,1329746,1329746,1048576,256,0,0,8,8,16,64,0x0,0x7ff36005ce80,49853,49853,16384,65536,13040,1680908,5862031958679664,5862046126501116,5862046126524956,5862031966293896
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,1329746,1329746,1048576,256,0,0,8,8,16,64,0x0,0x7ff36005ce80,113546,113546,16384,65536,8251,1048576,5862031966316188,5862046126616796,5862046126635516,5862031966678814
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,1329746,1329746,1048576,256,0,0,8,8,16,64,0x0,0x7ff36005ce80,47978,47978,16384,65536,8069,1048584,5862031966711406,5862046126657436,5862046126676476,5862031966894302
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,1328531,1328531,1048576,256,0,0,8,8,16,64,0x0,0x7f64b2038e80,0,0,0,5862026052994063,5862046126501116,5862046126524956,5862026060638081
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,1328531,1328531,1048576,256,0,0,8,8,16,64,0x0,0x7f64b2038e80,0,0,0,5862026060659161,5862046126616796,5862046126635516,5862026060957375
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,1328531,1328531,1048576,256,0,0,8,8,16,64,0x0,0x7f64b2038e80,0,0,0,5862026060985809,5862046126657436,5862046126676476,5862026061154438
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,1328329,1328329,1048576,256,0,0,8,8,16,64,0x0,0x7fdff6a24e80,65536,185356,23718656,5862025131935600,5862046126501116,5862046126524956,5862025140185344
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,1328329,1328329,1048576,256,0,0,8,8,16,64,0x0,0x7fdff6a24e80,65536,188418,24213280,5862025140195654,5862046126616796,5862046126635516,5862025140512263
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,1328329,1328329,1048576,256,0,0,8,8,16,64,0x0,0x7fdff6a24e80,65536,175286,22402288,5862025140540476,5862046126657436,5862046126676476,5862025140712692
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,1330557,1330557,1048576,256,0,0,8,8,16,64,0x0,0x7f6ef60aae80,32768,646195,82717292,5862035909155076,5862046126501116,5862046126524956,5862035917308328
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,1330557,1330557,1048576,256,0,0,8,8,16,64,0x0,0x7f6ef60aae80,32768,679196,86941576,5862035917329729,5862046126616796,5862046126635516,5862035917590542
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,1330557,1330557,1048576,256,0,0,8,8,16,64,0x0,0x7f6ef60aae80,32768,648200,82969328,5862035917619637,5862046126657436,5862046126676476,5862035917766324
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,1331365,1331365,1048576,256,0,0,8,8,16,64,0x0,0x7ff38955ee80,48726,48726,15960,389816,16384,25298259,237438,0,101737392,5862039834232768,5862046126501116,5862046126524956,5862039841771177
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,1331365,1331365,1048576,256,0,0,8,8,16,64,0x0,0x7ff38955ee80,42346,42346,13239,338776,16384,25180426,231129,0,101259708,5862039841799491,5862046126616796,5862046126635516,5862039842117172
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,1331365,1331365,1048576,256,0,0,8,8,16,64,0x0,0x7ff38955ee80,43098,43098,13945,344792,16384,25427869,236168,0,102246936,5862039842156836,5862046126657436,5862046126676476,5862039842351986
@@ -0,0 +1,5 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_WAVES SQ_IFETCH SQ_IFETCH_LEVEL  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_LDS SQ_INST_LEVEL_LDS  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_SMEM  SQ_INST_LEVEL_SMEM SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_VMEM  SQ_INST_LEVEL_VMEM SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE CPC_ME1_BUSY_FOR_PACKET_DECODE SQ_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_BUSY_CYCLES SQ_LEVEL_WAVES  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQC_TC_INST_REQ SQC_TC_DATA_READ_REQ SQC_TC_DATA_WRITE_REQ GRBM_COUNT GRBM_GUI_ACTIVE TCP_GATE_EN1_sum TCP_GATE_EN2_sum TCP_TD_TCP_STALL_CYCLES_sum TCP_TCR_TCP_STALL_CYCLES_sum TA_TA_BUSY_sum TA_BUFFER_WAVEFRONTS_sum TD_TD_BUSY_sum TD_TC_STALL_sum SPI_CSN_WINDOW_VALID SPI_CSN_BUSY CPC_CPC_STAT_BUSY CPC_CPC_STAT_IDLE CPF_CPF_STAT_BUSY CPF_CPF_STAT_STALL TCC_CYCLE_sum TCC_BUSY_sum TCC_PROBE_sum TCC_PROBE_ALL_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_TC_DATA_ATOMIC_REQ SQC_TC_STALL SQC_TC_REQ SQC_DCACHE_REQ_READ_16 SQC_ICACHE_REQ SQC_ICACHE_HITS SQC_ICACHE_MISSES SQC_ICACHE_MISSES_DUPLICATE GRBM_SPI_BUSY TCP_READ_TAGCONFLICT_STALL_CYCLES_sum TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum TCP_TA_TCP_STATE_READ_sum TA_BUFFER_READ_WAVEFRONTS_sum TA_BUFFER_WRITE_WAVEFRONTS_sum TD_COALESCABLE_WAVEFRONT_sum TD_LOAD_WAVEFRONT_sum SPI_CSN_NUM_THREADGROUPS SPI_CSN_WAVE CPC_CPC_TCIU_BUSY CPC_CPC_TCIU_IDLE CPF_CPF_TCIU_BUSY CPF_CPF_TCIU_STALL TCC_NC_REQ_sum TCC_UC_REQ_sum TCC_CC_REQ_sum TCC_RW_REQ_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_EA_ATOMIC_LEVEL_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_ATOMIC[0] TCC_CYCLE[0] TCC_EA_ATOMIC[0] TCC_EA_ATOMIC_LEVEL[0] TCC_ATOMIC[1] TCC_CYCLE[1] TCC_EA_ATOMIC[1] TCC_EA_ATOMIC_LEVEL[1] TCC_ATOMIC[2] TCC_CYCLE[2] TCC_EA_ATOMIC[2] TCC_EA_ATOMIC_LEVEL[2] TCC_ATOMIC[3] TCC_CYCLE[3] TCC_EA_ATOMIC[3] TCC_EA_ATOMIC_LEVEL[3] TCC_ATOMIC[4] TCC_CYCLE[4] TCC_EA_ATOMIC[4] TCC_EA_ATOMIC_LEVEL[4] TCC_ATOMIC[5] TCC_CYCLE[5] TCC_EA_ATOMIC[5] TCC_EA_ATOMIC_LEVEL[5] TCC_ATOMIC[6] TCC_CYCLE[6] TCC_EA_ATOMIC[6] TCC_EA_ATOMIC_LEVEL[6] TCC_ATOMIC[7] TCC_CYCLE[7] TCC_EA_ATOMIC[7] TCC_EA_ATOMIC_LEVEL[7] TCC_ATOMIC[8] TCC_CYCLE[8] TCC_EA_ATOMIC[8] TCC_EA_ATOMIC_LEVEL[8] TCC_ATOMIC[9] TCC_CYCLE[9] TCC_EA_ATOMIC[9] TCC_EA_ATOMIC_LEVEL[9] TCC_ATOMIC[10] TCC_CYCLE[10] TCC_EA_ATOMIC[10] TCC_EA_ATOMIC_LEVEL[10] TCC_ATOMIC[11] TCC_CYCLE[11] TCC_EA_ATOMIC[11] TCC_EA_ATOMIC_LEVEL[11] TCC_ATOMIC[12] TCC_CYCLE[12] TCC_EA_ATOMIC[12] TCC_EA_ATOMIC_LEVEL[12] TCC_ATOMIC[13] TCC_CYCLE[13] TCC_EA_ATOMIC[13] TCC_EA_ATOMIC_LEVEL[13] TCC_ATOMIC[14] TCC_CYCLE[14] TCC_EA_ATOMIC[14] TCC_EA_ATOMIC_LEVEL[14] TCC_ATOMIC[15] TCC_CYCLE[15] TCC_EA_ATOMIC[15] TCC_EA_ATOMIC_LEVEL[15] TCC_ATOMIC[16] TCC_CYCLE[16] TCC_EA_ATOMIC[16] TCC_EA_ATOMIC_LEVEL[16] TCC_ATOMIC[17] TCC_CYCLE[17] TCC_EA_ATOMIC[17] TCC_EA_ATOMIC_LEVEL[17] TCC_ATOMIC[18] TCC_CYCLE[18] TCC_EA_ATOMIC[18] TCC_EA_ATOMIC_LEVEL[18] TCC_ATOMIC[19] TCC_CYCLE[19] TCC_EA_ATOMIC[19] TCC_EA_ATOMIC_LEVEL[19] TCC_ATOMIC[20] TCC_CYCLE[20] TCC_EA_ATOMIC[20] TCC_EA_ATOMIC_LEVEL[20] TCC_ATOMIC[21] TCC_CYCLE[21] TCC_EA_ATOMIC[21] TCC_EA_ATOMIC_LEVEL[21] TCC_ATOMIC[22] TCC_CYCLE[22] TCC_EA_ATOMIC[22] TCC_EA_ATOMIC_LEVEL[22] TCC_ATOMIC[23] TCC_CYCLE[23] TCC_EA_ATOMIC[23] TCC_EA_ATOMIC_LEVEL[23] TCC_ATOMIC[24] TCC_CYCLE[24] TCC_EA_ATOMIC[24] TCC_EA_ATOMIC_LEVEL[24] TCC_ATOMIC[25] TCC_CYCLE[25] TCC_EA_ATOMIC[25] TCC_EA_ATOMIC_LEVEL[25] TCC_ATOMIC[26] TCC_CYCLE[26] TCC_EA_ATOMIC[26] TCC_EA_ATOMIC_LEVEL[26] TCC_ATOMIC[27] TCC_CYCLE[27] TCC_EA_ATOMIC[27] TCC_EA_ATOMIC_LEVEL[27] TCC_ATOMIC[28] TCC_CYCLE[28] TCC_EA_ATOMIC[28] TCC_EA_ATOMIC_LEVEL[28] TCC_ATOMIC[29] TCC_CYCLE[29] TCC_EA_ATOMIC[29] TCC_EA_ATOMIC_LEVEL[29] TCC_ATOMIC[30] TCC_CYCLE[30] TCC_EA_ATOMIC[30] TCC_EA_ATOMIC_LEVEL[30] TCC_ATOMIC[31] TCC_CYCLE[31] TCC_EA_ATOMIC[31] TCC_EA_ATOMIC_LEVEL[31]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_EA_RDREQ[0] TCC_EA_RDREQ_32B[0] TCC_EA_RDREQ_DRAM_CREDIT_STALL[0] TCC_EA_RDREQ_GMI_CREDIT_STALL[0] TCC_EA_RDREQ[1] TCC_EA_RDREQ_32B[1] TCC_EA_RDREQ_DRAM_CREDIT_STALL[1] TCC_EA_RDREQ_GMI_CREDIT_STALL[1] TCC_EA_RDREQ[2] TCC_EA_RDREQ_32B[2] TCC_EA_RDREQ_DRAM_CREDIT_STALL[2] TCC_EA_RDREQ_GMI_CREDIT_STALL[2] TCC_EA_RDREQ[3] TCC_EA_RDREQ_32B[3] TCC_EA_RDREQ_DRAM_CREDIT_STALL[3] TCC_EA_RDREQ_GMI_CREDIT_STALL[3] TCC_EA_RDREQ[4] TCC_EA_RDREQ_32B[4] TCC_EA_RDREQ_DRAM_CREDIT_STALL[4] TCC_EA_RDREQ_GMI_CREDIT_STALL[4] TCC_EA_RDREQ[5] TCC_EA_RDREQ_32B[5] TCC_EA_RDREQ_DRAM_CREDIT_STALL[5] TCC_EA_RDREQ_GMI_CREDIT_STALL[5] TCC_EA_RDREQ[6] TCC_EA_RDREQ_32B[6] TCC_EA_RDREQ_DRAM_CREDIT_STALL[6] TCC_EA_RDREQ_GMI_CREDIT_STALL[6] TCC_EA_RDREQ[7] TCC_EA_RDREQ_32B[7] TCC_EA_RDREQ_DRAM_CREDIT_STALL[7] TCC_EA_RDREQ_GMI_CREDIT_STALL[7] TCC_EA_RDREQ[8] TCC_EA_RDREQ_32B[8] TCC_EA_RDREQ_DRAM_CREDIT_STALL[8] TCC_EA_RDREQ_GMI_CREDIT_STALL[8] TCC_EA_RDREQ[9] TCC_EA_RDREQ_32B[9] TCC_EA_RDREQ_DRAM_CREDIT_STALL[9] TCC_EA_RDREQ_GMI_CREDIT_STALL[9] TCC_EA_RDREQ[10] TCC_EA_RDREQ_32B[10] TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] TCC_EA_RDREQ_GMI_CREDIT_STALL[10] TCC_EA_RDREQ[11] TCC_EA_RDREQ_32B[11] TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] TCC_EA_RDREQ_GMI_CREDIT_STALL[11] TCC_EA_RDREQ[12] TCC_EA_RDREQ_32B[12] TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] TCC_EA_RDREQ_GMI_CREDIT_STALL[12] TCC_EA_RDREQ[13] TCC_EA_RDREQ_32B[13] TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] TCC_EA_RDREQ_GMI_CREDIT_STALL[13] TCC_EA_RDREQ[14] TCC_EA_RDREQ_32B[14] TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] TCC_EA_RDREQ_GMI_CREDIT_STALL[14] TCC_EA_RDREQ[15] TCC_EA_RDREQ_32B[15] TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] TCC_EA_RDREQ_GMI_CREDIT_STALL[15] TCC_EA_RDREQ[16] TCC_EA_RDREQ_32B[16] TCC_EA_RDREQ_DRAM_CREDIT_STALL[16] TCC_EA_RDREQ_GMI_CREDIT_STALL[16] TCC_EA_RDREQ[17] TCC_EA_RDREQ_32B[17] TCC_EA_RDREQ_DRAM_CREDIT_STALL[17] TCC_EA_RDREQ_GMI_CREDIT_STALL[17] TCC_EA_RDREQ[18] TCC_EA_RDREQ_32B[18] TCC_EA_RDREQ_DRAM_CREDIT_STALL[18] TCC_EA_RDREQ_GMI_CREDIT_STALL[18] TCC_EA_RDREQ[19] TCC_EA_RDREQ_32B[19] TCC_EA_RDREQ_DRAM_CREDIT_STALL[19] TCC_EA_RDREQ_GMI_CREDIT_STALL[19] TCC_EA_RDREQ[20] TCC_EA_RDREQ_32B[20] TCC_EA_RDREQ_DRAM_CREDIT_STALL[20] TCC_EA_RDREQ_GMI_CREDIT_STALL[20] TCC_EA_RDREQ[21] TCC_EA_RDREQ_32B[21] TCC_EA_RDREQ_DRAM_CREDIT_STALL[21] TCC_EA_RDREQ_GMI_CREDIT_STALL[21] TCC_EA_RDREQ[22] TCC_EA_RDREQ_32B[22] TCC_EA_RDREQ_DRAM_CREDIT_STALL[22] TCC_EA_RDREQ_GMI_CREDIT_STALL[22] TCC_EA_RDREQ[23] TCC_EA_RDREQ_32B[23] TCC_EA_RDREQ_DRAM_CREDIT_STALL[23] TCC_EA_RDREQ_GMI_CREDIT_STALL[23] TCC_EA_RDREQ[24] TCC_EA_RDREQ_32B[24] TCC_EA_RDREQ_DRAM_CREDIT_STALL[24] TCC_EA_RDREQ_GMI_CREDIT_STALL[24] TCC_EA_RDREQ[25] TCC_EA_RDREQ_32B[25] TCC_EA_RDREQ_DRAM_CREDIT_STALL[25] TCC_EA_RDREQ_GMI_CREDIT_STALL[25] TCC_EA_RDREQ[26] TCC_EA_RDREQ_32B[26] TCC_EA_RDREQ_DRAM_CREDIT_STALL[26] TCC_EA_RDREQ_GMI_CREDIT_STALL[26] TCC_EA_RDREQ[27] TCC_EA_RDREQ_32B[27] TCC_EA_RDREQ_DRAM_CREDIT_STALL[27] TCC_EA_RDREQ_GMI_CREDIT_STALL[27] TCC_EA_RDREQ[28] TCC_EA_RDREQ_32B[28] TCC_EA_RDREQ_DRAM_CREDIT_STALL[28] TCC_EA_RDREQ_GMI_CREDIT_STALL[28] TCC_EA_RDREQ[29] TCC_EA_RDREQ_32B[29] TCC_EA_RDREQ_DRAM_CREDIT_STALL[29] TCC_EA_RDREQ_GMI_CREDIT_STALL[29] TCC_EA_RDREQ[30] TCC_EA_RDREQ_32B[30] TCC_EA_RDREQ_DRAM_CREDIT_STALL[30] TCC_EA_RDREQ_GMI_CREDIT_STALL[30] TCC_EA_RDREQ[31] TCC_EA_RDREQ_32B[31] TCC_EA_RDREQ_DRAM_CREDIT_STALL[31] TCC_EA_RDREQ_GMI_CREDIT_STALL[31]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_EA_RDREQ_IO_CREDIT_STALL[0] TCC_EA_RDREQ_LEVEL[0] TCC_EA_WRREQ[0] TCC_EA_WRREQ_64B[0] TCC_EA_RDREQ_IO_CREDIT_STALL[1] TCC_EA_RDREQ_LEVEL[1] TCC_EA_WRREQ[1] TCC_EA_WRREQ_64B[1] TCC_EA_RDREQ_IO_CREDIT_STALL[2] TCC_EA_RDREQ_LEVEL[2] TCC_EA_WRREQ[2] TCC_EA_WRREQ_64B[2] TCC_EA_RDREQ_IO_CREDIT_STALL[3] TCC_EA_RDREQ_LEVEL[3] TCC_EA_WRREQ[3] TCC_EA_WRREQ_64B[3] TCC_EA_RDREQ_IO_CREDIT_STALL[4] TCC_EA_RDREQ_LEVEL[4] TCC_EA_WRREQ[4] TCC_EA_WRREQ_64B[4] TCC_EA_RDREQ_IO_CREDIT_STALL[5] TCC_EA_RDREQ_LEVEL[5] TCC_EA_WRREQ[5] TCC_EA_WRREQ_64B[5] TCC_EA_RDREQ_IO_CREDIT_STALL[6] TCC_EA_RDREQ_LEVEL[6] TCC_EA_WRREQ[6] TCC_EA_WRREQ_64B[6] TCC_EA_RDREQ_IO_CREDIT_STALL[7] TCC_EA_RDREQ_LEVEL[7] TCC_EA_WRREQ[7] TCC_EA_WRREQ_64B[7] TCC_EA_RDREQ_IO_CREDIT_STALL[8] TCC_EA_RDREQ_LEVEL[8] TCC_EA_WRREQ[8] TCC_EA_WRREQ_64B[8] TCC_EA_RDREQ_IO_CREDIT_STALL[9] TCC_EA_RDREQ_LEVEL[9] TCC_EA_WRREQ[9] TCC_EA_WRREQ_64B[9] TCC_EA_RDREQ_IO_CREDIT_STALL[10] TCC_EA_RDREQ_LEVEL[10] TCC_EA_WRREQ[10] TCC_EA_WRREQ_64B[10] TCC_EA_RDREQ_IO_CREDIT_STALL[11] TCC_EA_RDREQ_LEVEL[11] TCC_EA_WRREQ[11] TCC_EA_WRREQ_64B[11] TCC_EA_RDREQ_IO_CREDIT_STALL[12] TCC_EA_RDREQ_LEVEL[12] TCC_EA_WRREQ[12] TCC_EA_WRREQ_64B[12] TCC_EA_RDREQ_IO_CREDIT_STALL[13] TCC_EA_RDREQ_LEVEL[13] TCC_EA_WRREQ[13] TCC_EA_WRREQ_64B[13] TCC_EA_RDREQ_IO_CREDIT_STALL[14] TCC_EA_RDREQ_LEVEL[14] TCC_EA_WRREQ[14] TCC_EA_WRREQ_64B[14] TCC_EA_RDREQ_IO_CREDIT_STALL[15] TCC_EA_RDREQ_LEVEL[15] TCC_EA_WRREQ[15] TCC_EA_WRREQ_64B[15] TCC_EA_RDREQ_IO_CREDIT_STALL[16] TCC_EA_RDREQ_LEVEL[16] TCC_EA_WRREQ[16] TCC_EA_WRREQ_64B[16] TCC_EA_RDREQ_IO_CREDIT_STALL[17] TCC_EA_RDREQ_LEVEL[17] TCC_EA_WRREQ[17] TCC_EA_WRREQ_64B[17] TCC_EA_RDREQ_IO_CREDIT_STALL[18] TCC_EA_RDREQ_LEVEL[18] TCC_EA_WRREQ[18] TCC_EA_WRREQ_64B[18] TCC_EA_RDREQ_IO_CREDIT_STALL[19] TCC_EA_RDREQ_LEVEL[19] TCC_EA_WRREQ[19] TCC_EA_WRREQ_64B[19] TCC_EA_RDREQ_IO_CREDIT_STALL[20] TCC_EA_RDREQ_LEVEL[20] TCC_EA_WRREQ[20] TCC_EA_WRREQ_64B[20] TCC_EA_RDREQ_IO_CREDIT_STALL[21] TCC_EA_RDREQ_LEVEL[21] TCC_EA_WRREQ[21] TCC_EA_WRREQ_64B[21] TCC_EA_RDREQ_IO_CREDIT_STALL[22] TCC_EA_RDREQ_LEVEL[22] TCC_EA_WRREQ[22] TCC_EA_WRREQ_64B[22] TCC_EA_RDREQ_IO_CREDIT_STALL[23] TCC_EA_RDREQ_LEVEL[23] TCC_EA_WRREQ[23] TCC_EA_WRREQ_64B[23] TCC_EA_RDREQ_IO_CREDIT_STALL[24] TCC_EA_RDREQ_LEVEL[24] TCC_EA_WRREQ[24] TCC_EA_WRREQ_64B[24] TCC_EA_RDREQ_IO_CREDIT_STALL[25] TCC_EA_RDREQ_LEVEL[25] TCC_EA_WRREQ[25] TCC_EA_WRREQ_64B[25] TCC_EA_RDREQ_IO_CREDIT_STALL[26] TCC_EA_RDREQ_LEVEL[26] TCC_EA_WRREQ[26] TCC_EA_WRREQ_64B[26] TCC_EA_RDREQ_IO_CREDIT_STALL[27] TCC_EA_RDREQ_LEVEL[27] TCC_EA_WRREQ[27] TCC_EA_WRREQ_64B[27] TCC_EA_RDREQ_IO_CREDIT_STALL[28] TCC_EA_RDREQ_LEVEL[28] TCC_EA_WRREQ[28] TCC_EA_WRREQ_64B[28] TCC_EA_RDREQ_IO_CREDIT_STALL[29] TCC_EA_RDREQ_LEVEL[29] TCC_EA_WRREQ[29] TCC_EA_WRREQ_64B[29] TCC_EA_RDREQ_IO_CREDIT_STALL[30] TCC_EA_RDREQ_LEVEL[30] TCC_EA_WRREQ[30] TCC_EA_WRREQ_64B[30] TCC_EA_RDREQ_IO_CREDIT_STALL[31] TCC_EA_RDREQ_LEVEL[31] TCC_EA_WRREQ[31] TCC_EA_WRREQ_64B[31]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_EA_WRREQ_DRAM_CREDIT_STALL[0] TCC_EA_WRREQ_GMI_CREDIT_STALL[0] TCC_EA_WRREQ_IO_CREDIT_STALL[0] TCC_EA_WRREQ_LEVEL[0] TCC_EA_WRREQ_DRAM_CREDIT_STALL[1] TCC_EA_WRREQ_GMI_CREDIT_STALL[1] TCC_EA_WRREQ_IO_CREDIT_STALL[1] TCC_EA_WRREQ_LEVEL[1] TCC_EA_WRREQ_DRAM_CREDIT_STALL[2] TCC_EA_WRREQ_GMI_CREDIT_STALL[2] TCC_EA_WRREQ_IO_CREDIT_STALL[2] TCC_EA_WRREQ_LEVEL[2] TCC_EA_WRREQ_DRAM_CREDIT_STALL[3] TCC_EA_WRREQ_GMI_CREDIT_STALL[3] TCC_EA_WRREQ_IO_CREDIT_STALL[3] TCC_EA_WRREQ_LEVEL[3] TCC_EA_WRREQ_DRAM_CREDIT_STALL[4] TCC_EA_WRREQ_GMI_CREDIT_STALL[4] TCC_EA_WRREQ_IO_CREDIT_STALL[4] TCC_EA_WRREQ_LEVEL[4] TCC_EA_WRREQ_DRAM_CREDIT_STALL[5] TCC_EA_WRREQ_GMI_CREDIT_STALL[5] TCC_EA_WRREQ_IO_CREDIT_STALL[5] TCC_EA_WRREQ_LEVEL[5] TCC_EA_WRREQ_DRAM_CREDIT_STALL[6] TCC_EA_WRREQ_GMI_CREDIT_STALL[6] TCC_EA_WRREQ_IO_CREDIT_STALL[6] TCC_EA_WRREQ_LEVEL[6] TCC_EA_WRREQ_DRAM_CREDIT_STALL[7] TCC_EA_WRREQ_GMI_CREDIT_STALL[7] TCC_EA_WRREQ_IO_CREDIT_STALL[7] TCC_EA_WRREQ_LEVEL[7] TCC_EA_WRREQ_DRAM_CREDIT_STALL[8] TCC_EA_WRREQ_GMI_CREDIT_STALL[8] TCC_EA_WRREQ_IO_CREDIT_STALL[8] TCC_EA_WRREQ_LEVEL[8] TCC_EA_WRREQ_DRAM_CREDIT_STALL[9] TCC_EA_WRREQ_GMI_CREDIT_STALL[9] TCC_EA_WRREQ_IO_CREDIT_STALL[9] TCC_EA_WRREQ_LEVEL[9] TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] TCC_EA_WRREQ_GMI_CREDIT_STALL[10] TCC_EA_WRREQ_IO_CREDIT_STALL[10] TCC_EA_WRREQ_LEVEL[10] TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] TCC_EA_WRREQ_GMI_CREDIT_STALL[11] TCC_EA_WRREQ_IO_CREDIT_STALL[11] TCC_EA_WRREQ_LEVEL[11] TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] TCC_EA_WRREQ_GMI_CREDIT_STALL[12] TCC_EA_WRREQ_IO_CREDIT_STALL[12] TCC_EA_WRREQ_LEVEL[12] TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] TCC_EA_WRREQ_GMI_CREDIT_STALL[13] TCC_EA_WRREQ_IO_CREDIT_STALL[13] TCC_EA_WRREQ_LEVEL[13] TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] TCC_EA_WRREQ_GMI_CREDIT_STALL[14] TCC_EA_WRREQ_IO_CREDIT_STALL[14] TCC_EA_WRREQ_LEVEL[14] TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] TCC_EA_WRREQ_GMI_CREDIT_STALL[15] TCC_EA_WRREQ_IO_CREDIT_STALL[15] TCC_EA_WRREQ_LEVEL[15] TCC_EA_WRREQ_DRAM_CREDIT_STALL[16] TCC_EA_WRREQ_GMI_CREDIT_STALL[16] TCC_EA_WRREQ_IO_CREDIT_STALL[16] TCC_EA_WRREQ_LEVEL[16] TCC_EA_WRREQ_DRAM_CREDIT_STALL[17] TCC_EA_WRREQ_GMI_CREDIT_STALL[17] TCC_EA_WRREQ_IO_CREDIT_STALL[17] TCC_EA_WRREQ_LEVEL[17] TCC_EA_WRREQ_DRAM_CREDIT_STALL[18] TCC_EA_WRREQ_GMI_CREDIT_STALL[18] TCC_EA_WRREQ_IO_CREDIT_STALL[18] TCC_EA_WRREQ_LEVEL[18] TCC_EA_WRREQ_DRAM_CREDIT_STALL[19] TCC_EA_WRREQ_GMI_CREDIT_STALL[19] TCC_EA_WRREQ_IO_CREDIT_STALL[19] TCC_EA_WRREQ_LEVEL[19] TCC_EA_WRREQ_DRAM_CREDIT_STALL[20] TCC_EA_WRREQ_GMI_CREDIT_STALL[20] TCC_EA_WRREQ_IO_CREDIT_STALL[20] TCC_EA_WRREQ_LEVEL[20] TCC_EA_WRREQ_DRAM_CREDIT_STALL[21] TCC_EA_WRREQ_GMI_CREDIT_STALL[21] TCC_EA_WRREQ_IO_CREDIT_STALL[21] TCC_EA_WRREQ_LEVEL[21] TCC_EA_WRREQ_DRAM_CREDIT_STALL[22] TCC_EA_WRREQ_GMI_CREDIT_STALL[22] TCC_EA_WRREQ_IO_CREDIT_STALL[22] TCC_EA_WRREQ_LEVEL[22] TCC_EA_WRREQ_DRAM_CREDIT_STALL[23] TCC_EA_WRREQ_GMI_CREDIT_STALL[23] TCC_EA_WRREQ_IO_CREDIT_STALL[23] TCC_EA_WRREQ_LEVEL[23] TCC_EA_WRREQ_DRAM_CREDIT_STALL[24] TCC_EA_WRREQ_GMI_CREDIT_STALL[24] TCC_EA_WRREQ_IO_CREDIT_STALL[24] TCC_EA_WRREQ_LEVEL[24] TCC_EA_WRREQ_DRAM_CREDIT_STALL[25] TCC_EA_WRREQ_GMI_CREDIT_STALL[25] TCC_EA_WRREQ_IO_CREDIT_STALL[25] TCC_EA_WRREQ_LEVEL[25] TCC_EA_WRREQ_DRAM_CREDIT_STALL[26] TCC_EA_WRREQ_GMI_CREDIT_STALL[26] TCC_EA_WRREQ_IO_CREDIT_STALL[26] TCC_EA_WRREQ_LEVEL[26] TCC_EA_WRREQ_DRAM_CREDIT_STALL[27] TCC_EA_WRREQ_GMI_CREDIT_STALL[27] TCC_EA_WRREQ_IO_CREDIT_STALL[27] TCC_EA_WRREQ_LEVEL[27] TCC_EA_WRREQ_DRAM_CREDIT_STALL[28] TCC_EA_WRREQ_GMI_CREDIT_STALL[28] TCC_EA_WRREQ_IO_CREDIT_STALL[28] TCC_EA_WRREQ_LEVEL[28] TCC_EA_WRREQ_DRAM_CREDIT_STALL[29] TCC_EA_WRREQ_GMI_CREDIT_STALL[29] TCC_EA_WRREQ_IO_CREDIT_STALL[29] TCC_EA_WRREQ_LEVEL[29] TCC_EA_WRREQ_DRAM_CREDIT_STALL[30] TCC_EA_WRREQ_GMI_CREDIT_STALL[30] TCC_EA_WRREQ_IO_CREDIT_STALL[30] TCC_EA_WRREQ_LEVEL[30] TCC_EA_WRREQ_DRAM_CREDIT_STALL[31] TCC_EA_WRREQ_GMI_CREDIT_STALL[31] TCC_EA_WRREQ_IO_CREDIT_STALL[31] TCC_EA_WRREQ_LEVEL[31]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_HIT[0] TCC_MISS[0] TCC_READ[0] TCC_REQ[0] TCC_HIT[1] TCC_MISS[1] TCC_READ[1] TCC_REQ[1] TCC_HIT[2] TCC_MISS[2] TCC_READ[2] TCC_REQ[2] TCC_HIT[3] TCC_MISS[3] TCC_READ[3] TCC_REQ[3] TCC_HIT[4] TCC_MISS[4] TCC_READ[4] TCC_REQ[4] TCC_HIT[5] TCC_MISS[5] TCC_READ[5] TCC_REQ[5] TCC_HIT[6] TCC_MISS[6] TCC_READ[6] TCC_REQ[6] TCC_HIT[7] TCC_MISS[7] TCC_READ[7] TCC_REQ[7] TCC_HIT[8] TCC_MISS[8] TCC_READ[8] TCC_REQ[8] TCC_HIT[9] TCC_MISS[9] TCC_READ[9] TCC_REQ[9] TCC_HIT[10] TCC_MISS[10] TCC_READ[10] TCC_REQ[10] TCC_HIT[11] TCC_MISS[11] TCC_READ[11] TCC_REQ[11] TCC_HIT[12] TCC_MISS[12] TCC_READ[12] TCC_REQ[12] TCC_HIT[13] TCC_MISS[13] TCC_READ[13] TCC_REQ[13] TCC_HIT[14] TCC_MISS[14] TCC_READ[14] TCC_REQ[14] TCC_HIT[15] TCC_MISS[15] TCC_READ[15] TCC_REQ[15] TCC_HIT[16] TCC_MISS[16] TCC_READ[16] TCC_REQ[16] TCC_HIT[17] TCC_MISS[17] TCC_READ[17] TCC_REQ[17] TCC_HIT[18] TCC_MISS[18] TCC_READ[18] TCC_REQ[18] TCC_HIT[19] TCC_MISS[19] TCC_READ[19] TCC_REQ[19] TCC_HIT[20] TCC_MISS[20] TCC_READ[20] TCC_REQ[20] TCC_HIT[21] TCC_MISS[21] TCC_READ[21] TCC_REQ[21] TCC_HIT[22] TCC_MISS[22] TCC_READ[22] TCC_REQ[22] TCC_HIT[23] TCC_MISS[23] TCC_READ[23] TCC_REQ[23] TCC_HIT[24] TCC_MISS[24] TCC_READ[24] TCC_REQ[24] TCC_HIT[25] TCC_MISS[25] TCC_READ[25] TCC_REQ[25] TCC_HIT[26] TCC_MISS[26] TCC_READ[26] TCC_REQ[26] TCC_HIT[27] TCC_MISS[27] TCC_READ[27] TCC_REQ[27] TCC_HIT[28] TCC_MISS[28] TCC_READ[28] TCC_REQ[28] TCC_HIT[29] TCC_MISS[29] TCC_READ[29] TCC_REQ[29] TCC_HIT[30] TCC_MISS[30] TCC_READ[30] TCC_REQ[30] TCC_HIT[31] TCC_MISS[31] TCC_READ[31] TCC_REQ[31]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_RW_REQ[0] TCC_TOO_MANY_EA_WRREQS_STALL[0] TCC_WRITE[0] TCC_RW_REQ[1] TCC_TOO_MANY_EA_WRREQS_STALL[1] TCC_WRITE[1] TCC_RW_REQ[2] TCC_TOO_MANY_EA_WRREQS_STALL[2] TCC_WRITE[2] TCC_RW_REQ[3] TCC_TOO_MANY_EA_WRREQS_STALL[3] TCC_WRITE[3] TCC_RW_REQ[4] TCC_TOO_MANY_EA_WRREQS_STALL[4] TCC_WRITE[4] TCC_RW_REQ[5] TCC_TOO_MANY_EA_WRREQS_STALL[5] TCC_WRITE[5] TCC_RW_REQ[6] TCC_TOO_MANY_EA_WRREQS_STALL[6] TCC_WRITE[6] TCC_RW_REQ[7] TCC_TOO_MANY_EA_WRREQS_STALL[7] TCC_WRITE[7] TCC_RW_REQ[8] TCC_TOO_MANY_EA_WRREQS_STALL[8] TCC_WRITE[8] TCC_RW_REQ[9] TCC_TOO_MANY_EA_WRREQS_STALL[9] TCC_WRITE[9] TCC_RW_REQ[10] TCC_TOO_MANY_EA_WRREQS_STALL[10] TCC_WRITE[10] TCC_RW_REQ[11] TCC_TOO_MANY_EA_WRREQS_STALL[11] TCC_WRITE[11] TCC_RW_REQ[12] TCC_TOO_MANY_EA_WRREQS_STALL[12] TCC_WRITE[12] TCC_RW_REQ[13] TCC_TOO_MANY_EA_WRREQS_STALL[13] TCC_WRITE[13] TCC_RW_REQ[14] TCC_TOO_MANY_EA_WRREQS_STALL[14] TCC_WRITE[14] TCC_RW_REQ[15] TCC_TOO_MANY_EA_WRREQS_STALL[15] TCC_WRITE[15] TCC_RW_REQ[16] TCC_TOO_MANY_EA_WRREQS_STALL[16] TCC_WRITE[16] TCC_RW_REQ[17] TCC_TOO_MANY_EA_WRREQS_STALL[17] TCC_WRITE[17] TCC_RW_REQ[18] TCC_TOO_MANY_EA_WRREQS_STALL[18] TCC_WRITE[18] TCC_RW_REQ[19] TCC_TOO_MANY_EA_WRREQS_STALL[19] TCC_WRITE[19] TCC_RW_REQ[20] TCC_TOO_MANY_EA_WRREQS_STALL[20] TCC_WRITE[20] TCC_RW_REQ[21] TCC_TOO_MANY_EA_WRREQS_STALL[21] TCC_WRITE[21] TCC_RW_REQ[22] TCC_TOO_MANY_EA_WRREQS_STALL[22] TCC_WRITE[22] TCC_RW_REQ[23] TCC_TOO_MANY_EA_WRREQS_STALL[23] TCC_WRITE[23] TCC_RW_REQ[24] TCC_TOO_MANY_EA_WRREQS_STALL[24] TCC_WRITE[24] TCC_RW_REQ[25] TCC_TOO_MANY_EA_WRREQS_STALL[25] TCC_WRITE[25] TCC_RW_REQ[26] TCC_TOO_MANY_EA_WRREQS_STALL[26] TCC_WRITE[26] TCC_RW_REQ[27] TCC_TOO_MANY_EA_WRREQS_STALL[27] TCC_WRITE[27] TCC_RW_REQ[28] TCC_TOO_MANY_EA_WRREQS_STALL[28] TCC_WRITE[28] TCC_RW_REQ[29] TCC_TOO_MANY_EA_WRREQS_STALL[29] TCC_WRITE[29] TCC_RW_REQ[30] TCC_TOO_MANY_EA_WRREQS_STALL[30] TCC_WRITE[30] TCC_RW_REQ[31] TCC_TOO_MANY_EA_WRREQS_STALL[31] TCC_WRITE[31]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_DCACHE_INPUT_VALID_READYB SQC_DCACHE_ATOMIC SQC_DCACHE_REQ_READ_8 SQC_DCACHE_REQ SQC_DCACHE_HITS SQC_DCACHE_MISSES SQC_DCACHE_MISSES_DUPLICATE SQC_DCACHE_REQ_READ_1 TCP_VOLATILE_sum TCP_TOTAL_ACCESSES_sum TCP_TOTAL_READ_sum TCP_TOTAL_WRITE_sum TA_BUFFER_ATOMIC_WAVEFRONTS_sum TA_BUFFER_TOTAL_CYCLES_sum TD_ATOMIC_WAVEFRONT_sum TD_STORE_WAVEFRONT_sum SPI_RA_REQ_NO_ALLOC SPI_RA_REQ_NO_ALLOC_CSN CPC_CPC_STAT_STALL CPC_UTCL1_STALL_ON_TRANSLATION CPF_CPF_STAT_IDLE CPF_CPF_TCIU_IDLE TCC_REQ_sum TCC_STREAMING_REQ_sum TCC_HIT_sum TCC_MISS_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_DCACHE_REQ_READ_2 SQC_DCACHE_REQ_READ_4 SQ_INSTS_VMEM_WR SQ_INSTS_VMEM_RD SQ_INSTS_VMEM SQ_INSTS_SALU SQ_INSTS_VSKIPPED SQ_INSTS_SMEM TCP_TOTAL_ATOMIC_WITH_RET_sum TCP_TOTAL_ATOMIC_WITHOUT_RET_sum TCP_TOTAL_WRITEBACK_INVALIDATES_sum TCP_TOTAL_CACHE_ACCESSES_sum TA_BUFFER_COALESCED_READ_CYCLES_sum TA_BUFFER_COALESCED_WRITE_CYCLES_sum SPI_RA_RES_STALL_CSN SPI_RA_TMP_STALL_CSN CPC_CPC_UTCL2IU_BUSY CPC_CPC_UTCL2IU_IDLE CPF_CMP_UTCL1_STALL_ON_TRANSLATION TCC_READ_sum TCC_WRITE_sum TCC_ATOMIC_sum TCC_WRITEBACK_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_FLAT SQ_INSTS_LDS SQ_INSTS_GDS SQ_INSTS_EXP_GDS SQ_INSTS_BRANCH SQ_INSTS_SENDMSG SQ_INSTS SQ_WAIT_ANY TCP_UTCL1_TRANSLATION_MISS_sum TCP_UTCL1_TRANSLATION_HIT_sum TCP_UTCL1_PERMISSION_MISS_sum TCP_UTCL1_REQUEST_sum TA_ADDR_STALLED_BY_TC_CYCLES_sum TA_TOTAL_WAVEFRONTS_sum SPI_RA_WAVE_SIMD_FULL_CSN SPI_RA_VGPR_SIMD_FULL_CSN CPC_CPC_UTCL2IU_STALL CPC_ME1_BUSY_FOR_PACKET_DECODE TCC_EA_WRREQ_sum TCC_EA_WRREQ_64B_sum TCC_EA_WR_UNCACHED_32B_sum TCC_EA_WRREQ_DRAM_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_WAIT_INST_ANY SQ_ACTIVE_INST_ANY SQ_INSTS_VALU SQ_ACTIVE_INST_VMEM SQ_ACTIVE_INST_LDS SQ_ACTIVE_INST_VALU SQ_ACTIVE_INST_SCA SQ_ACTIVE_INST_EXP_GDS TCP_TCP_LATENCY_sum TCP_TCC_READ_REQ_LATENCY_sum TCP_TCC_WRITE_REQ_LATENCY_sum TCP_TCC_READ_REQ_sum TA_ADDR_STALLED_BY_TD_CYCLES_sum TA_DATA_STALLED_BY_TC_CYCLES_sum SPI_RA_SGPR_SIMD_FULL_CSN SPI_RA_LDS_CU_FULL_CSN CPC_ME1_DC0_SPI_BUSY TCC_EA_WRREQ_STALL_sum TCC_EA_WRREQ_IO_CREDIT_STALL_sum TCC_EA_WRREQ_GMI_CREDIT_STALL_sum TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_ACTIVE_INST_MISC SQ_ACTIVE_INST_FLAT SQ_INST_CYCLES_VMEM_WR SQ_INST_CYCLES_VMEM_RD SQ_INST_CYCLES_SMEM SQ_INST_CYCLES_SALU SQ_THREAD_CYCLES_VALU SQ_IFETCH TCP_TCC_WRITE_REQ_sum TCP_TCC_ATOMIC_WITH_RET_REQ_sum TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum TCP_TCC_NC_READ_REQ_sum TA_FLAT_WAVEFRONTS_sum TA_FLAT_READ_WAVEFRONTS_sum SPI_RA_BAR_CU_FULL_CSN SPI_RA_TGLIM_CU_FULL_CSN TCC_EA_RDREQ_sum TCC_EA_RDREQ_32B_sum TCC_EA_RD_UNCACHED_32B_sum TCC_EA_RDREQ_DRAM_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_LDS_BANK_CONFLICT SQ_LDS_ADDR_CONFLICT SQ_LDS_UNALIGNED_STALL SQ_WAVES_EQ_64 SQ_WAVES_LT_64 SQ_WAVES_LT_48 SQ_WAVES_LT_32 SQ_WAVES_LT_16 TCP_TCC_NC_WRITE_REQ_sum TCP_TCC_NC_ATOMIC_REQ_sum TCP_TCC_UC_READ_REQ_sum TCP_TCC_UC_WRITE_REQ_sum TA_FLAT_WRITE_WAVEFRONTS_sum TA_FLAT_ATOMIC_WAVEFRONTS_sum SPI_RA_WVLIM_STALL_CSN SPI_SWC_CSC_WR TCC_EA_RDREQ_IO_CREDIT_STALL_sum TCC_EA_RDREQ_GMI_CREDIT_STALL_sum TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum TCC_TAG_STALL_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_ITEMS SQ_LDS_MEM_VIOLATIONS SQ_LDS_ATOMIC_RETURN SQ_LDS_IDX_ACTIVE SQ_WAVES_RESTORED SQ_WAVES_SAVED SQ_INSTS_SMEM_NORM TCP_TCC_UC_ATOMIC_REQ_sum TCP_TCC_CC_READ_REQ_sum TCP_TCC_CC_WRITE_REQ_sum TCP_TCC_CC_ATOMIC_REQ_sum SPI_VWC_CSC_WR SPI_RA_BULKY_CU_FULL_CSN TCC_NORMAL_WRITEBACK_sum TCC_ALL_TC_OP_WB_WRITEBACK_sum TCC_NORMAL_EVICT_sum TCC_ALL_TC_OP_INV_EVICT_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCP_TCC_RW_READ_REQ_sum TCP_TCC_RW_WRITE_REQ_sum TCP_TCC_RW_ATOMIC_REQ_sum TCP_PENDING_STALL_CYCLES_sum TCC_TOO_MANY_EA_WRREQS_STALL_sum TCC_EA_ATOMIC_sum TCC_EA_RDREQ_LEVEL_sum TCC_EA_WRREQ_LEVEL_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID
+0,"vecCopy(double*, double*, double*, int, int)",2
+1,"vecCopy(double*, double*, double*, int, int)",2
+2,"vecCopy(double*, double*, double*, int, int)",2
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_BUFFER_WAVEFRONTS_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2506192,2506192,1048576,256,0,0,8,8,16,64,0x0,0x7f6d00ddce80,387944,231876,3381429,16384,24479957,144,48,0,48492,48492,3829962.0,2956311.0,7779.0,1218015.0,2028935.0,0.0,2947718.0,2636032.0,386879,241828,48492,0,48492,0,1551744.0,970309.0,0.0,0.0,5255486636623607,5255477523602709,5255477523626869,5255486644675676
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2506192,2506192,1048576,256,0,0,8,8,16,64,0x0,0x7f6d00ddce80,347176,226940,3324691,16384,24507650,0,48,0,43396,43396,3693477.0,3028337.0,5682.0,1119280.0,2040456.0,0.0,3019418.0,2707688.0,347168,236471,43396,0,43396,0,1388672.0,825503.0,0.0,0.0,5255486645190559,5255477523727189,5255477523745909,5255486645761069
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2506192,2506192,1048576,256,0,0,8,8,16,64,0x0,0x7f6d00ddce80,336256,224102,3276450,16384,24165791,0,48,0,42031,42031,3650603.0,2996298.0,6116.0,1082593.0,2000564.0,0.0,2987361.0,2675741.0,336248,233309,42031,0,42031,0,1344992.0,808442.0,0.0,0.0,5255486646287654,5255477523767029,5255477523785909,5255486646790496
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2503804,2503804,1048576,256,0,0,8,8,16,64,0x0,0x7fce2c1f6e80,0,0,192,0,65536,64463,48,1328,31457,0.0,0.0,0.0,32768.0,0.0,0.0,0.0,32768.0,4096,16384,566,47595,1753,0,48.0,267.0,0.0,262288.0,5255475603740413,5255477523602709,5255477523626869,5255475611599657
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2503804,2503804,1048576,256,0,0,8,8,16,64,0x0,0x7fce2c1f6e80,0,0,48,0,65536,65536,0,0,31418,0.0,0.0,0.0,32768.0,0.0,0.0,0.0,32768.0,4096,16384,485,43362,1692,0,48.0,260.0,0.0,262144.0,5255475612116504,5255477523727189,5255477523745909,5255475612678297
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2503804,2503804,1048576,256,0,0,8,8,16,64,0x0,0x7fce2c1f6e80,0,0,48,0,65536,65536,0,0,30785,0.0,0.0,0.0,32768.0,0.0,0.0,0.0,32768.0,4096,16384,484,42117,1769,0,48.0,292.0,0.0,262144.0,5255475613204502,5255477523767029,5255477523785909,5255475613684550
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,TCC_EA_ATOMIC_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2502411,2502411,1048576,256,0,0,8,8,16,64,0x0,0x7fbad2a9ee80,0.0,5255468851933661,5255477523602709,5255477523626869,5255468859346622
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2502411,2502411,1048576,256,0,0,8,8,16,64,0x0,0x7fbad2a9ee80,0.0,5255468859371759,5255477523727189,5255477523745909,5255468859732853
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2502411,2502411,1048576,256,0,0,8,8,16,64,0x0,0x7fbad2a9ee80,0.0,5255468859766997,5255477523767029,5255477523785909,5255468859987274
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2502809,2502809,1048576,256,0,0,8,8,16,64,0x0,0x7f6beb8d6e80,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,0,48711,0,0,5255471044333015,5255477523602709,5255477523626869,5255471052065240
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2502809,2502809,1048576,256,0,0,8,8,16,64,0x0,0x7f6beb8d6e80,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,0,43055,0,0,5255471052133319,5255477523727189,5255477523745909,5255471052654826
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2502809,2502809,1048576,256,0,0,8,8,16,64,0x0,0x7f6beb8d6e80,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,0,42511,0,0,5255471052732092,5255477523767029,5255477523785909,5255471053044382
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2502609,2502609,1048576,256,0,0,8,8,16,64,0x0,0x7f12c929ee80,4096,0,1630,0,4096,0,1318,0,4099,0,1107,0,4096,0,668,0,4096,0,850,0,4187,0,1462,0,4096,0,2185,0,4096,0,96,0,4096,0,937,0,4096,0,1065,0,4144,0,2608,0,4096,0,1315,0,4097,0,379,0,4096,0,2310,0,4096,0,1631,0,4096,0,18,0,4096,0,1714,0,4096,0,1709,0,4096,0,2055,0,4096,0,1403,0,4096,0,430,0,4096,0,1888,0,4096,0,429,0,4096,0,798,0,4096,0,206,0,4096,0,1680,0,4096,0,723,0,4096,0,596,0,4096,0,269,0,4096,0,1847,0,4144,0,1351,0,4096,0,5627,0,5255469945486487,5255477523602709,5255477523626869,5255469953250101
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2502609,2502609,1048576,256,0,0,8,8,16,64,0x0,0x7f12c929ee80,4096,0,24,0,4096,0,3641,0,4096,0,6674,0,4096,0,1381,0,4097,0,55,0,4188,0,116,0,4096,0,3627,0,4096,0,1530,0,4096,0,134,0,4096,0,33,0,4144,0,1747,0,4097,0,2094,0,4097,0,1110,0,4096,0,459,0,4096,0,2537,0,4096,0,71,0,4096,0,1573,0,4096,0,3596,0,4096,0,7691,0,4099,0,760,0,4096,0,158,0,4096,0,990,0,4096,0,1453,0,4097,0,2110,0,4096,0,0,0,4096,0,5352,0,4096,0,875,0,4096,0,56,0,4096,0,0,0,4096,0,0,0,4144,0,86,0,4096,0,249,0,5255469953316807,5255477523727189,5255477523745909,5255469953869372
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2502609,2502609,1048576,256,0,0,8,8,16,64,0x0,0x7f12c929ee80,4096,0,7377,0,4096,0,523,0,4096,0,90,0,4096,0,850,0,4097,0,0,0,4171,0,3051,0,4096,0,936,0,4096,0,1156,0,4096,0,0,0,4096,0,0,0,4144,0,0,0,4097,0,976,0,4097,0,299,0,4096,0,669,0,4096,0,393,0,4096,0,433,0,4096,0,1504,0,4096,0,96,0,4096,0,156,0,4099,0,948,0,4096,0,0,0,4096,0,1299,0,4096,0,744,0,4097,0,0,0,4096,0,0,0,4096,0,0,0,4096,0,0,0,4096,0,0,0,4096,0,0,0,4096,0,0,0,4144,0,0,0,4096,0,0,0,5255469953947330,5255477523767029,5255477523785909,5255469954345823
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2505195,2505195,1048576,256,0,0,8,8,16,64,0x0,0x7f6897764e80,0,4199967,4096,4096,0,3787845,4096,4096,0,3798826,4096,4096,0,3965707,4096,4096,0,4265502,4096,4096,0,3224875,4096,4096,0,3269732,4096,4096,0,4759519,4096,4096,0,3408748,4096,4096,0,3746181,4096,4096,0,4995994,4096,4096,0,4398527,4096,4096,0,4982045,4096,4096,0,4420582,4096,4096,0,3395586,4096,4096,0,3635501,4096,4096,0,4605479,4096,4096,0,4290013,4096,4096,0,5471570,4096,4096,0,3380308,4096,4096,0,2923558,4096,4096,0,4757409,4096,4096,0,4256877,4096,4096,0,3610068,4096,4096,0,3482292,4096,4096,0,4179240,4096,4096,0,3325666,4096,4096,0,4431641,4096,4096,0,3673996,4096,4096,0,3443525,4096,4096,0,5083134,4096,4096,0,3373160,4096,4096,5255482056061761,5255477523602709,5255477523626869,5255482063909393
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2505195,2505195,1048576,256,0,0,8,8,16,64,0x0,0x7f6897764e80,0,3945625,2720,2720,0,3637482,2698,2698,0,4160693,2728,2728,0,4267811,2700,2700,0,3988071,2669,2669,0,3381390,2740,2740,0,3869233,2724,2724,0,3821182,2678,2678,0,3595625,2699,2699,0,3964716,2696,2696,0,3735386,2718,2718,0,3810793,2732,2732,0,3903194,2708,2708,0,3457876,2696,2696,0,4311564,2712,2712,0,4873632,2710,2710,0,3099974,2674,2674,0,3699894,2734,2734,0,3717282,2720,2720,0,3980427,2740,2740,0,3296021,2684,2684,0,3293713,2753,2753,0,4565345,2708,2708,0,4438297,2692,2692,0,3736186,2673,2673,0,3842887,2718,2718,0,3861515,2722,2722,0,3487951,2722,2722,0,3451360,2690,2690,0,3260900,2702,2702,0,3906882,2714,2714,0,3761768,2726,2726,5255482063977883,5255477523727189,5255477523745909,5255482064534395
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2505195,2505195,1048576,256,0,0,8,8,16,64,0x0,0x7f6897764e80,0,3357033,2742,2742,0,3308360,2726,2726,0,3700260,2706,2706,0,3322244,2737,2737,0,3278681,2720,2720,0,3289291,2717,2717,0,4165032,2761,2761,0,3678049,2710,2710,0,2970411,2724,2724,0,3792083,2714,2714,0,3586427,2744,2744,0,4332538,2726,2726,0,3001487,2688,2688,0,3570121,2746,2746,0,3444118,2728,2728,0,4920101,2743,2743,0,3133024,2702,2702,0,3663592,2756,2756,0,3335035,2697,2697,0,4043109,2776,2776,0,3006236,2740,2740,0,4114151,2753,2753,0,4080535,2714,2714,0,3398524,2715,2715,0,2857780,2702,2702,0,3653575,2734,2734,0,3194397,2742,2742,0,3675930,2749,2749,0,2918960,2720,2720,0,3868721,2756,2756,0,3416089,2728,2728,0,3559499,2764,2764,5255482064611581,5255477523767029,5255477523785909,5255482065000797
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2505789,2505789,1048576,256,0,0,8,8,16,64,0x0,0x7f2464ff8e80,1362,0,0,1772749,2395,0,0,1915772,1708,0,0,1760583,1168,0,0,1774277,1921,0,0,1806044,2164,0,0,1922614,1585,0,0,1760526,1766,0,0,1841640,1175,0,0,1688581,3901,0,0,2055028,653,0,0,1665457,1728,0,0,1868750,692,0,0,1696121,6580,0,0,2265636,920,0,0,1748105,981,0,0,1712684,1547,0,0,1713275,1727,0,0,1761652,2644,0,0,1990127,3217,0,0,1968023,1163,0,0,1690656,3936,0,0,2055541,694,0,0,1738340,6885,0,0,2349657,2774,0,0,2003554,3232,0,0,2009370,1018,0,0,1778080,1799,0,0,1767463,1379,0,0,1712616,4321,0,0,2092130,1002,0,0,1796998,1905,0,0,1948391,5255484890454743,5255477523602709,5255477523626869,5255484898237743
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2505789,2505789,1048576,256,0,0,8,8,16,64,0x0,0x7f2464ff8e80,2825,0,0,1610320,2010,0,0,1453374,1976,0,0,1346409,5186,0,0,1766161,3192,0,0,1578145,668,0,0,1254082,1695,0,0,1442969,979,0,0,1298836,1648,0,0,1452923,1321,0,0,1367727,2775,0,0,1633999,651,0,0,1275994,5896,0,0,1852989,401,0,0,1129189,1422,0,0,1552545,1809,0,0,1512768,2878,0,0,1564059,15,0,0,1043562,5103,0,0,1807824,3203,0,0,1553366,3388,0,0,1605487,483,0,0,1187053,3305,0,0,1636655,2288,0,0,1425865,1464,0,0,1334573,826,0,0,1227040,1966,0,0,1481582,2399,0,0,1553371,2381,0,0,1522777,3921,0,0,1584294,6864,0,0,1899464,2317,0,0,1475340,5255484898307365,5255477523727189,5255477523745909,5255484898846344
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2505789,2505789,1048576,256,0,0,8,8,16,64,0x0,0x7f2464ff8e80,1658,0,0,1357005,815,0,0,1251707,806,0,0,1296471,8106,0,0,1971684,1010,0,0,1286227,2323,0,0,1506255,1671,0,0,1402325,732,0,0,1304578,976,0,0,1306722,418,0,0,1217583,995,0,0,1261259,194,0,0,1294151,1558,0,0,1261404,1021,0,0,1366638,3737,0,0,1663534,3082,0,0,1498572,555,0,0,1222219,983,0,0,1305704,806,0,0,1167812,1497,0,0,1300276,1751,0,0,1388434,4339,0,0,1710562,3905,0,0,1629757,6485,0,0,1797143,1565,0,0,1273292,711,0,0,1228676,1260,0,0,1411654,6337,0,0,1862579,1367,0,0,1302549,6269,0,0,1795652,1694,0,0,1375304,2504,0,0,1459175,5255484898923841,5255477523767029,5255477523785909,5255484899266228
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2503605,2503605,1048576,256,0,0,8,8,16,64,0x0,0x7fb0a8d5ce80,47,8193,4144,8240,0,8430,4334,8430,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,141,8195,4240,8336,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8240,4144,8240,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8208,4112,8208,0,8192,4096,8192,0,8192,4096,8192,0,8240,4144,8240,0,8192,4096,8192,5255474735075905,5255477523602709,5255477523626869,5255474742830210
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2503605,2503605,1048576,256,0,0,8,8,16,64,0x0,0x7fb0a8d5ce80,47,8193,4144,8240,0,8432,4336,8432,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8193,4097,8193,0,8195,4099,8195,0,8192,4096,8192,0,8192,4096,8192,0,8193,4097,8193,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8241,4145,8241,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8238,4142,8238,0,8192,4096,8192,0,8192,4096,8192,0,8240,4144,8240,0,8192,4096,8192,5255474742899311,5255477523727189,5255477523745909,5255474743409356
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2503605,2503605,1048576,256,0,0,8,8,16,64,0x0,0x7fb0a8d5ce80,47,8193,4144,8240,0,8432,4336,8432,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8193,4097,8193,0,8195,4099,8195,0,8192,4096,8192,0,8192,4096,8192,0,8193,4097,8193,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8241,4145,8241,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8242,4146,8242,0,8192,4096,8192,0,8192,4096,8192,0,8240,4144,8240,0,8192,4096,8192,5255474743486331,5255477523767029,5255477523785909,5255474743827256
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2504007,2504007,1048576,256,0,0,8,8,16,64,0x0,0x7f57fe5e8e80,8192,0,4096,8192,0,4096,8336,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,5255476648728339,5255477523602709,5255477523626869,5255476656514154
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2504007,2504007,1048576,256,0,0,8,8,16,64,0x0,0x7f57fe5e8e80,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,5255476656566463,5255477523727189,5255477523745909,5255476657042643
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2504007,2504007,1048576,256,0,0,8,8,16,64,0x0,0x7f57fe5e8e80,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,5255476657106815,5255477523767029,5255477523785909,5255476657435246
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2505393,2505393,1048576,256,0,0,8,8,16,64,0x0,0x7fb5c31cee80,127456,0,0,65536,64048,48,1440,32768,2097152.0,2097152.0,1048576.0,1048576.0,0.0,0.0,0.0,16384.0,12010,28394,9387,588,0,47301,262662.0,0.0,188.0,262474.0,5255482940426522,5255477523602709,5255477523626869,5255482948272190
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2505393,2505393,1048576,256,0,0,8,8,16,64,0x0,0x7fb5c31cee80,184963,0,0,65536,64048,48,1440,32768,2097152.0,2097152.0,1048576.0,1048576.0,0.0,0.0,0.0,16384.0,12316,28700,8604,3914,0,41168,262501.0,0.0,47.0,262454.0,5255482948787796,5255477523727189,5255477523745909,5255482949284144
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2505393,2505393,1048576,256,0,0,8,8,16,64,0x0,0x7fb5c31cee80,185097,0,0,65536,64048,48,1440,32768,2097152.0,2097152.0,1048576.0,1048576.0,0.0,0.0,0.0,16384.0,13067,29451,8454,3873,0,40781,262491.0,0.0,47.0,262444.0,5255482949810239,5255477523767029,5255477523785909,5255482950320134
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2502213,2502213,1048576,256,0,0,8,8,16,64,0x0,0x7faac8ab8e80,32768,0,16384,16384,32768,49152,0,65536,0.0,0.0,120.0,524288.0,0.0,0.0,0,0,913,47440,0,131523.0,131072.0,0.0,131104.0,5255467984134331,5255477523602709,5255477523626869,5255467992118683
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2502213,2502213,1048576,256,0,0,8,8,16,64,0x0,0x7faac8ab8e80,32768,0,16384,16384,32768,49152,0,65536,0.0,0.0,120.0,524288.0,0.0,0.0,0,0,2982,39242,0,131375.0,131072.0,0.0,86801.0,5255467992528158,5255477523727189,5255477523745909,5255467993009969
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2502213,2502213,1048576,256,0,0,8,8,16,64,0x0,0x7faac8ab8e80,32768,0,16384,16384,32768,49152,0,65536,0.0,0.0,120.0,524288.0,0.0,0.0,0,0,2740,38903,0,131366.0,131072.0,0.0,86478.0,5255467993387223,5255477523767029,5255477523785909,5255467993869645
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAIT_ANY,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_DRAM_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2504799,2504799,1048576,256,0,0,8,8,16,64,0x0,0x7fe944a7ae80,32768,0,0,0,16384,16384,393216,22818566,960.0,513929.0,0.0,524288.0,973160.0,32768.0,0,0,0,15853,131072.0,131072.0,0.0,131072.0,5255480092131817,5255477523602709,5255477523626869,5255480100121388
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2504799,2504799,1048576,256,0,0,8,8,16,64,0x0,0x7fe944a7ae80,32768,0,0,0,16384,16384,393216,22796945,960.0,513920.0,0.0,524288.0,1052429.0,32768.0,0,0,0,14374,86427.0,86427.0,0.0,86427.0,5255480100530732,5255477523727189,5255477523745909,5255480101042641
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2504799,2504799,1048576,256,0,0,8,8,16,64,0x0,0x7fe944a7ae80,32768,0,0,0,16384,16384,393216,23050498,960.0,513854.0,0.0,524288.0,1032802.0,32768.0,0,0,0,14514,86574.0,86574.0,0.0,86574.0,5255480101397161,5255477523767029,5255477523785909,5255480101867741
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_STALL_sum,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2504601,2504601,1048576,256,0,0,8,8,16,64,0x0,0x7fb93167ce80,2401097,360448,163840,0,0,180224,114688,0,63183910.0,178360826.0,73472986.0,131072.0,0.0,579128.0,0,0,26510,160674.0,0.0,0.0,160674.0,5255479238979177,5255477523602709,5255477523626869,5255479246825677
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2504601,2504601,1048576,256,0,0,8,8,16,64,0x0,0x7fb93167ce80,1749558,360448,163840,0,0,180224,114688,0,63804267.0,174389289.0,81563486.0,131072.0,0.0,1015017.0,0,0,28364,26297.0,0.0,0.0,26297.0,5255479247235002,5255477523727189,5255477523745909,5255479247715600
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2504601,2504601,1048576,256,0,0,8,8,16,64,0x0,0x7fb93167ce80,2266773,360448,163840,0,0,180224,114688,0,62333348.0,167139174.0,70212142.0,131072.0,0.0,502949.0,0,0,26360,150530.0,0.0,0.0,150530.0,5255479248061204,5255477523767029,5255477523785909,5255479248515834
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,TCC_EA_RDREQ_DRAM_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2503206,2503206,1048576,256,0,0,8,8,16,64,0x0,0x7f5165bcee80,32768,32768,16384,16384,65536,49152,11534336,65536,131072.0,0.0,0.0,0.0,32768.0,16384.0,0,0,131403.0,0.0,654.0,131402.0,5255472779999302,5255477523602709,5255477523626869,5255472787872554
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2503206,2503206,1048576,256,0,0,8,8,16,64,0x0,0x7f5165bcee80,32768,32768,16384,16384,65536,49152,11534336,65536,131072.0,0.0,0.0,0.0,32768.0,16384.0,0,0,131405.0,0.0,664.0,131404.0,5255472788280485,5255477523727189,5255477523745909,5255472788735096
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2503206,2503206,1048576,256,0,0,8,8,16,64,0x0,0x7f5165bcee80,32768,32768,16384,16384,65536,49152,11534336,65536,131072.0,0.0,0.0,0.0,32768.0,16384.0,0,0,131385.0,0.0,624.0,131384.0,5255472789121446,5255477523767029,5255477523785909,5255472789564955
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2503406,2503406,1048576,256,0,0,8,8,16,64,0x0,0x7fe43a3dce80,0,0,0,16384,0,0,0,0,0.0,0.0,0.0,0.0,16384.0,0.0,0,81920,0.0,0.0,28555.0,123147.0,5255473651421229,5255477523602709,5255477523626869,5255473659148252
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2503406,2503406,1048576,256,0,0,8,8,16,64,0x0,0x7fe43a3dce80,0,0,0,16384,0,0,0,0,0.0,0.0,0.0,0.0,16384.0,0.0,0,81920,0.0,0.0,24406.0,117740.0,5255473659556374,5255477523727189,5255477523745909,5255473660045560
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2503406,2503406,1048576,256,0,0,8,8,16,64,0x0,0x7fe43a3dce80,0,0,0,16384,0,0,0,0,0.0,0.0,0.0,0.0,16384.0,0.0,0,81920,0.0,0.0,30143.0,117619.0,5255473660464542,5255477523767029,5255477523785909,5255473660902821
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2504403,2504403,1048576,256,0,0,8,8,16,64,0x0,0x7f90e3670e80,1048576,0,0,0,0,0,131072,0.0,0.0,0.0,0.0,16384,0,86376.0,44696.0,131112.0,0.0,5255478374482041,5255477523602709,5255477523626869,5255478382738647
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2504403,2504403,1048576,256,0,0,8,8,16,64,0x0,0x7f90e3670e80,1048576,0,0,0,0,0,131072,0.0,0.0,0.0,0.0,16384,0,86650.0,0.0,131110.0,0.0,5255478383039316,5255477523727189,5255477523745909,5255478383517560
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2504403,2504403,1048576,256,0,0,8,8,16,64,0x0,0x7f90e3670e80,1048576,0,0,0,0,0,131072,0.0,0.0,0.0,0.0,16384,0,86608.0,0.0,131112.0,0.0,5255478383710425,5255477523767029,5255477523785909,5255478384197656
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2503007,2503007,1048576,256,0,0,8,8,16,64,0x0,0x7fc2645dae80,131072.0,131072.0,0.0,2634051.0,0.0,0.0,101035301.0,60679800.0,5255471915112862,5255477523602709,5255477523626869,5255471922855878
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2503007,2503007,1048576,256,0,0,8,8,16,64,0x0,0x7fc2645dae80,131072.0,131072.0,0.0,2636684.0,0.0,0.0,132074784.0,48137103.0,5255471923130227,5255477523727189,5255477523745909,5255471923536144
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2503007,2503007,1048576,256,0,0,8,8,16,64,0x0,0x7fc2645dae80,131072.0,131072.0,0.0,2615156.0,0.0,0.0,108332268.0,49336132.0,5255471923718419,5255477523767029,5255477523785909,5255471924155456
@@ -0,0 +1,2 @@
+workload_name,command,host_name,host_cpu,sbios,host_distro,host_kernel,host_rocmver,date,gpu_soc,vbios,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,totalL2Banks,LDSBanks,name,numSQC,numPipes,hbmBW,compute_partition,memory_partition,ip_blocks
+app_1,./tests/vcopy -n 1048576 -b 256 -i 3,t004-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,5.7.1-98,Wed Feb 14 11:44:01 2024 (CST),gfx908,113-D3431401-100,8,120,4,64,40,1024,16,8192,1502,1200,1502,1200,32,32,32,MI100,30,4,1200,,,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,1332584,1332584,1048576,256,0,0,8,8,16,64,0x0,0x7f9fcce86e80,5862046126473749,5862046126501116,5862046126524956,5862046126538100
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,1332584,1332584,1048576,256,0,0,8,8,16,64,0x0,0x7f9fcce86e80,5862046126537579,5862046126616796,5862046126635516,5862046126636526
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,1332584,1332584,1048576,256,0,0,8,8,16,64,0x0,0x7f9fcce86e80,5862046126648188,5862046126657436,5862046126676476,5862046126677664
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2695647,2695647,1048576,256,0,0,8,0,16,64,0x0,0x7f8e6993cec0,27987,27987,16384,65536,13259,1512196,2423827663335467,2423816758936208,2423816758956208,2423827678821236
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2695647,2695647,1048576,256,0,0,8,0,16,64,0x0,0x7f8e6993cec0,41409,41409,16384,65536,9342,1048640,2423827678841204,2423816758974928,2423816758990448,2423827679167481
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2695647,2695647,1048576,256,0,0,8,0,16,64,0x0,0x7f8e6993cec0,42107,42107,16384,65536,9319,1048704,2423827679204520,2423816759063728,2423816759080688,2423827679384871
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2690991,2690991,1048576,256,0,0,8,0,16,64,0x0,0x7fbcd5864ec0,0,0,0,2423803831466254,2423816758936208,2423816758956208,2423803847254015
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2690991,2690991,1048576,256,0,0,8,0,16,64,0x0,0x7fbcd5864ec0,0,0,0,2423803847273952,2423816758974928,2423816758990448,2423803847594598
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2690991,2690991,1048576,256,0,0,8,0,16,64,0x0,0x7fbcd5864ec0,0,0,0,2423803847620387,2423816759063728,2423816759080688,2423803847781652
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2695445,2695445,1048576,256,0,0,8,0,16,64,0x0,0x7facdf810ec0,65536,199108,22345568,2423826707526640,2423816758936208,2423816758956208,2423826723521191
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2695445,2695445,1048576,256,0,0,8,0,16,64,0x0,0x7facdf810ec0,65536,279492,31248008,2423826723547862,2423816758974928,2423816758990448,2423826723876613
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2695445,2695445,1048576,256,0,0,8,0,16,64,0x0,0x7facdf810ec0,65536,297828,33376048,2423826723903344,2423816759063728,2423816759080688,2423826724073595
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2691397,2691397,1048576,256,0,0,8,0,16,64,0x0,0x7f2c3aac8ec0,32768,299874,33590924,2423805825500971,2423816758936208,2423816758956208,2423805841017168
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2691397,2691397,1048576,256,0,0,8,0,16,64,0x0,0x7f2c3aac8ec0,32768,590892,66171900,2423805841024021,2423816758974928,2423816758990448,2423805841366077
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2691397,2691397,1048576,256,0,0,8,0,16,64,0x0,0x7f2c3aac8ec0,32768,587630,65806776,2423805841393178,2423816759063728,2423816759080688,2423805841573549
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2692813,2692813,1048576,256,0,0,8,0,16,64,0x0,0x7efeaac8cec0,27886,27886,10990,223096,16384,11169429,131145,0,45174824,2423813660512481,2423816758936208,2423816758956208,2423813676161599
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2692813,2692813,1048576,256,0,0,8,0,16,64,0x0,0x7efeaac8cec0,42468,42468,14278,339752,16384,20055323,227652,0,80702288,2423813676188640,2423816758974928,2423816758990448,2423813676510959
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2692813,2692813,1048576,256,0,0,8,0,16,64,0x0,0x7efeaac8cec0,41526,41526,13353,332216,16384,19715179,224611,0,79334060,2423813676546005,2423816759063728,2423816759080688,2423813676718491
@@ -0,0 +1,5 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_WAVES SQ_IFETCH SQ_IFETCH_LEVEL  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_LDS SQ_INST_LEVEL_LDS  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_SMEM  SQ_INST_LEVEL_SMEM SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_VMEM  SQ_INST_LEVEL_VMEM SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE CPC_ME1_BUSY_FOR_PACKET_DECODE SQ_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_BUSY_CYCLES SQ_LEVEL_WAVES  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_INSTS_VALU_CVT SQ_INSTS_VMEM_WR SQ_INSTS_VMEM_RD GRBM_COUNT GRBM_GUI_ACTIVE TCP_GATE_EN1_sum TCP_GATE_EN2_sum TCP_TD_TCP_STALL_CYCLES_sum TCP_TCR_TCP_STALL_CYCLES_sum TA_TA_BUSY_sum TA_BUFFER_WAVEFRONTS_sum TD_TD_BUSY_sum TD_TC_STALL_sum SPI_CSN_WINDOW_VALID SPI_CSN_BUSY CPC_CPC_STAT_BUSY CPC_CPC_STAT_IDLE CPF_CPF_STAT_BUSY CPF_CPF_STAT_STALL TCC_CYCLE_sum TCC_BUSY_sum TCC_PROBE_sum TCC_PROBE_ALL_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VMEM SQ_INSTS_SALU SQ_INSTS_VSKIPPED SQ_INSTS SQ_INSTS_VALU SQ_INSTS_VALU_ADD_F16 SQ_INSTS_VALU_MUL_F16 SQ_INSTS_VALU_FMA_F16 GRBM_SPI_BUSY TCP_READ_TAGCONFLICT_STALL_CYCLES_sum TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum TCP_TA_TCP_STATE_READ_sum TA_BUFFER_READ_WAVEFRONTS_sum TA_BUFFER_WRITE_WAVEFRONTS_sum TD_SPI_STALL_sum TD_LOAD_WAVEFRONT_sum SPI_CSN_NUM_THREADGROUPS SPI_CSN_WAVE CPC_CPC_TCIU_BUSY CPC_CPC_TCIU_IDLE CPF_CPF_TCIU_BUSY CPF_CPF_TCIU_STALL TCC_NC_REQ_sum TCC_UC_REQ_sum TCC_CC_REQ_sum TCC_RW_REQ_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_TC_DATA_WRITE_REQ SQC_TC_DATA_ATOMIC_REQ SQC_TC_STALL SQC_TC_REQ SQC_DCACHE_REQ_READ_16 SQC_ICACHE_REQ SQC_ICACHE_HITS SQC_ICACHE_MISSES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_ICACHE_MISSES_DUPLICATE SQC_DCACHE_INPUT_VALID_READYB SQC_DCACHE_ATOMIC SQC_DCACHE_REQ_READ_8 SQC_DCACHE_REQ SQC_DCACHE_HITS SQC_DCACHE_MISSES SQC_DCACHE_MISSES_DUPLICATE
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_DCACHE_REQ_READ_1 SQC_DCACHE_REQ_READ_2 SQC_DCACHE_REQ_READ_4
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_ATOMIC[0] TCC_CYCLE[0] TCC_EA_ATOMIC[0] TCC_EA_ATOMIC_LEVEL[0] TCC_ATOMIC[1] TCC_CYCLE[1] TCC_EA_ATOMIC[1] TCC_EA_ATOMIC_LEVEL[1] TCC_ATOMIC[2] TCC_CYCLE[2] TCC_EA_ATOMIC[2] TCC_EA_ATOMIC_LEVEL[2] TCC_ATOMIC[3] TCC_CYCLE[3] TCC_EA_ATOMIC[3] TCC_EA_ATOMIC_LEVEL[3] TCC_ATOMIC[4] TCC_CYCLE[4] TCC_EA_ATOMIC[4] TCC_EA_ATOMIC_LEVEL[4] TCC_ATOMIC[5] TCC_CYCLE[5] TCC_EA_ATOMIC[5] TCC_EA_ATOMIC_LEVEL[5] TCC_ATOMIC[6] TCC_CYCLE[6] TCC_EA_ATOMIC[6] TCC_EA_ATOMIC_LEVEL[6] TCC_ATOMIC[7] TCC_CYCLE[7] TCC_EA_ATOMIC[7] TCC_EA_ATOMIC_LEVEL[7] TCC_ATOMIC[8] TCC_CYCLE[8] TCC_EA_ATOMIC[8] TCC_EA_ATOMIC_LEVEL[8] TCC_ATOMIC[9] TCC_CYCLE[9] TCC_EA_ATOMIC[9] TCC_EA_ATOMIC_LEVEL[9] TCC_ATOMIC[10] TCC_CYCLE[10] TCC_EA_ATOMIC[10] TCC_EA_ATOMIC_LEVEL[10] TCC_ATOMIC[11] TCC_CYCLE[11] TCC_EA_ATOMIC[11] TCC_EA_ATOMIC_LEVEL[11] TCC_ATOMIC[12] TCC_CYCLE[12] TCC_EA_ATOMIC[12] TCC_EA_ATOMIC_LEVEL[12] TCC_ATOMIC[13] TCC_CYCLE[13] TCC_EA_ATOMIC[13] TCC_EA_ATOMIC_LEVEL[13] TCC_ATOMIC[14] TCC_CYCLE[14] TCC_EA_ATOMIC[14] TCC_EA_ATOMIC_LEVEL[14] TCC_ATOMIC[15] TCC_CYCLE[15] TCC_EA_ATOMIC[15] TCC_EA_ATOMIC_LEVEL[15] TCC_ATOMIC[16] TCC_CYCLE[16] TCC_EA_ATOMIC[16] TCC_EA_ATOMIC_LEVEL[16] TCC_ATOMIC[17] TCC_CYCLE[17] TCC_EA_ATOMIC[17] TCC_EA_ATOMIC_LEVEL[17] TCC_ATOMIC[18] TCC_CYCLE[18] TCC_EA_ATOMIC[18] TCC_EA_ATOMIC_LEVEL[18] TCC_ATOMIC[19] TCC_CYCLE[19] TCC_EA_ATOMIC[19] TCC_EA_ATOMIC_LEVEL[19] TCC_ATOMIC[20] TCC_CYCLE[20] TCC_EA_ATOMIC[20] TCC_EA_ATOMIC_LEVEL[20] TCC_ATOMIC[21] TCC_CYCLE[21] TCC_EA_ATOMIC[21] TCC_EA_ATOMIC_LEVEL[21] TCC_ATOMIC[22] TCC_CYCLE[22] TCC_EA_ATOMIC[22] TCC_EA_ATOMIC_LEVEL[22] TCC_ATOMIC[23] TCC_CYCLE[23] TCC_EA_ATOMIC[23] TCC_EA_ATOMIC_LEVEL[23] TCC_ATOMIC[24] TCC_CYCLE[24] TCC_EA_ATOMIC[24] TCC_EA_ATOMIC_LEVEL[24] TCC_ATOMIC[25] TCC_CYCLE[25] TCC_EA_ATOMIC[25] TCC_EA_ATOMIC_LEVEL[25] TCC_ATOMIC[26] TCC_CYCLE[26] TCC_EA_ATOMIC[26] TCC_EA_ATOMIC_LEVEL[26] TCC_ATOMIC[27] TCC_CYCLE[27] TCC_EA_ATOMIC[27] TCC_EA_ATOMIC_LEVEL[27] TCC_ATOMIC[28] TCC_CYCLE[28] TCC_EA_ATOMIC[28] TCC_EA_ATOMIC_LEVEL[28] TCC_ATOMIC[29] TCC_CYCLE[29] TCC_EA_ATOMIC[29] TCC_EA_ATOMIC_LEVEL[29] TCC_ATOMIC[30] TCC_CYCLE[30] TCC_EA_ATOMIC[30] TCC_EA_ATOMIC_LEVEL[30] TCC_ATOMIC[31] TCC_CYCLE[31] TCC_EA_ATOMIC[31] TCC_EA_ATOMIC_LEVEL[31]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_EA_RDREQ[0] TCC_EA_RDREQ_32B[0] TCC_EA_RDREQ_DRAM_CREDIT_STALL[0] TCC_EA_RDREQ_GMI_CREDIT_STALL[0] TCC_EA_RDREQ[1] TCC_EA_RDREQ_32B[1] TCC_EA_RDREQ_DRAM_CREDIT_STALL[1] TCC_EA_RDREQ_GMI_CREDIT_STALL[1] TCC_EA_RDREQ[2] TCC_EA_RDREQ_32B[2] TCC_EA_RDREQ_DRAM_CREDIT_STALL[2] TCC_EA_RDREQ_GMI_CREDIT_STALL[2] TCC_EA_RDREQ[3] TCC_EA_RDREQ_32B[3] TCC_EA_RDREQ_DRAM_CREDIT_STALL[3] TCC_EA_RDREQ_GMI_CREDIT_STALL[3] TCC_EA_RDREQ[4] TCC_EA_RDREQ_32B[4] TCC_EA_RDREQ_DRAM_CREDIT_STALL[4] TCC_EA_RDREQ_GMI_CREDIT_STALL[4] TCC_EA_RDREQ[5] TCC_EA_RDREQ_32B[5] TCC_EA_RDREQ_DRAM_CREDIT_STALL[5] TCC_EA_RDREQ_GMI_CREDIT_STALL[5] TCC_EA_RDREQ[6] TCC_EA_RDREQ_32B[6] TCC_EA_RDREQ_DRAM_CREDIT_STALL[6] TCC_EA_RDREQ_GMI_CREDIT_STALL[6] TCC_EA_RDREQ[7] TCC_EA_RDREQ_32B[7] TCC_EA_RDREQ_DRAM_CREDIT_STALL[7] TCC_EA_RDREQ_GMI_CREDIT_STALL[7] TCC_EA_RDREQ[8] TCC_EA_RDREQ_32B[8] TCC_EA_RDREQ_DRAM_CREDIT_STALL[8] TCC_EA_RDREQ_GMI_CREDIT_STALL[8] TCC_EA_RDREQ[9] TCC_EA_RDREQ_32B[9] TCC_EA_RDREQ_DRAM_CREDIT_STALL[9] TCC_EA_RDREQ_GMI_CREDIT_STALL[9] TCC_EA_RDREQ[10] TCC_EA_RDREQ_32B[10] TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] TCC_EA_RDREQ_GMI_CREDIT_STALL[10] TCC_EA_RDREQ[11] TCC_EA_RDREQ_32B[11] TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] TCC_EA_RDREQ_GMI_CREDIT_STALL[11] TCC_EA_RDREQ[12] TCC_EA_RDREQ_32B[12] TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] TCC_EA_RDREQ_GMI_CREDIT_STALL[12] TCC_EA_RDREQ[13] TCC_EA_RDREQ_32B[13] TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] TCC_EA_RDREQ_GMI_CREDIT_STALL[13] TCC_EA_RDREQ[14] TCC_EA_RDREQ_32B[14] TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] TCC_EA_RDREQ_GMI_CREDIT_STALL[14] TCC_EA_RDREQ[15] TCC_EA_RDREQ_32B[15] TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] TCC_EA_RDREQ_GMI_CREDIT_STALL[15] TCC_EA_RDREQ[16] TCC_EA_RDREQ_32B[16] TCC_EA_RDREQ_DRAM_CREDIT_STALL[16] TCC_EA_RDREQ_GMI_CREDIT_STALL[16] TCC_EA_RDREQ[17] TCC_EA_RDREQ_32B[17] TCC_EA_RDREQ_DRAM_CREDIT_STALL[17] TCC_EA_RDREQ_GMI_CREDIT_STALL[17] TCC_EA_RDREQ[18] TCC_EA_RDREQ_32B[18] TCC_EA_RDREQ_DRAM_CREDIT_STALL[18] TCC_EA_RDREQ_GMI_CREDIT_STALL[18] TCC_EA_RDREQ[19] TCC_EA_RDREQ_32B[19] TCC_EA_RDREQ_DRAM_CREDIT_STALL[19] TCC_EA_RDREQ_GMI_CREDIT_STALL[19] TCC_EA_RDREQ[20] TCC_EA_RDREQ_32B[20] TCC_EA_RDREQ_DRAM_CREDIT_STALL[20] TCC_EA_RDREQ_GMI_CREDIT_STALL[20] TCC_EA_RDREQ[21] TCC_EA_RDREQ_32B[21] TCC_EA_RDREQ_DRAM_CREDIT_STALL[21] TCC_EA_RDREQ_GMI_CREDIT_STALL[21] TCC_EA_RDREQ[22] TCC_EA_RDREQ_32B[22] TCC_EA_RDREQ_DRAM_CREDIT_STALL[22] TCC_EA_RDREQ_GMI_CREDIT_STALL[22] TCC_EA_RDREQ[23] TCC_EA_RDREQ_32B[23] TCC_EA_RDREQ_DRAM_CREDIT_STALL[23] TCC_EA_RDREQ_GMI_CREDIT_STALL[23] TCC_EA_RDREQ[24] TCC_EA_RDREQ_32B[24] TCC_EA_RDREQ_DRAM_CREDIT_STALL[24] TCC_EA_RDREQ_GMI_CREDIT_STALL[24] TCC_EA_RDREQ[25] TCC_EA_RDREQ_32B[25] TCC_EA_RDREQ_DRAM_CREDIT_STALL[25] TCC_EA_RDREQ_GMI_CREDIT_STALL[25] TCC_EA_RDREQ[26] TCC_EA_RDREQ_32B[26] TCC_EA_RDREQ_DRAM_CREDIT_STALL[26] TCC_EA_RDREQ_GMI_CREDIT_STALL[26] TCC_EA_RDREQ[27] TCC_EA_RDREQ_32B[27] TCC_EA_RDREQ_DRAM_CREDIT_STALL[27] TCC_EA_RDREQ_GMI_CREDIT_STALL[27] TCC_EA_RDREQ[28] TCC_EA_RDREQ_32B[28] TCC_EA_RDREQ_DRAM_CREDIT_STALL[28] TCC_EA_RDREQ_GMI_CREDIT_STALL[28] TCC_EA_RDREQ[29] TCC_EA_RDREQ_32B[29] TCC_EA_RDREQ_DRAM_CREDIT_STALL[29] TCC_EA_RDREQ_GMI_CREDIT_STALL[29] TCC_EA_RDREQ[30] TCC_EA_RDREQ_32B[30] TCC_EA_RDREQ_DRAM_CREDIT_STALL[30] TCC_EA_RDREQ_GMI_CREDIT_STALL[30] TCC_EA_RDREQ[31] TCC_EA_RDREQ_32B[31] TCC_EA_RDREQ_DRAM_CREDIT_STALL[31] TCC_EA_RDREQ_GMI_CREDIT_STALL[31]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_EA_RDREQ_IO_CREDIT_STALL[0] TCC_EA_RDREQ_LEVEL[0] TCC_EA_WRREQ[0] TCC_EA_WRREQ_64B[0] TCC_EA_RDREQ_IO_CREDIT_STALL[1] TCC_EA_RDREQ_LEVEL[1] TCC_EA_WRREQ[1] TCC_EA_WRREQ_64B[1] TCC_EA_RDREQ_IO_CREDIT_STALL[2] TCC_EA_RDREQ_LEVEL[2] TCC_EA_WRREQ[2] TCC_EA_WRREQ_64B[2] TCC_EA_RDREQ_IO_CREDIT_STALL[3] TCC_EA_RDREQ_LEVEL[3] TCC_EA_WRREQ[3] TCC_EA_WRREQ_64B[3] TCC_EA_RDREQ_IO_CREDIT_STALL[4] TCC_EA_RDREQ_LEVEL[4] TCC_EA_WRREQ[4] TCC_EA_WRREQ_64B[4] TCC_EA_RDREQ_IO_CREDIT_STALL[5] TCC_EA_RDREQ_LEVEL[5] TCC_EA_WRREQ[5] TCC_EA_WRREQ_64B[5] TCC_EA_RDREQ_IO_CREDIT_STALL[6] TCC_EA_RDREQ_LEVEL[6] TCC_EA_WRREQ[6] TCC_EA_WRREQ_64B[6] TCC_EA_RDREQ_IO_CREDIT_STALL[7] TCC_EA_RDREQ_LEVEL[7] TCC_EA_WRREQ[7] TCC_EA_WRREQ_64B[7] TCC_EA_RDREQ_IO_CREDIT_STALL[8] TCC_EA_RDREQ_LEVEL[8] TCC_EA_WRREQ[8] TCC_EA_WRREQ_64B[8] TCC_EA_RDREQ_IO_CREDIT_STALL[9] TCC_EA_RDREQ_LEVEL[9] TCC_EA_WRREQ[9] TCC_EA_WRREQ_64B[9] TCC_EA_RDREQ_IO_CREDIT_STALL[10] TCC_EA_RDREQ_LEVEL[10] TCC_EA_WRREQ[10] TCC_EA_WRREQ_64B[10] TCC_EA_RDREQ_IO_CREDIT_STALL[11] TCC_EA_RDREQ_LEVEL[11] TCC_EA_WRREQ[11] TCC_EA_WRREQ_64B[11] TCC_EA_RDREQ_IO_CREDIT_STALL[12] TCC_EA_RDREQ_LEVEL[12] TCC_EA_WRREQ[12] TCC_EA_WRREQ_64B[12] TCC_EA_RDREQ_IO_CREDIT_STALL[13] TCC_EA_RDREQ_LEVEL[13] TCC_EA_WRREQ[13] TCC_EA_WRREQ_64B[13] TCC_EA_RDREQ_IO_CREDIT_STALL[14] TCC_EA_RDREQ_LEVEL[14] TCC_EA_WRREQ[14] TCC_EA_WRREQ_64B[14] TCC_EA_RDREQ_IO_CREDIT_STALL[15] TCC_EA_RDREQ_LEVEL[15] TCC_EA_WRREQ[15] TCC_EA_WRREQ_64B[15] TCC_EA_RDREQ_IO_CREDIT_STALL[16] TCC_EA_RDREQ_LEVEL[16] TCC_EA_WRREQ[16] TCC_EA_WRREQ_64B[16] TCC_EA_RDREQ_IO_CREDIT_STALL[17] TCC_EA_RDREQ_LEVEL[17] TCC_EA_WRREQ[17] TCC_EA_WRREQ_64B[17] TCC_EA_RDREQ_IO_CREDIT_STALL[18] TCC_EA_RDREQ_LEVEL[18] TCC_EA_WRREQ[18] TCC_EA_WRREQ_64B[18] TCC_EA_RDREQ_IO_CREDIT_STALL[19] TCC_EA_RDREQ_LEVEL[19] TCC_EA_WRREQ[19] TCC_EA_WRREQ_64B[19] TCC_EA_RDREQ_IO_CREDIT_STALL[20] TCC_EA_RDREQ_LEVEL[20] TCC_EA_WRREQ[20] TCC_EA_WRREQ_64B[20] TCC_EA_RDREQ_IO_CREDIT_STALL[21] TCC_EA_RDREQ_LEVEL[21] TCC_EA_WRREQ[21] TCC_EA_WRREQ_64B[21] TCC_EA_RDREQ_IO_CREDIT_STALL[22] TCC_EA_RDREQ_LEVEL[22] TCC_EA_WRREQ[22] TCC_EA_WRREQ_64B[22] TCC_EA_RDREQ_IO_CREDIT_STALL[23] TCC_EA_RDREQ_LEVEL[23] TCC_EA_WRREQ[23] TCC_EA_WRREQ_64B[23] TCC_EA_RDREQ_IO_CREDIT_STALL[24] TCC_EA_RDREQ_LEVEL[24] TCC_EA_WRREQ[24] TCC_EA_WRREQ_64B[24] TCC_EA_RDREQ_IO_CREDIT_STALL[25] TCC_EA_RDREQ_LEVEL[25] TCC_EA_WRREQ[25] TCC_EA_WRREQ_64B[25] TCC_EA_RDREQ_IO_CREDIT_STALL[26] TCC_EA_RDREQ_LEVEL[26] TCC_EA_WRREQ[26] TCC_EA_WRREQ_64B[26] TCC_EA_RDREQ_IO_CREDIT_STALL[27] TCC_EA_RDREQ_LEVEL[27] TCC_EA_WRREQ[27] TCC_EA_WRREQ_64B[27] TCC_EA_RDREQ_IO_CREDIT_STALL[28] TCC_EA_RDREQ_LEVEL[28] TCC_EA_WRREQ[28] TCC_EA_WRREQ_64B[28] TCC_EA_RDREQ_IO_CREDIT_STALL[29] TCC_EA_RDREQ_LEVEL[29] TCC_EA_WRREQ[29] TCC_EA_WRREQ_64B[29] TCC_EA_RDREQ_IO_CREDIT_STALL[30] TCC_EA_RDREQ_LEVEL[30] TCC_EA_WRREQ[30] TCC_EA_WRREQ_64B[30] TCC_EA_RDREQ_IO_CREDIT_STALL[31] TCC_EA_RDREQ_LEVEL[31] TCC_EA_WRREQ[31] TCC_EA_WRREQ_64B[31]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_EA_WRREQ_DRAM_CREDIT_STALL[0] TCC_EA_WRREQ_GMI_CREDIT_STALL[0] TCC_EA_WRREQ_IO_CREDIT_STALL[0] TCC_EA_WRREQ_LEVEL[0] TCC_EA_WRREQ_DRAM_CREDIT_STALL[1] TCC_EA_WRREQ_GMI_CREDIT_STALL[1] TCC_EA_WRREQ_IO_CREDIT_STALL[1] TCC_EA_WRREQ_LEVEL[1] TCC_EA_WRREQ_DRAM_CREDIT_STALL[2] TCC_EA_WRREQ_GMI_CREDIT_STALL[2] TCC_EA_WRREQ_IO_CREDIT_STALL[2] TCC_EA_WRREQ_LEVEL[2] TCC_EA_WRREQ_DRAM_CREDIT_STALL[3] TCC_EA_WRREQ_GMI_CREDIT_STALL[3] TCC_EA_WRREQ_IO_CREDIT_STALL[3] TCC_EA_WRREQ_LEVEL[3] TCC_EA_WRREQ_DRAM_CREDIT_STALL[4] TCC_EA_WRREQ_GMI_CREDIT_STALL[4] TCC_EA_WRREQ_IO_CREDIT_STALL[4] TCC_EA_WRREQ_LEVEL[4] TCC_EA_WRREQ_DRAM_CREDIT_STALL[5] TCC_EA_WRREQ_GMI_CREDIT_STALL[5] TCC_EA_WRREQ_IO_CREDIT_STALL[5] TCC_EA_WRREQ_LEVEL[5] TCC_EA_WRREQ_DRAM_CREDIT_STALL[6] TCC_EA_WRREQ_GMI_CREDIT_STALL[6] TCC_EA_WRREQ_IO_CREDIT_STALL[6] TCC_EA_WRREQ_LEVEL[6] TCC_EA_WRREQ_DRAM_CREDIT_STALL[7] TCC_EA_WRREQ_GMI_CREDIT_STALL[7] TCC_EA_WRREQ_IO_CREDIT_STALL[7] TCC_EA_WRREQ_LEVEL[7] TCC_EA_WRREQ_DRAM_CREDIT_STALL[8] TCC_EA_WRREQ_GMI_CREDIT_STALL[8] TCC_EA_WRREQ_IO_CREDIT_STALL[8] TCC_EA_WRREQ_LEVEL[8] TCC_EA_WRREQ_DRAM_CREDIT_STALL[9] TCC_EA_WRREQ_GMI_CREDIT_STALL[9] TCC_EA_WRREQ_IO_CREDIT_STALL[9] TCC_EA_WRREQ_LEVEL[9] TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] TCC_EA_WRREQ_GMI_CREDIT_STALL[10] TCC_EA_WRREQ_IO_CREDIT_STALL[10] TCC_EA_WRREQ_LEVEL[10] TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] TCC_EA_WRREQ_GMI_CREDIT_STALL[11] TCC_EA_WRREQ_IO_CREDIT_STALL[11] TCC_EA_WRREQ_LEVEL[11] TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] TCC_EA_WRREQ_GMI_CREDIT_STALL[12] TCC_EA_WRREQ_IO_CREDIT_STALL[12] TCC_EA_WRREQ_LEVEL[12] TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] TCC_EA_WRREQ_GMI_CREDIT_STALL[13] TCC_EA_WRREQ_IO_CREDIT_STALL[13] TCC_EA_WRREQ_LEVEL[13] TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] TCC_EA_WRREQ_GMI_CREDIT_STALL[14] TCC_EA_WRREQ_IO_CREDIT_STALL[14] TCC_EA_WRREQ_LEVEL[14] TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] TCC_EA_WRREQ_GMI_CREDIT_STALL[15] TCC_EA_WRREQ_IO_CREDIT_STALL[15] TCC_EA_WRREQ_LEVEL[15] TCC_EA_WRREQ_DRAM_CREDIT_STALL[16] TCC_EA_WRREQ_GMI_CREDIT_STALL[16] TCC_EA_WRREQ_IO_CREDIT_STALL[16] TCC_EA_WRREQ_LEVEL[16] TCC_EA_WRREQ_DRAM_CREDIT_STALL[17] TCC_EA_WRREQ_GMI_CREDIT_STALL[17] TCC_EA_WRREQ_IO_CREDIT_STALL[17] TCC_EA_WRREQ_LEVEL[17] TCC_EA_WRREQ_DRAM_CREDIT_STALL[18] TCC_EA_WRREQ_GMI_CREDIT_STALL[18] TCC_EA_WRREQ_IO_CREDIT_STALL[18] TCC_EA_WRREQ_LEVEL[18] TCC_EA_WRREQ_DRAM_CREDIT_STALL[19] TCC_EA_WRREQ_GMI_CREDIT_STALL[19] TCC_EA_WRREQ_IO_CREDIT_STALL[19] TCC_EA_WRREQ_LEVEL[19] TCC_EA_WRREQ_DRAM_CREDIT_STALL[20] TCC_EA_WRREQ_GMI_CREDIT_STALL[20] TCC_EA_WRREQ_IO_CREDIT_STALL[20] TCC_EA_WRREQ_LEVEL[20] TCC_EA_WRREQ_DRAM_CREDIT_STALL[21] TCC_EA_WRREQ_GMI_CREDIT_STALL[21] TCC_EA_WRREQ_IO_CREDIT_STALL[21] TCC_EA_WRREQ_LEVEL[21] TCC_EA_WRREQ_DRAM_CREDIT_STALL[22] TCC_EA_WRREQ_GMI_CREDIT_STALL[22] TCC_EA_WRREQ_IO_CREDIT_STALL[22] TCC_EA_WRREQ_LEVEL[22] TCC_EA_WRREQ_DRAM_CREDIT_STALL[23] TCC_EA_WRREQ_GMI_CREDIT_STALL[23] TCC_EA_WRREQ_IO_CREDIT_STALL[23] TCC_EA_WRREQ_LEVEL[23] TCC_EA_WRREQ_DRAM_CREDIT_STALL[24] TCC_EA_WRREQ_GMI_CREDIT_STALL[24] TCC_EA_WRREQ_IO_CREDIT_STALL[24] TCC_EA_WRREQ_LEVEL[24] TCC_EA_WRREQ_DRAM_CREDIT_STALL[25] TCC_EA_WRREQ_GMI_CREDIT_STALL[25] TCC_EA_WRREQ_IO_CREDIT_STALL[25] TCC_EA_WRREQ_LEVEL[25] TCC_EA_WRREQ_DRAM_CREDIT_STALL[26] TCC_EA_WRREQ_GMI_CREDIT_STALL[26] TCC_EA_WRREQ_IO_CREDIT_STALL[26] TCC_EA_WRREQ_LEVEL[26] TCC_EA_WRREQ_DRAM_CREDIT_STALL[27] TCC_EA_WRREQ_GMI_CREDIT_STALL[27] TCC_EA_WRREQ_IO_CREDIT_STALL[27] TCC_EA_WRREQ_LEVEL[27] TCC_EA_WRREQ_DRAM_CREDIT_STALL[28] TCC_EA_WRREQ_GMI_CREDIT_STALL[28] TCC_EA_WRREQ_IO_CREDIT_STALL[28] TCC_EA_WRREQ_LEVEL[28] TCC_EA_WRREQ_DRAM_CREDIT_STALL[29] TCC_EA_WRREQ_GMI_CREDIT_STALL[29] TCC_EA_WRREQ_IO_CREDIT_STALL[29] TCC_EA_WRREQ_LEVEL[29] TCC_EA_WRREQ_DRAM_CREDIT_STALL[30] TCC_EA_WRREQ_GMI_CREDIT_STALL[30] TCC_EA_WRREQ_IO_CREDIT_STALL[30] TCC_EA_WRREQ_LEVEL[30] TCC_EA_WRREQ_DRAM_CREDIT_STALL[31] TCC_EA_WRREQ_GMI_CREDIT_STALL[31] TCC_EA_WRREQ_IO_CREDIT_STALL[31] TCC_EA_WRREQ_LEVEL[31]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_HIT[0] TCC_MISS[0] TCC_READ[0] TCC_REQ[0] TCC_HIT[1] TCC_MISS[1] TCC_READ[1] TCC_REQ[1] TCC_HIT[2] TCC_MISS[2] TCC_READ[2] TCC_REQ[2] TCC_HIT[3] TCC_MISS[3] TCC_READ[3] TCC_REQ[3] TCC_HIT[4] TCC_MISS[4] TCC_READ[4] TCC_REQ[4] TCC_HIT[5] TCC_MISS[5] TCC_READ[5] TCC_REQ[5] TCC_HIT[6] TCC_MISS[6] TCC_READ[6] TCC_REQ[6] TCC_HIT[7] TCC_MISS[7] TCC_READ[7] TCC_REQ[7] TCC_HIT[8] TCC_MISS[8] TCC_READ[8] TCC_REQ[8] TCC_HIT[9] TCC_MISS[9] TCC_READ[9] TCC_REQ[9] TCC_HIT[10] TCC_MISS[10] TCC_READ[10] TCC_REQ[10] TCC_HIT[11] TCC_MISS[11] TCC_READ[11] TCC_REQ[11] TCC_HIT[12] TCC_MISS[12] TCC_READ[12] TCC_REQ[12] TCC_HIT[13] TCC_MISS[13] TCC_READ[13] TCC_REQ[13] TCC_HIT[14] TCC_MISS[14] TCC_READ[14] TCC_REQ[14] TCC_HIT[15] TCC_MISS[15] TCC_READ[15] TCC_REQ[15] TCC_HIT[16] TCC_MISS[16] TCC_READ[16] TCC_REQ[16] TCC_HIT[17] TCC_MISS[17] TCC_READ[17] TCC_REQ[17] TCC_HIT[18] TCC_MISS[18] TCC_READ[18] TCC_REQ[18] TCC_HIT[19] TCC_MISS[19] TCC_READ[19] TCC_REQ[19] TCC_HIT[20] TCC_MISS[20] TCC_READ[20] TCC_REQ[20] TCC_HIT[21] TCC_MISS[21] TCC_READ[21] TCC_REQ[21] TCC_HIT[22] TCC_MISS[22] TCC_READ[22] TCC_REQ[22] TCC_HIT[23] TCC_MISS[23] TCC_READ[23] TCC_REQ[23] TCC_HIT[24] TCC_MISS[24] TCC_READ[24] TCC_REQ[24] TCC_HIT[25] TCC_MISS[25] TCC_READ[25] TCC_REQ[25] TCC_HIT[26] TCC_MISS[26] TCC_READ[26] TCC_REQ[26] TCC_HIT[27] TCC_MISS[27] TCC_READ[27] TCC_REQ[27] TCC_HIT[28] TCC_MISS[28] TCC_READ[28] TCC_REQ[28] TCC_HIT[29] TCC_MISS[29] TCC_READ[29] TCC_REQ[29] TCC_HIT[30] TCC_MISS[30] TCC_READ[30] TCC_REQ[30] TCC_HIT[31] TCC_MISS[31] TCC_READ[31] TCC_REQ[31]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_RW_REQ[0] TCC_TOO_MANY_EA_WRREQS_STALL[0] TCC_WRITE[0] TCC_RW_REQ[1] TCC_TOO_MANY_EA_WRREQS_STALL[1] TCC_WRITE[1] TCC_RW_REQ[2] TCC_TOO_MANY_EA_WRREQS_STALL[2] TCC_WRITE[2] TCC_RW_REQ[3] TCC_TOO_MANY_EA_WRREQS_STALL[3] TCC_WRITE[3] TCC_RW_REQ[4] TCC_TOO_MANY_EA_WRREQS_STALL[4] TCC_WRITE[4] TCC_RW_REQ[5] TCC_TOO_MANY_EA_WRREQS_STALL[5] TCC_WRITE[5] TCC_RW_REQ[6] TCC_TOO_MANY_EA_WRREQS_STALL[6] TCC_WRITE[6] TCC_RW_REQ[7] TCC_TOO_MANY_EA_WRREQS_STALL[7] TCC_WRITE[7] TCC_RW_REQ[8] TCC_TOO_MANY_EA_WRREQS_STALL[8] TCC_WRITE[8] TCC_RW_REQ[9] TCC_TOO_MANY_EA_WRREQS_STALL[9] TCC_WRITE[9] TCC_RW_REQ[10] TCC_TOO_MANY_EA_WRREQS_STALL[10] TCC_WRITE[10] TCC_RW_REQ[11] TCC_TOO_MANY_EA_WRREQS_STALL[11] TCC_WRITE[11] TCC_RW_REQ[12] TCC_TOO_MANY_EA_WRREQS_STALL[12] TCC_WRITE[12] TCC_RW_REQ[13] TCC_TOO_MANY_EA_WRREQS_STALL[13] TCC_WRITE[13] TCC_RW_REQ[14] TCC_TOO_MANY_EA_WRREQS_STALL[14] TCC_WRITE[14] TCC_RW_REQ[15] TCC_TOO_MANY_EA_WRREQS_STALL[15] TCC_WRITE[15] TCC_RW_REQ[16] TCC_TOO_MANY_EA_WRREQS_STALL[16] TCC_WRITE[16] TCC_RW_REQ[17] TCC_TOO_MANY_EA_WRREQS_STALL[17] TCC_WRITE[17] TCC_RW_REQ[18] TCC_TOO_MANY_EA_WRREQS_STALL[18] TCC_WRITE[18] TCC_RW_REQ[19] TCC_TOO_MANY_EA_WRREQS_STALL[19] TCC_WRITE[19] TCC_RW_REQ[20] TCC_TOO_MANY_EA_WRREQS_STALL[20] TCC_WRITE[20] TCC_RW_REQ[21] TCC_TOO_MANY_EA_WRREQS_STALL[21] TCC_WRITE[21] TCC_RW_REQ[22] TCC_TOO_MANY_EA_WRREQS_STALL[22] TCC_WRITE[22] TCC_RW_REQ[23] TCC_TOO_MANY_EA_WRREQS_STALL[23] TCC_WRITE[23] TCC_RW_REQ[24] TCC_TOO_MANY_EA_WRREQS_STALL[24] TCC_WRITE[24] TCC_RW_REQ[25] TCC_TOO_MANY_EA_WRREQS_STALL[25] TCC_WRITE[25] TCC_RW_REQ[26] TCC_TOO_MANY_EA_WRREQS_STALL[26] TCC_WRITE[26] TCC_RW_REQ[27] TCC_TOO_MANY_EA_WRREQS_STALL[27] TCC_WRITE[27] TCC_RW_REQ[28] TCC_TOO_MANY_EA_WRREQS_STALL[28] TCC_WRITE[28] TCC_RW_REQ[29] TCC_TOO_MANY_EA_WRREQS_STALL[29] TCC_WRITE[29] TCC_RW_REQ[30] TCC_TOO_MANY_EA_WRREQS_STALL[30] TCC_WRITE[30] TCC_RW_REQ[31] TCC_TOO_MANY_EA_WRREQS_STALL[31] TCC_WRITE[31]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VALU_TRANS_F16 SQ_INSTS_VALU_ADD_F32 SQ_INSTS_VALU_MUL_F32 SQ_INSTS_VALU_FMA_F32 SQ_INSTS_VALU_TRANS_F32 SQ_INSTS_VALU_ADD_F64 SQ_INSTS_VALU_MUL_F64 SQ_INSTS_VALU_FMA_F64 TCP_VOLATILE_sum TCP_TOTAL_ACCESSES_sum TCP_TOTAL_READ_sum TCP_TOTAL_WRITE_sum TA_BUFFER_ATOMIC_WAVEFRONTS_sum TA_BUFFER_TOTAL_CYCLES_sum TD_ATOMIC_WAVEFRONT_sum TD_STORE_WAVEFRONT_sum SPI_RA_REQ_NO_ALLOC SPI_RA_REQ_NO_ALLOC_CSN CPC_CPC_STAT_STALL CPC_UTCL1_STALL_ON_TRANSLATION CPF_CPF_STAT_IDLE CPF_CPF_TCIU_IDLE TCC_REQ_sum TCC_STREAMING_REQ_sum TCC_HIT_sum TCC_MISS_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VALU_TRANS_F64 SQ_INSTS_VALU_INT32 SQ_INSTS_VALU_INT64 SQ_INSTS_SMEM SQ_INSTS_FLAT SQ_INSTS_LDS SQ_INSTS_GDS SQ_INSTS_EXP_GDS TCP_TOTAL_ATOMIC_WITH_RET_sum TCP_TOTAL_ATOMIC_WITHOUT_RET_sum TCP_TOTAL_WRITEBACK_INVALIDATES_sum TCP_TOTAL_CACHE_ACCESSES_sum TA_BUFFER_COALESCED_READ_CYCLES_sum TA_BUFFER_COALESCED_WRITE_CYCLES_sum TD_COALESCABLE_WAVEFRONT_sum SPI_RA_RES_STALL_CSN SPI_RA_TMP_STALL_CSN CPC_CPC_UTCL2IU_BUSY CPC_CPC_UTCL2IU_IDLE CPF_CMP_UTCL1_STALL_ON_TRANSLATION TCC_READ_sum TCC_WRITE_sum TCC_ATOMIC_sum TCC_WRITEBACK_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_BRANCH SQ_INSTS_SENDMSG SQ_WAIT_ANY SQ_WAIT_INST_ANY SQ_ACTIVE_INST_ANY SQ_ACTIVE_INST_VMEM SQ_ACTIVE_INST_LDS SQ_ACTIVE_INST_VALU TCP_UTCL1_TRANSLATION_MISS_sum TCP_UTCL1_TRANSLATION_HIT_sum TCP_UTCL1_PERMISSION_MISS_sum TCP_UTCL1_REQUEST_sum TA_ADDR_STALLED_BY_TC_CYCLES_sum TA_TOTAL_WAVEFRONTS_sum SPI_RA_WAVE_SIMD_FULL_CSN SPI_RA_VGPR_SIMD_FULL_CSN CPC_CPC_UTCL2IU_STALL CPC_ME1_BUSY_FOR_PACKET_DECODE TCC_EA_WRREQ_sum TCC_EA_WRREQ_64B_sum TCC_EA_WR_UNCACHED_32B_sum TCC_EA_WRREQ_DRAM_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_ACTIVE_INST_SCA SQ_ACTIVE_INST_EXP_GDS SQ_ACTIVE_INST_MISC SQ_ACTIVE_INST_FLAT SQ_INST_CYCLES_VMEM_WR SQ_INST_CYCLES_VMEM_RD SQ_INST_CYCLES_SMEM SQ_INST_CYCLES_SALU TCP_TCP_LATENCY_sum TCP_TCC_READ_REQ_LATENCY_sum TCP_TCC_WRITE_REQ_LATENCY_sum TCP_TCC_READ_REQ_sum TA_ADDR_STALLED_BY_TD_CYCLES_sum TA_DATA_STALLED_BY_TC_CYCLES_sum SPI_RA_SGPR_SIMD_FULL_CSN SPI_RA_LDS_CU_FULL_CSN CPC_ME1_DC0_SPI_BUSY TCC_EA_WRREQ_STALL_sum TCC_EA_RDREQ_sum TCC_EA_RDREQ_32B_sum TCC_EA_RD_UNCACHED_32B_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_THREAD_CYCLES_VALU SQ_IFETCH SQ_LDS_BANK_CONFLICT SQ_LDS_ADDR_CONFLICT SQ_LDS_UNALIGNED_STALL SQ_WAVES_EQ_64 SQ_WAVES_LT_64 SQ_WAVES_LT_48 TCP_TCC_WRITE_REQ_sum TCP_TCC_ATOMIC_WITH_RET_REQ_sum TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum TCP_TCC_NC_READ_REQ_sum TA_FLAT_WAVEFRONTS_sum TA_FLAT_READ_WAVEFRONTS_sum SPI_RA_BAR_CU_FULL_CSN SPI_RA_TGLIM_CU_FULL_CSN TCC_EA_RDREQ_DRAM_sum TCC_TAG_STALL_sum TCC_NORMAL_WRITEBACK_sum TCC_ALL_TC_OP_WB_WRITEBACK_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_WAVES_LT_32 SQ_WAVES_LT_16 SQ_ITEMS SQ_LDS_MEM_VIOLATIONS SQ_LDS_ATOMIC_RETURN SQ_LDS_IDX_ACTIVE SQ_WAVES_RESTORED SQ_WAVES_SAVED TCP_TCC_NC_WRITE_REQ_sum TCP_TCC_NC_ATOMIC_REQ_sum TCP_TCC_UC_READ_REQ_sum TCP_TCC_UC_WRITE_REQ_sum TA_FLAT_WRITE_WAVEFRONTS_sum TA_FLAT_ATOMIC_WAVEFRONTS_sum SPI_RA_WVLIM_STALL_CSN SPI_SWC_CSC_WR TCC_NORMAL_EVICT_sum TCC_ALL_TC_OP_INV_EVICT_sum TCC_TOO_MANY_EA_WRREQS_STALL_sum TCC_EA_ATOMIC_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_SMEM_NORM SQ_INSTS_MFMA SQ_INSTS_VALU_MFMA_I8 SQ_INSTS_VALU_MFMA_F16 SQ_INSTS_VALU_MFMA_BF16 SQ_INSTS_VALU_MFMA_F32 SQ_INSTS_VALU_MFMA_F64 SQ_VALU_MFMA_BUSY_CYCLES TCP_TCC_UC_ATOMIC_REQ_sum TCP_TCC_CC_READ_REQ_sum TCP_TCC_CC_WRITE_REQ_sum TCP_TCC_CC_ATOMIC_REQ_sum SPI_VWC_CSC_WR SPI_RA_BULKY_CU_FULL_CSN TCC_EA_RDREQ_LEVEL_sum TCC_EA_WRREQ_LEVEL_sum TCC_EA_ATOMIC_LEVEL_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_FLAT_LDS_ONLY SQ_INSTS_VALU_MFMA_MOPS_I8 SQ_INSTS_VALU_MFMA_MOPS_F16 SQ_INSTS_VALU_MFMA_MOPS_BF16 SQ_INSTS_VALU_MFMA_MOPS_F32 SQ_INSTS_VALU_MFMA_MOPS_F64 SQC_TC_INST_REQ SQC_TC_DATA_READ_REQ TCP_TCC_RW_READ_REQ_sum TCP_TCC_RW_WRITE_REQ_sum TCP_TCC_RW_ATOMIC_REQ_sum TCP_PENDING_STALL_CYCLES_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID
+0,"vecCopy(double*, double*, double*, int, int)",2
+1,"vecCopy(double*, double*, double*, int, int)",2
+2,"vecCopy(double*, double*, double*, int, int)",2
@@ -0,0 +1,5 @@
+device,HBMBw,HBMBwLow,hbmBwHigh,L2Bw,L2BwLow,L2BwHigh,L1Bw,L1BwLow,L1BwHigh,LDSBw,LDSBwLow,LDSBwHigh,FP32Flops,FP32FlopsLow,FP32FlopsHigh,FP64Flops,FP64FlopsLow,FP64FlopsHigh,MFMABF16Flops,MFMABF16FlopsLow,MFMABF16FlopsHigh,MFMAF16Flops,MFMAF16FlopsLow,MFMAF16FlopsHigh,MFMAF32Flops,MFMAF32FlopsLow,MFMAF32FlopsHigh,MFMAF64Flops,MFMAF64FlopsLow,MFMAF64FlopsHigh,MFMAI8Ops,MFMAFI8OpsLow,MFMAI8OpsHigh
+0,1389.2573,1388.7148,1389.7998,5028.8901,5025.7681,5032.0122,9236.2383,9235.5488,9236.9277,17609.27,17606.766,17611.773,21018.107,20957.701,21078.514,20440.506,20439.146,20441.865,170492.3,170487.67,170496.92,164888.08,164883.73,164892.42,41448.984,41448.043,41449.926,41427.156,41426.016,41428.297,166462.45,165973.48,166951.42
+1,1388.6865,1388.1116,1389.2615,5043.5737,5041.3315,5045.8159,9269.6289,9269.0537,9270.2041,17701.557,17696.309,17706.805,20996.717,20800.053,21193.381,20510.537,20509.943,20511.131,170937.3,170933.94,170940.66,165438.28,165434.06,165442.5,41577.234,41576.676,41577.793,41548.996,41546.246,41551.746,167192.28,167189.86,167194.7
+2,1388.6455,1388.0868,1389.2042,5031.8101,5029.8232,5033.7969,9247.6719,9247.1436,9248.2002,17836.916,17827.848,17845.984,21070.893,21070.477,21071.309,20462.385,20461.734,20463.035,170666.73,170661.8,170671.67,165136.25,165131.95,165140.55,41499.688,41498.645,41500.73,41479.488,41478.453,41480.523,166663.62,166079.67,167247.58
+3,1388.3237,1387.6769,1388.9706,5042.8608,5041.9971,5043.7246,9237.6855,9237.2197,9238.1514,17895.852,17888.172,17903.531,21056.562,21056.182,21056.943,20440.436,20439.594,20441.277,170615.14,170611.98,170618.3,164958.52,164953.75,164963.28,41457.891,41457.164,41458.617,41306.961,41053.715,41560.207,166802.38,166799.5,166805.25
@@ -0,0 +1,2 @@
+workload_name,command,host_name,host_cpu,sbios,host_distro,host_kernel,host_rocmver,date,gpu_soc,vbios,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,totalL2Banks,LDSBanks,name,numSQC,numPipes,hbmBW,compute_partition,memory_partition,ip_blocks
+app_1,./sample/vcopy -n 1048576 -b 256 -i 3,t004-004.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,5.7.1-98,Fri Feb 16 14:36:58 2024 (CST),gfx90a,113-D67301-059,8,104,4,64,32,1024,16,8192,1700,1200,1700,1200,32,32,32,MI200,56,4,1200,,,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
@@ -0,0 +1,4 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int)",2,0,0,2693421,2693421,1048576,256,0,0,8,0,16,64,0x0,0x7f7cf8518ec0,2423816758910852,2423816758936208,2423816758956208,2423816758969663
+1,"vecCopy(double*, double*, double*, int, int)",2,0,2,2693421,2693421,1048576,256,0,0,8,0,16,64,0x0,0x7f7cf8518ec0,2423816758967389,2423816758974928,2423816758990448,2423816759061657
+2,"vecCopy(double*, double*, double*, int, int)",2,0,4,2693421,2693421,1048576,256,0,0,8,0,16,64,0x0,0x7f7cf8518ec0,2423816759001022,2423816759063728,2423816759080688,2423816759081835