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P4 to Git Change 1448201 by smekhano@stas-nova-hsa on 2017/08/16 19:58:09

Browse Source 
SWDEV-121551 - Complib: fix ocltst ACLApi regression after CL 1448141 (HSAIL part)

Affected files ...

... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/libUtils.cpp#25 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_amdil.h#47 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_amdil64.h#43 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_hsail.h#46 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_hsail64.h#41 edit


[ROCm/clr commit: 6622762df5]
This commit is contained in:
foreman
2017-08-16 20:11:30 -04:00
parent 4df5368e3b
commit ccf86da3c9
5 changed files with 10 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp
+2
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@@ -566,7 +566,9 @@ int getIsaType(const aclTargetInfo *target)
case VI_ICELAND_M_A0: return 800;
case VI_FIJI_P_A0:
case VI_BAFFIN_M_A0:
case VI_BAFFIN_M_A1:
case VI_ELLESMERE_P_A0:
case VI_ELLESMERE_P_A1:
case VI_LEXA_V_A0:
case VI_POLARIS22_P_A0:
#if defined(BUILD_HSA_TARGET)
projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_amdil.h
+2 -2
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@@ -98,9 +98,9 @@ static const TargetMapping AMDILTargetMapping_0_8[] = {
{ "CI", "Bonaire", "bonaire", amd::GPU_Library_CI, CI_BONAIRE_M_A1, F_SI_BASE, true, true, FAMILY_CI },
{ "VI", "Fiji", "fiji", amd::GPU_Library_CI, VI_FIJI_P_A0, F_SI_BASE, true, true, FAMILY_VI },
{ "CZ", "Stoney", "stoney", amd::GPU_Library_CI, STONEY_A0, F_SI_BASE, true, true, FAMILY_CZ },
{ "VI", "Baffin", "baffin", amd::GPU_Library_CI, VI_BAFFIN_M_A0, F_SI_BASE, true, true, FAMILY_VI },
{ "VI", "Baffin", "baffin", amd::GPU_Library_CI, VI_BAFFIN_M_A0, F_SI_BASE, true, false, FAMILY_VI },
{ "VI", "Baffin", "baffin", amd::GPU_Library_CI, VI_BAFFIN_M_A1, F_SI_BASE, true, true, FAMILY_VI },
{ "VI", "Ellesmere", "ellesmere", amd::GPU_Library_CI, VI_ELLESMERE_P_A0, F_SI_BASE, true, true, FAMILY_VI },
{ "VI", "Ellesmere", "ellesmere", amd::GPU_Library_CI, VI_ELLESMERE_P_A0, F_SI_BASE, true, false, FAMILY_VI },
{ "VI", "Ellesmere", "ellesmere", amd::GPU_Library_CI, VI_ELLESMERE_P_A1, F_SI_BASE, true, true, FAMILY_VI },
#ifndef BRAHMA
{ "VI", "gfx804", "gfx804", amd::GPU_Library_CI, VI_LEXA_V_A0, F_SI_BASE, true, true, FAMILY_VI },
projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_amdil64.h
+2 -2
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@@ -44,9 +44,9 @@ static const TargetMapping AMDIL64TargetMapping_0_8[] = {
{ "CI", "Bonaire", "bonaire", amd::GPU64_Library_CI, CI_BONAIRE_M_A0, F_SI_64BIT_PTR, true, true, FAMILY_CI },
{ "VI", "Fiji", "fiji", amd::GPU64_Library_CI, VI_FIJI_P_A0, F_SI_64BIT_PTR, true, true, FAMILY_VI },
{ "CZ", "Stoney", "stoney", amd::GPU64_Library_CI, STONEY_A0, F_SI_64BIT_PTR, true, true, FAMILY_CZ },
{ "VI", "Baffin", "baffin", amd::GPU64_Library_CI, VI_BAFFIN_M_A0, F_SI_64BIT_PTR, true, true, FAMILY_VI },
{ "VI", "Baffin", "baffin", amd::GPU64_Library_CI, VI_BAFFIN_M_A0, F_SI_64BIT_PTR, true, false, FAMILY_VI },
{ "VI", "Baffin", "baffin", amd::GPU64_Library_CI, VI_BAFFIN_M_A1, F_SI_64BIT_PTR, true, true, FAMILY_VI },
{ "VI", "Ellesmere", "ellesmere", amd::GPU64_Library_CI, VI_ELLESMERE_P_A0, F_SI_64BIT_PTR, true, true, FAMILY_VI },
{ "VI", "Ellesmere", "ellesmere", amd::GPU64_Library_CI, VI_ELLESMERE_P_A0, F_SI_64BIT_PTR, true, false, FAMILY_VI },
{ "VI", "Ellesmere", "ellesmere", amd::GPU64_Library_CI, VI_ELLESMERE_P_A1, F_SI_64BIT_PTR, true, true, FAMILY_VI },
#ifndef BRAHMA
{ "VI", "gfx804", "gfx804", amd::GPU64_Library_CI, VI_LEXA_V_A0, F_SI_64BIT_PTR, true, true, FAMILY_VI },
projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h
+2 -2
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@@ -29,9 +29,9 @@ static const TargetMapping HSAILTargetMapping_0_8[] = {
{ "CZ", "Carrizo", "GFX8", amd::GPU_Library_HSAIL, CARRIZO_A0, F_VI_BASE, true, true, FAMILY_CZ },
{ "VI", "Fiji", "GFX8", amd::GPU_Library_HSAIL, VI_FIJI_P_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "CZ", "Stoney", "GFX8", amd::GPU_Library_HSAIL, STONEY_A0, F_VI_BASE, true, true, FAMILY_CZ },
{ "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A0, F_VI_BASE, true, false, FAMILY_VI },
{ "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A1, F_VI_BASE, true, true, FAMILY_VI },
{ "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, F_VI_BASE, true, false, FAMILY_VI },
{ "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A1, F_VI_BASE, true, true, FAMILY_VI },
#ifndef BRAHMA
{ "AI", "gfx900", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, true, FAMILY_AI },
projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h
+2 -2
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@@ -28,9 +28,9 @@ static const TargetMapping HSAIL64TargetMapping_0_8[] = {
{ "CZ", "Carrizo", "GFX8", amd::GPU_Library_HSAIL, CARRIZO_A0, F_VI_BASE, true, true, FAMILY_CZ },
{ "VI", "Fiji", "GFX8", amd::GPU_Library_HSAIL, VI_FIJI_P_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "CZ", "Stoney", "GFX8", amd::GPU_Library_HSAIL, STONEY_A0, F_VI_BASE, true, true, FAMILY_CZ },
{ "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A0, F_VI_BASE, true, false, FAMILY_VI },
{ "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A1, F_VI_BASE, true, true, FAMILY_VI },
{ "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, F_VI_BASE, true, false, FAMILY_VI },
{ "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A1, F_VI_BASE, true, true, FAMILY_VI },
#ifndef BRAHMA
{ "AI", "gfx900", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, true, FAMILY_AI },