P4 to Git Change 1393335 by gandryey@gera-w8 on 2017/03/31 13:43:08
SWDEV-79445 - OCL generic changes and code clean-up
- Implement the right fix for SWDEV-115408 and revert CL#1392885. PAL fence reset should occur after WaitForFences(), since there is a possible delay between TS event and OS event
Affected files ...
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palvirtual.cpp#45 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palvirtual.hpp#19 edit
... //depot/stg/opencl/drivers/opencl/runtime/utils/flags.hpp#267 edit
[ROCm/clr commit: a708eb45ce]
Este commit está contenido en:
@@ -246,6 +246,12 @@ VirtualGPU::Queue::flush()
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}
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}
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// Reset the fence. PAL will reset OS event
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if (Pal::Result::Success != iDev_->ResetFences(1, &iCmdFences_[cmdBufIdSlot_])) {
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LogError("PAL failed to reset a fence!");
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return false;
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}
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Pal::SubmitInfo submitInfo = {};
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submitInfo.cmdBufferCount = 1;
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submitInfo.ppCmdBuffers = &iCmdBuffs_[cmdBufIdSlot_];
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@@ -279,7 +285,8 @@ VirtualGPU::Queue::flush()
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cmdBufIdSlot_ = cmdBufIdCurrent_ % MaxCmdBuffers;
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// Make sure the slot isn't busy
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waifForFence(cmdBufIdSlot_);
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constexpr bool IbReuse = true;
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waifForFence(cmdBufIdSlot_, IbReuse);
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// Progress retired TS
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if ((cmdBufIdCurrent_ > MaxCmdBuffers) &&
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@@ -287,12 +294,6 @@ VirtualGPU::Queue::flush()
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cmbBufIdRetired_ = cmdBufIdCurrent_ - MaxCmdBuffers;
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}
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if (Pal::Result::Success !=
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iDev_->ResetFences(1, &iCmdFences_[cmdBufIdSlot_])) {
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LogError("PAL failed to reset a fence!");
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return false;
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}
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// Reset command buffer, so CB chunks could be reused
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if (Pal::Result::Success != iCmdBuffs_[cmdBufIdSlot_]->Reset(nullptr, false)) {
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LogError("PAL failed CB reset!");
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@@ -90,7 +90,8 @@ public:
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iDev_->RemoveGpuMemoryReferences(1, &iMem, NULL);
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}
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bool waifForFence(uint cbId) const
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// ibReuse forces event wait without polling, to make sure event occured
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bool waifForFence(uint cbId, bool ibReuse = false) const
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{
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Pal::Result result = Pal::Result::Success;
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uint64_t start = amd::Os::timeNanos();
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@@ -100,20 +101,12 @@ public:
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break;
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}
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uint64_t end = amd::Os::timeNanos();
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if ((end - start) < PollIntervalInNsec) {
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if (!ibReuse && ((end - start) < PollIntervalInNsec)) {
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amd::Os::yield();
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continue;
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}
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result = iDev_->WaitForFences(1, &iCmdFences_[cbId], true, WaitTimeoutInNsec);
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if (Pal::Result::Success == result) {
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// Note: This is a workaround for a timing sensitive issue when OS event
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// succeeded without the actual GPU operation completion.
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// The issue occurs under heavy GPU load with more than 1 OCL app running and
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// HWS enabled under Win10
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while (GPU_PAL_FENCE_VALIDATION &&
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(Pal::Result::Success != iCmdFences_[cbId]->GetStatus())) {
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amd::Os::yield();
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}
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break;
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}
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else if ((Pal::Result::NotReady == result) ||
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@@ -181,8 +181,6 @@ release(uint, GPU_WAVES_PER_SIMD, 0, \
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"Force the number of waves per SIMD (1-10)") \
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release(bool, GPU_WAVE_LIMIT_ENABLE, false, \
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"1 = Enable adaptive wave limiter") \
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release(bool, GPU_PAL_FENCE_VALIDATION, true, \
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"1 = Enables PAL fence validation with TS") \
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release_on_stg(uint, GPU_WAVE_LIMIT_CU_PER_SH, 0, \
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"Assume the number of CU per SH for wave limiter") \
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release_on_stg(uint, GPU_WAVE_LIMIT_MAX_WAVE, 10, \
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