AI/rocm-systems
2
0
Форкнуть 0
Код Задачи Запросы на слияние Действия Пакеты Проекты Релизы Вики Активность
76 333 коммитов 3 Ветки 0 Теги
develop
Граф коммитов

23 Коммитов

Автор SHA1 Сообщение Дата
Fábio Mestre 447beeb00b Replace usages of __ockl_gws_init with __builtin_amdgcn_ds_gws_init (#2235) 2025-12-15 16:56:14 +01:00
Danylo Lytovchenko f7338717ae SWDEV-470698 - fix formatting, add format check workflow (#657) 2025-08-20 19:58:06 +05:30
Andryeyev, German a9df586812 SWDEV-459758 - Pass workgroup size explicitly (#185) 
It's easier for compiler to move explicit kernel arguments into user SGPRs

[ROCm/clr commit: 3fd7650fe3]
 2025-04-15 15:22:15 -04:00
Sourabh Betigeri 7261404002 SWDEV-440866 - [hip-roclr] Adds support to batch memory operations APIs 
Change-Id: I5ac63a6626af8c2b4ac382c52dfe1aaf0b3716b8


[ROCm/clr commit: 03dbcd8ca7]
 2024-12-12 19:29:24 -05:00
Sourabh Betigeri 1712acdd2e Revert "SWDEV-440866 - [hip-roclr] Adds support to batch memory operations APIs" 
This reverts commit ab0ff9163d.

Reason for revert: hipInfo fails on windows. Updating llvm amd-mainline-closed

Change-Id: I57e1fa1945188b0bc0a799c4f3d540f2b7713003


[ROCm/clr commit: 2ca644cf22]
 2024-12-02 16:46:12 -05:00
Sourabh Betigeri ab0ff9163d SWDEV-440866 - [hip-roclr] Adds support to batch memory operations APIs 
Change-Id: I449ffca44bbb04d13348d112e896d603c70fd485


[ROCm/clr commit: bd5d8e9baf]
 2024-11-30 17:54:32 -05:00
Ioannis Assiouras 407d1346f2 SWDEV-463865 - changed device,roc and pal namespaces to be nested under amd 
Change-Id: Icad342843c039c634e249a13a7aa31400730b1dd


[ROCm/clr commit: 775dc204aa]
 2024-06-07 12:23:06 -04:00
German Andryeyev 27dec1c62d SWDEV-455254 - Reduce blit kernels signature 
Remove offset from blit kernels, since it can be applied in setup.

Change-Id: I06b585068d68a0ee8e125ddf46a36fccb372f30d


[ROCm/clr commit: 7de7da4016]
 2024-04-12 14:45:55 -04:00
Ajay e8a077dc68 SWDEV-347670 - StreamWait and StreamWrite on Windows 
__amd_streamOpsWrite blitkernel in device-libs has only 3 args.
so getting rid of the 4th unused arg (sizeBytes)

Change-Id: I81cc1107f8b424bf58558c93a2495a1b878aef91


[ROCm/clr commit: e643406caa]
 2024-02-26 22:45:10 -05:00
German Andryeyev eec1e978f0 SWDEV-434298 - Change copy buffer kernel 
The new copy kernel can limit the number of launched workgoups.
It can copy in chunks of 16 bytes or 4 bytes.
Workgoup size is increased to 512 or 1024

Change-Id: Ic3fefa2d5bda6afebd1acc4d41ad310b138af6df


[ROCm/clr commit: ed4e1fec98]
 2023-11-28 16:56:30 -05:00
German Andryeyev e390ec044f SWDEV-432174 - Change the fillBuffer kernel 
- Add the new fillBuffer kernel, which allows to launch a limited
number of workgroups for memory fill operation
- Switch fill memory to 16 bytes write by default
- Allow to limit the workgroups with DEBUG_CLR_LIMIT_BLIT_WG

Change-Id: Ibad1822f2d42b2fc71bcfc1917c31409c0623e8e


[ROCm/clr commit: f1dc81f427]
 2023-11-16 14:25:55 -04:00
kjayapra-amd 96580585c3 SWDEV-419688 - Do not run GWS init kernel for targets > gfx12 and MI300. 
Change-Id: I8e7441268978be71ab8a5a33e7f8bcf69660e500
(cherry picked from commit 36d37ef614909c0f215512aac0c133408d787080)


[ROCm/clr commit: 6a8bc3c718]
 2023-10-05 14:57:56 -04:00
Alex Xie a7418845f8 SWDEV-409299 - Vega clinfo is not working 
Change-Id: Ia48bc6f130bd102dff210b105de6f9c02ebbe012


[ROCm/clr commit: 7912f3af89]
 2023-07-10 09:53:50 -04:00
ajay a8d5879f26 SWDEV-406687 - combining rocblitcl and palblitcl blit kernel defs 
Change-Id: Ia312d73584a03491e8d574f424295b64df6de174


[ROCm/clr commit: d6946ffcbc]
 2023-06-23 18:38:36 -04:00
kjayapra-amd 31c0525344 SWDEV-305527 - Changes to handle memset blit kernel that takes width, height and depth. This also fixes SWDEV-317261. 
Change-Id: Ic85f63a95d9d8f48884fc8c7fd95cbb496dfbbca


[ROCm/clr commit: 7fb80a027a]
 2022-03-31 09:02:33 -04:00
Julia Jiang e3f6db3d64 SWDEV-308644 - update blit kernel setup in rocm 
Change-Id: Iaa9ff97b3ed7d379189c359696be932a83cf203c


[ROCm/clr commit: ef3d6f7b28]
 2021-11-15 13:28:07 -05:00
kjayapra-amd cfb15c6c5d SWDEV-294420 - Ignore Image blit kernels if image instructions are not supported. 
Change-Id: I145172672b0b032aa722649b0c4ca9267e3e5c85


[ROCm/clr commit: 7413b7f79b]
 2021-10-05 18:12:44 -04:00
Sourabh 936e0836a8 SWDEV-292525 - [vdi] Path to streamOps shaders 
Implementation to use a blit kernel to perform
a hipStreamWait/write instead of an AQL packet.

Change-Id: I462671ed5cec37144dfe97ff66439249196117c1


[ROCm/clr commit: cbb8d82bdb]
 2021-09-27 13:59:35 -04:00
Saleel Kudchadker 36ec8c8871 SWDEV-297448 - Add 64bit and 16bit write support 
For the fillBuffer shader, if there are two 32bit writes to a MMIO
register, it can get dropped. It has to be a single 64bit write.
Add optimization to fillBuffer to write 64bit and 16bit writes.

Change-Id: I3aa78e027898f8ae01e9c8f09004615673720c2b


[ROCm/clr commit: 21ba34d0fe]
 2021-09-08 12:30:04 -04:00
agunashe 49f0546637 SWDEV-293742 - Update copyright end year VDI repo 
Change-Id: I69d2fea4a7a43adf96ccea794270e4af991c5261


[ROCm/clr commit: d96481fb36]
 2021-08-22 23:56:07 -07:00
Anusha Godavarthy Surya de10e7e1e6 SWDEV-244600 - HIP BLIT code object needs to have reserved symbol name 
Change-Id: I8401fea5eab71c0f7414eec0666066d9553a6622


[ROCm/clr commit: 093f7fa3ca]
 2020-08-06 01:14:06 -04:00
Laurent Morichetti e284923583 Update copyright info 
Change-Id: Ia4f9ff0f5f873b4223a8cca154188bb0d2f1abba


[ROCm/clr commit: b4c6143a2f]
 2020-02-04 09:26:14 -08:00
Laurent Morichetti 011f3e945b Merge branch 'origin/pghafari/vdi-prototype' into lmoriche/amd-master 
Change-Id: Id3b833d405596735becb3346f3b08c6da57033fe


[ROCm/clr commit: 20c7173849]
 2020-01-30 20:12:13 -08:00