32 Коммитов

Автор SHA1 Сообщение Дата
Danylo Lytovchenko 2ff2316227 Adjust clang format to the new versions, revert broken macro layout (#714) 2025-08-22 17:23:22 +02:00
Danylo Lytovchenko f7338717ae SWDEV-470698 - fix formatting, add format check workflow (#657) 2025-08-20 19:58:06 +05:30
Andryeyev, German a9df586812 SWDEV-459758 - Pass workgroup size explicitly (#185)
It's easier for compiler to move explicit kernel arguments into user SGPRs

[ROCm/clr commit: 3fd7650fe3]
2025-04-15 15:22:15 -04:00
agunashe 52a1f5dbf7 SWDEV-507967 - Deprecate gfx9, gfx8, gfx7 on Windows
PAL_CLIENT_INTERFACE_MAJOR_VERSION from 872 --> 910

Change-Id: I03dfa2924ccdae4c2f13f09d5f34ee58298e1343


[ROCm/clr commit: ea804e16f8]
2025-02-17 02:59:41 -05:00
kjayapra-amd f19260d568 SWDEV-480772 - Remove name variable from amd::Monitor class.
Change-Id: Ie2a4fa44f485786227230f8a892e090e718aa30e


[ROCm/clr commit: 12a39fbf22]
2024-09-19 11:55:01 -04:00
Ioannis Assiouras 407d1346f2 SWDEV-463865 - changed device,roc and pal namespaces to be nested under amd
Change-Id: Icad342843c039c634e249a13a7aa31400730b1dd


[ROCm/clr commit: 775dc204aa]
2024-06-07 12:23:06 -04:00
kjayapra-amd 27bc1632f1 SWDEV-417091 - Disable GWS Init for PAL/Windows side.
Change-Id: Ib6295f063daa835c1f33f21f50c083241a9026ff


[ROCm/clr commit: 931431fc38]
2024-05-28 06:31:10 +00:00
German Andryeyev 27dec1c62d SWDEV-455254 - Reduce blit kernels signature
Remove offset from blit kernels, since it can be applied in setup.

Change-Id: I06b585068d68a0ee8e125ddf46a36fccb372f30d


[ROCm/clr commit: 7de7da4016]
2024-04-12 14:45:55 -04:00
Ajay e8a077dc68 SWDEV-347670 - StreamWait and StreamWrite on Windows
__amd_streamOpsWrite blitkernel in device-libs has only 3 args.
so getting rid of the 4th unused arg (sizeBytes)

Change-Id: I81cc1107f8b424bf58558c93a2495a1b878aef91


[ROCm/clr commit: e643406caa]
2024-02-26 22:45:10 -05:00
German fe71f14732 SWDEV-434241 - Replace size_t with uint64_t
The kernel accepts uint64_t, but with 32bit OCL build size_t was 32 bit

Change-Id: I6fe37d2e5e69c7bd62d7b1bd4cace758758b3482


[ROCm/clr commit: b3171d08e6]
2023-12-08 16:56:29 -05:00
German Andryeyev d60fabacbe SWDEV-434298 - Add destination offset
The end pointer in copy buffer requires destination offset

Change-Id: I01f2967144f741761fd2ce3244fd8d04564d986f


[ROCm/clr commit: 44761fe89b]
2023-11-29 16:33:29 -05:00
German Andryeyev eec1e978f0 SWDEV-434298 - Change copy buffer kernel
The new copy kernel can limit the number of launched workgoups.
It can copy in chunks of 16 bytes or 4 bytes.
Workgoup size is increased to 512 or 1024

Change-Id: Ic3fefa2d5bda6afebd1acc4d41ad310b138af6df


[ROCm/clr commit: ed4e1fec98]
2023-11-28 16:56:30 -05:00
German Andryeyev e390ec044f SWDEV-432174 - Change the fillBuffer kernel
- Add the new fillBuffer kernel, which allows to launch a limited
number of workgroups for memory fill operation
- Switch fill memory to 16 bytes write by default
- Allow to limit the workgroups with DEBUG_CLR_LIMIT_BLIT_WG

Change-Id: Ibad1822f2d42b2fc71bcfc1917c31409c0623e8e


[ROCm/clr commit: f1dc81f427]
2023-11-16 14:25:55 -04:00
victzhan 4312ca9e32 SWDEV-416580 - Add condition when memory has direct access, only use host fill if image is small
Change-Id: I3509c4aa21f6413adad3b46273ec650f5c577ddd


[ROCm/clr commit: cb426df1bd]
2023-08-17 17:23:49 -04:00
taosang2 8d054fa50e SWDEV-366528 – Fix image memory format updating issue
Add dstMemory format updating.
Separate format updating for srcMemory and dstMemory.

Change-Id: I1692b92d417bbd742d562679f218ebf8ca532e92


[ROCm/clr commit: 7624a48de9]
2023-05-08 21:43:42 -04:00
Anusha GodavarthySurya 379781ea65 SWDEV-364576 - initialize device malloc heap state using blit kernel
Change-Id: I5d0172aff7d2c04b322a4d828b8a2b438158b80f


[ROCm/clr commit: 274f2de391]
2023-01-07 06:53:53 +00:00
Ioannis Assiouras 733c8d1d1c SWDEV-369581 - Convey copy API metadata to ROCclr
Change-Id: I569462d6d268700d419510255e201bf7d80d6714


[ROCm/clr commit: 72b45e2a1f]
2022-12-09 00:27:15 -05:00
German c04e2300c8 SWDEV-363074 - Clean-up sync between SDMA and compute
HIP can't rely on the resource tracking, used in OCL and requires different explicit sync.
Make sure ROCCLR syncs compute only when SDMA is used and vise versa.
The new logic will allow to enable CPDMA without unnecessary waits.

Change-Id: Ib9d1788cfd5afa5ea2fec4c96a37d8b9c4d0059d


[ROCm/clr commit: ff6b4db70b]
2022-10-31 10:02:01 -04:00
Ajay e81e8965c9 SWDEV-360944 - palBlit setArgument desc.size_ --> argSize
Fixes AMF tests that were impacted on Windows

Change-Id: I0326e794ec5a34fdec7a5ff4ed79d5bd055997d2


[ROCm/clr commit: a5b550e828]
2022-10-20 12:44:15 -04:00
Ajay c2a7fe7bd6 SWDEV-347670 - GPU StreamWait and StreamWrite support in Windows PAL backend
Change-Id: Ic4881305b6332e217f3d3127dce7e9d9d0a7df11


[ROCm/clr commit: 373a7d1195]
2022-09-15 13:57:40 -04:00
kjayapra-amd 31c0525344 SWDEV-305527 - Changes to handle memset blit kernel that takes width, height and depth. This also fixes SWDEV-317261.
Change-Id: Ic85f63a95d9d8f48884fc8c7fd95cbb496dfbbca


[ROCm/clr commit: 7fb80a027a]
2022-03-31 09:02:33 -04:00
Satyanvesh Dittakavi 85c2cac111 SWDEV-306939 - Fix vdi errors/warnings by CppCheck
Change-Id: I56d910f8363787f1050d5d7e8064ed553c5827fd


[ROCm/clr commit: e20dd61932]
2022-01-12 00:22:16 -05:00
Jason Tang e4db6ef66a SWDEV-306697 - Fix OCLGlobalOffset segfaults
If we don't create the __amd_rocclr_gwsInit kernel, we still want
to create the rest of the image related blit kernels.

Change-Id: I8bc4645f9f9116eeecbb8b22e981ac4d520f3121


[ROCm/clr commit: 55a0cf0b0c]
2021-10-12 15:13:28 -04:00
Saleel Kudchadker 36ec8c8871 SWDEV-297448 - Add 64bit and 16bit write support
For the fillBuffer shader, if there are two 32bit writes to a MMIO
register, it can get dropped. It has to be a single 64bit write.
Add optimization to fillBuffer to write 64bit and 16bit writes.

Change-Id: I3aa78e027898f8ae01e9c8f09004615673720c2b


[ROCm/clr commit: 21ba34d0fe]
2021-09-08 12:30:04 -04:00
agunashe 49f0546637 SWDEV-293742 - Update copyright end year VDI repo
Change-Id: I69d2fea4a7a43adf96ccea794270e4af991c5261


[ROCm/clr commit: d96481fb36]
2021-08-22 23:56:07 -07:00
Sourabh Betigeri 6ec57b845c SWDEV-273265 - Fix to wait on a pending dispatch in PAL.
Change-Id: I431cedfef5d5cb727c35ba8e294528017bfe2088


[ROCm/clr commit: 21ea81d5b9]
2021-04-06 13:13:07 -04:00
Ravi C Akkenapally 6629930067 SWDEV-179105 - Stream Operations: Add support for Wait and Write
Change-Id: Ibffa1d6d573826b64763da280074a77271d66808


[ROCm/clr commit: 0a5f9a3b10]
2021-02-15 17:02:38 -08:00
Tao Sang 44eb207f8d Apply constexpr on global constant varaibles
When HIP_ENABLE_DEFERRED_LOADING=0, many global variables will be
referenced but they are not initialized in that early time. The patch
will use constexpr to initialze global constant varables in compile
time.

Change-Id: I9d538b7abc6a0ce700ec3332b97fc144db5fc1ef


[ROCm/clr commit: fdef6f722f]
2020-07-22 22:14:13 -04:00
Laurent Morichetti 7de346234a Fix build errors for PAL and GSL
The last commit to replace the cl_* types with standard types
failed to correct issues introduced in the PAL and GPU backend.

Change-Id: I926997234dfbe346fc165a7bc4e1b8aabab7bac5


[ROCm/clr commit: b81816f482]
2020-02-13 16:52:32 -05:00
Laurent Morichetti b3297f189d Replace cl_* integral types with standard types.
cl_bool -> bool
cl_int -> int32_t
cl_uint -> uint32_t
cl_long -> int64_t
cl_ulong -> uint64_t
cl_float -> float
cl_double -> double
cl_bitfield -> uint64_t

Change-Id: I840c8993b55f98f5b745d21e27f5f28233647a58


[ROCm/clr commit: d9d9c69399]
2020-02-12 13:16:06 -08:00
Laurent Morichetti e284923583 Update copyright info
Change-Id: Ia4f9ff0f5f873b4223a8cca154188bb0d2f1abba


[ROCm/clr commit: b4c6143a2f]
2020-02-04 09:26:14 -08:00
Laurent Morichetti 011f3e945b Merge branch 'origin/pghafari/vdi-prototype' into lmoriche/amd-master
Change-Id: Id3b833d405596735becb3346f3b08c6da57033fe


[ROCm/clr commit: 20c7173849]
2020-01-30 20:12:13 -08:00