AI/rocm-systems
2
0 Форкнуть 0
Код Задачи Запросы на слияние Действия Пакеты Проекты Релизы Вики Активность
76 333 коммитов 3 Ветки 0 Теги
develop
Граф коммитов
76333 Коммитов
This Branch
This Branch
Все ветки
Автор SHA1 Сообщение Дата
Todd tiantuo Li 8f2b881c3b SWDEV-354868 - return CL_INVALID_VALUE if number of RT CUs is less than its granularity when creating command queue 
Change-Id: I31004e82589c3378dba5541095a1eff763d4579d


[ROCm/clr commit: 6d4e067302]
 2022-12-13 04:59:33 -08:00
Todd tiantuo Li 6d4e067302 SWDEV-354868 - return CL_INVALID_VALUE if number of RT CUs is less than its granularity when creating command queue 
Change-Id: I31004e82589c3378dba5541095a1eff763d4579d
 2022-12-13 04:59:33 -08:00
Ioannis Assiouras f1407eb433 SWDEV-373235 - Fixed segfault when nullptr function is passed to hipKernelNameRef 
Change-Id: If23fbbd19ad92fd0b3fa888dca09e7fe705c0c56


[ROCm/clr commit: 1274f2a54c]
 2022-12-13 07:09:03 -05:00
Ioannis Assiouras 1274f2a54c SWDEV-373235 - Fixed segfault when nullptr function is passed to hipKernelNameRef 
Change-Id: If23fbbd19ad92fd0b3fa888dca09e7fe705c0c56
 2022-12-13 07:09:03 -05:00
Chauncey Hui db15e282f1 SWDEV-2 - Change OpenCL version number from 3543 to 3544 
[ROCm/clr commit: edb515eabf]
 2022-12-13 03:00:08 -05:00
Chauncey Hui edb515eabf SWDEV-2 - Change OpenCL version number from 3543 to 3544 2022-12-13 03:00:08 -05:00
Anusha GodavarthySurya 09b894eeef SWDEV-325711 - Node can be enabled/disabled only for kernel, memcpy and memset nodes 
Change-Id: Id9c19a14655732d61fccee9c3d1ffa0614123468


[ROCm/clr commit: 0fcc5557bd]
 2022-12-13 05:08:38 +00:00
Anusha GodavarthySurya 0fcc5557bd SWDEV-325711 - Node can be enabled/disabled only for kernel, memcpy and memset nodes 
Change-Id: Id9c19a14655732d61fccee9c3d1ffa0614123468
 2022-12-13 05:08:38 +00:00
Anusha GodavarthySurya e1b559e386 SWDEV-372521 - Fix copy of unused kernel attributes 
Change-Id: Ib93f27d68cedac2182ba6dac0c234cc71c2c4229


[ROCm/clr commit: 5bcfb07c85]
 2022-12-13 03:44:10 +00:00
Anusha GodavarthySurya 5bcfb07c85 SWDEV-372521 - Fix copy of unused kernel attributes 
Change-Id: Ib93f27d68cedac2182ba6dac0c234cc71c2c4229
 2022-12-13 03:44:10 +00:00
Galantsev, Dmitrii 5db4424549 Merge branch 'amd-dev' into amd-master 20221212 
Change-Id: I3dbaaae0e157487afbab1efb96d6f854c1249125
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>
 2022-12-12 20:12:57 -06:00
Galantsev, Dmitrii 3d46dd5abd Merge branch 'amd-dev' into amd-master 20221212 
Change-Id: I3dbaaae0e157487afbab1efb96d6f854c1249125
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>


[ROCm/amdsmi commit: 5db4424549]
 2022-12-12 20:12:57 -06:00
colramos425 45e42d894d Update Changelog 
Signed-off-by: colramos425 <colramos@amd.com>


[ROCm/rocprofiler-compute commit: b3041233ca]
 2022-12-12 17:53:55 -06:00
colramos425 b3041233ca Update Changelog 
Signed-off-by: colramos425 <colramos@amd.com>
 2022-12-12 17:53:55 -06:00
Ziyue Yang 431c7d2cb9 Add MSCCL Support (#658) 
* Add MSCCL support

* Add alignment and message size checking

* Fix nRanks checking, in-place and out-of-place tests and group call handling

* Fix hipGraph unit test

* Change MSCCL init warning to INFO

* Revise license info

[ROCm/rccl commit: adafc0f759]
 2022-12-12 15:51:04 -08:00
Ziyue Yang adafc0f759 Add MSCCL Support (#658) 
* Add MSCCL support

* Add alignment and message size checking

* Fix nRanks checking, in-place and out-of-place tests and group call handling

* Fix hipGraph unit test

* Change MSCCL init warning to INFO

* Revise license info
 2022-12-12 15:51:04 -08:00
Cole Ramos 19e413d200 Merge pull request #55 from AMDResearch/dev 
Merge features for v1.0.5

[ROCm/rocprofiler-compute commit: 76623fe7e7]
 2022-12-12 16:43:52 -06:00
Cole Ramos 76623fe7e7 Merge pull request #55 from AMDResearch/dev 
Merge features for v1.0.5
 2022-12-12 16:43:52 -06:00
colramos425 f3fa5544f2 Using xml configs from rocprofiler 
Signed-off-by: colramos425 <colramos@amd.com>


[ROCm/rocprofiler-compute commit: 9fa2d39f4a]
 2022-12-12 16:03:40 -06:00
colramos425 9fa2d39f4a Using xml configs from rocprofiler 
Signed-off-by: colramos425 <colramos@amd.com>
 2022-12-12 16:03:40 -06:00
Karl W. Schulz f76268b3a0 Include bibtex reference example directly within top-level README 
[ROCm/rocprofiler-compute commit: c64dbb1ed8]
 2022-12-12 15:55:49 -06:00
Karl W. Schulz c64dbb1ed8 Include bibtex reference example directly within top-level README 2022-12-12 15:55:49 -06:00
Galantsev, Dmitrii a255393b5c SWDEV-372949 - Resolve ASAN failure 
Change-Id: I622ba5e8fc4d30d98dae365a67a0b0e99ffae3a5
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>
 2022-12-12 15:49:55 -06:00
Galantsev, Dmitrii 00c054475d SWDEV-372949 - Resolve ASAN failure 
Change-Id: I622ba5e8fc4d30d98dae365a67a0b0e99ffae3a5
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>


[ROCm/amdsmi commit: a255393b5c]
 2022-12-12 15:49:55 -06:00
Galantsev, Dmitrii 0c52236abd CMAKE: Resolve lib dependencies for tests 
amdsmitst was failing and not finding libgtest and libamd_smi.

This change resolves the issue by

1. Installing gtest into tests directory
2. Modifying RUNPATH variable to point to libamd_smi.so

Change-Id: I126d01c88116d37c5f2b55b9ecb2c9f1313f26fe
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>
 2022-12-12 14:37:57 -06:00
Galantsev, Dmitrii 77223cb3db CMAKE: Resolve lib dependencies for tests 
amdsmitst was failing and not finding libgtest and libamd_smi.

This change resolves the issue by

1. Installing gtest into tests directory
2. Modifying RUNPATH variable to point to libamd_smi.so

Change-Id: I126d01c88116d37c5f2b55b9ecb2c9f1313f26fe
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>


[ROCm/amdsmi commit: 0c52236abd]
 2022-12-12 14:37:57 -06:00
Rahul Garg 6f89047bfa SWDEV-355313 - Merge remote-tracking branch 'hip/amd-staging' into amd-staging 
Change-Id: I96ef1395f75089ad701ca637f5c0273d280e849b


[ROCm/hip-tests commit: 0571115bed]
 2022-12-12 20:15:49 +00:00
Rahul Garg 0571115bed SWDEV-355313 - Merge remote-tracking branch 'hip/amd-staging' into amd-staging 
Change-Id: I96ef1395f75089ad701ca637f5c0273d280e849b
 2022-12-12 20:15:49 +00:00
Karl W. Schulz 1bd64feee5 changelog additions for next release 
Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>


[ROCm/rocprofiler-compute commit: dceabb9ddc]
 2022-12-12 15:01:35 -05:00
Karl W. Schulz dceabb9ddc changelog additions for next release 
Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>
 2022-12-12 15:01:35 -05:00
Karl W. Schulz 553eeb83f7 move DOI badge to top of README. Include pointer to bibtex-style generation. 
Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>


[ROCm/rocprofiler-compute commit: 477de3588a]
 2022-12-12 14:33:55 -05:00
Karl W. Schulz 477de3588a move DOI badge to top of README. Include pointer to bibtex-style generation. 
Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>
 2022-12-12 14:33:55 -05:00
Karl W. Schulz 9a7405191f Only update template VERSION.sha file when running within git clone. Fixes #53. 
Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>


[ROCm/rocprofiler-compute commit: 2f04b5b6b1]
 2022-12-12 13:28:39 -06:00
Karl W. Schulz 2f04b5b6b1 Only update template VERSION.sha file when running within git clone. Fixes #53. 
Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>
 2022-12-12 13:28:39 -06:00
kjayapra-amd c3c4eb85d3 SWDEV-371904 - Adding pseudo fine grain flag to hsa memory allocation for device fine grained memory. 
Change-Id: I8c605d6bc3ac905bfffc6de3a56911151ef0e663


[ROCm/clr commit: f7c194edf7]
 2022-12-12 11:40:00 -05:00
kjayapra-amd f7c194edf7 SWDEV-371904 - Adding pseudo fine grain flag to hsa memory allocation for device fine grained memory. 
Change-Id: I8c605d6bc3ac905bfffc6de3a56911151ef0e663
 2022-12-12 11:40:00 -05:00
pghafari c4fc6ea3ab SWDEV-369566, SWDEV-369565, SWDEV-369564 - match with cuda return 
Change-Id: I308f5344a64e5a06aa89685de9348f6722c196da


[ROCm/clr commit: 698f52acd8]
 2022-12-12 09:53:18 -05:00
pghafari 698f52acd8 SWDEV-369566, SWDEV-369565, SWDEV-369564 - match with cuda return 
Change-Id: I308f5344a64e5a06aa89685de9348f6722c196da
 2022-12-12 09:53:18 -05:00
David Addison 129a1b4b78 Add boot_id to the hostname hash due to collisions on Azure 
Fixes #60


[ROCm/rccl-tests commit: 0b4c4cb99f]
 2022-12-12 01:16:46 -08:00
David Addison 0b4c4cb99f Add boot_id to the hostname hash due to collisions on Azure 
Fixes #60
 2022-12-12 01:16:46 -08:00
Jithin Jose 5ba670d551 Use DJB2a hash algorithm in getHostHash() 
[ROCm/rccl-tests commit: 0aeba157db]
 2022-12-12 01:16:38 -08:00
Jithin Jose 0aeba157db Use DJB2a hash algorithm in getHostHash() 2022-12-12 01:16:38 -08:00
Hao Zhou 047eee3660 Merge amd-staging into amd-master 20221212 
Signed-off-by: Hao Zhou <Hao.Zhou@amd.com>
Change-Id: I555da02f58185a9eca00954755c2bfd8e418e153


[ROCm/rocm_smi_lib commit: 34f4b63853]
 2022-12-12 16:25:01 +08:00
Hao Zhou 34f4b63853 Merge amd-staging into amd-master 20221212 
Signed-off-by: Hao Zhou <Hao.Zhou@amd.com>
Change-Id: I555da02f58185a9eca00954755c2bfd8e418e153
 2022-12-12 16:25:01 +08:00
kjayapra-amd e295beb8ba SWDEV-371904 - Adding pseudo fine grain flag to hsa memory allocation for device fine grained memory. 
Change-Id: I8cada90f0e3880dfbc5bf5a3fac4554e7a0cb08e


[ROCm/clr commit: e56a611b92]
 2022-12-11 08:15:17 -05:00
kjayapra-amd e56a611b92 SWDEV-371904 - Adding pseudo fine grain flag to hsa memory allocation for device fine grained memory. 
Change-Id: I8cada90f0e3880dfbc5bf5a3fac4554e7a0cb08e
 2022-12-11 08:15:17 -05:00
Chauncey Hui 9cd8e38967 SWDEV-2 - Change OpenCL version number from 3542 to 3543 
[ROCm/clr commit: dc6bbe303b]
 2022-12-10 03:00:08 -05:00
Chauncey Hui dc6bbe303b SWDEV-2 - Change OpenCL version number from 3542 to 3543 2022-12-10 03:00:08 -05:00
Kiumars Sabeti a9a82ee107 SWDEV-369023: Added two new counters SQ_INSTS_TEX_LOAD and SQ_INSTS_TEX_STORE for gfx10.These two new counters are replacement for SQ_INSTS_VMEM_RD and SQ_INSTS_VMEM_WR which are not supported in gfx10 architecture 
Change-Id: I4c4101eea27f9073492ae42c70a30a002f4d8834
 2022-12-09 20:41:45 -05:00
Kiumars Sabeti f893fecf87 SWDEV-369023: Added two new counters SQ_INSTS_TEX_LOAD and SQ_INSTS_TEX_STORE for gfx10.These two new counters are replacement for SQ_INSTS_VMEM_RD and SQ_INSTS_VMEM_WR which are not supported in gfx10 architecture 
Change-Id: I4c4101eea27f9073492ae42c70a30a002f4d8834


[ROCm/rocprofiler commit: a9a82ee107]
 2022-12-09 20:41:45 -05:00