76333 Commits

Autor SHA1 Mensaje Fecha
David Galiffi 76cde58f56 Removing dyninst builds from CI docker files (#249)
Signed-off-by: David Galiffi <David.Galiffi@amd.com>

[ROCm/rocprofiler-systems commit: 8535da17c8]
2025-06-13 17:16:01 -04:00
David Galiffi 8535da17c8 Removing dyninst builds from CI docker files (#249)
Signed-off-by: David Galiffi <David.Galiffi@amd.com>
2025-06-13 17:16:01 -04:00
David Galiffi 7503cc7202 Add perfetto validation to rccl ctests (#246)
Check for the "RCCL Communication Send / Receive" data counters

Signed-off-by: David Galiffi <David.Galiffi@amd.com>

[ROCm/rocprofiler-systems commit: 6dd1ee78bf]
2025-06-13 17:09:49 -04:00
David Galiffi 6dd1ee78bf Add perfetto validation to rccl ctests (#246)
Check for the "RCCL Communication Send / Receive" data counters

Signed-off-by: David Galiffi <David.Galiffi@amd.com>
2025-06-13 17:09:49 -04:00
Yiltan 66e267235f Added simple rocshmem_info command (#156)
* Added simple rocshmem_info
* Add GPU Arch info

[ROCm/rocshmem commit: 72639277a3]
2025-06-13 15:40:32 -04:00
Yiltan 72639277a3 Added simple rocshmem_info command (#156)
* Added simple rocshmem_info
* Add GPU Arch info
2025-06-13 15:40:32 -04:00
akolliasAMD 482490f48f added init example and all_reduce example on the files (#150)
* added init example and all_reduce example on the files

* typo fix on folder name

[ROCm/rocshmem commit: 08a6a733d8]
2025-06-13 15:28:13 -04:00
akolliasAMD 08a6a733d8 added init example and all_reduce example on the files (#150)
* added init example and all_reduce example on the files

* typo fix on folder name
2025-06-13 15:28:13 -04:00
Aurelien Bouteiller f3345dbf05 Use finegrain allocator by default (#140)
* Use FineGrained allocator for heap by default, consolidate all types of
allocators under saner cmake controls

Co-authored-by: Yiltan <ytemucin@amd.com>

* Uncached may not be only for debug

Need to include the rocshmem config otherwise produce an inconsistent
build with different allocators used in different files

* Undo this pr adding presumably useless hip_host_allocator_noncoherent

* Rename HEAP_IS_COHERENT/USE_COHERENT_HEAP to USE_HDP_FLUSH as the former
was misleading

* Remove unused __roc_inv()

---------

Co-authored-by: Yiltan <ytemucin@amd.com>

[ROCm/rocshmem commit: 41fd9e2d57]
2025-06-13 15:26:26 -04:00
Aurelien Bouteiller 41fd9e2d57 Use finegrain allocator by default (#140)
* Use FineGrained allocator for heap by default, consolidate all types of
allocators under saner cmake controls

Co-authored-by: Yiltan <ytemucin@amd.com>

* Uncached may not be only for debug

Need to include the rocshmem config otherwise produce an inconsistent
build with different allocators used in different files

* Undo this pr adding presumably useless hip_host_allocator_noncoherent

* Rename HEAP_IS_COHERENT/USE_COHERENT_HEAP to USE_HDP_FLUSH as the former
was misleading

* Remove unused __roc_inv()

---------

Co-authored-by: Yiltan <ytemucin@amd.com>
2025-06-13 15:26:26 -04:00
Tim 7051f217a7 replayer update v0 (#1733)
* First version of new replayer, with comments on future TODOs

* plus minor fixes for UT

* Updated format of recorder, especially in binary department, according to replayer's need

[ROCm/rccl commit: ba97c9c18b]
2025-06-13 15:05:34 -04:00
Tim ba97c9c18b replayer update v0 (#1733)
* First version of new replayer, with comments on future TODOs

* plus minor fixes for UT

* Updated format of recorder, especially in binary department, according to replayer's need
2025-06-13 15:05:34 -04:00
Baraldi, Giovanni d41a31dc47 Adding LDS Bank conflict metric to MI300 (#456)
Adding LDS Bank conflict metric to MI3

Co-authored-by: Giovanni Baraldi <gbaraldi@amd.com>

[ROCm/rocprofiler-sdk commit: b1637869b3]
2025-06-13 19:28:57 +02:00
Baraldi, Giovanni b1637869b3 Adding LDS Bank conflict metric to MI300 (#456)
Adding LDS Bank conflict metric to MI3

Co-authored-by: Giovanni Baraldi <gbaraldi@amd.com>
2025-06-13 19:28:57 +02:00
Ranjith Ramakrishnan e8477f460f SWDEV-534264 - Add liboam.a to static rocm-smi package
liboam.a was missing in static rocm-smi package and resulting in compilation error on appliction that use rocm-smi


[ROCm/rocm_smi_lib commit: 59468e3f78]
2025-06-13 12:09:41 -05:00
Ranjith Ramakrishnan 59468e3f78 SWDEV-534264 - Add liboam.a to static rocm-smi package
liboam.a was missing in static rocm-smi package and resulting in compilation error on appliction that use rocm-smi
2025-06-13 12:09:41 -05:00
Sunday Clement 31b6474801 rocr: Remove Recursive Include
Removed unnecessary header inlude in file to prevent circular include.

Signed-off-by: Sunday Clement <Sunday.Clement@amd.com>
2025-06-13 12:29:52 -04:00
Sunday Clement 90e35e8486 rocr: Remove Recursive Include
Removed unnecessary header inlude in file to prevent circular include.

Signed-off-by: Sunday Clement <Sunday.Clement@amd.com>


[ROCm/ROCR-Runtime commit: 31b6474801]
2025-06-13 12:29:52 -04:00
Sunday Clement 06efa50c09 rocr: Fix Recursive Include in header files
scratch_cache.h includes amd_gpu_agent.h which then again includes
scratch_cache.h, this has now been fixed removing the unecessary
header include.

Signed-off-by: Sunday Clement <Sunday.Clement@amd.com>
2025-06-13 12:29:52 -04:00
Sunday Clement 76dbfc159c rocr: Fix Recursive Include in header files
scratch_cache.h includes amd_gpu_agent.h which then again includes
scratch_cache.h, this has now been fixed removing the unecessary
header include.

Signed-off-by: Sunday Clement <Sunday.Clement@amd.com>


[ROCm/ROCR-Runtime commit: 06efa50c09]
2025-06-13 12:29:52 -04:00
ywang103-amd 72e8576a7e format the code after mem chart's fix of test (#753)
[ROCm/rocprofiler-compute commit: b8dd6d049d]
2025-06-13 12:03:42 -04:00
ywang103-amd b8dd6d049d format the code after mem chart's fix of test (#753) 2025-06-13 12:03:42 -04:00
Aryan Salmanpour 3b10d1948e Improve the memory pool logic to enable the reuse of VA-API surfaces (#159)
* Improve the memory pool logic to enable the reuse of VA-API surfaces.

* Update the version

[ROCm/rocjpeg commit: 6046873054]
2025-06-13 11:51:26 -04:00
Aryan Salmanpour 6046873054 Improve the memory pool logic to enable the reuse of VA-API surfaces (#159)
* Improve the memory pool logic to enable the reuse of VA-API surfaces.

* Update the version
2025-06-13 11:51:26 -04:00
Jason Bonnell 503e2a8061 Move pr template file (#746)
* updated documentation wording, added cherry pick option for PR type

* moved pull_request_template to base .github directory

[ROCm/rocprofiler-compute commit: da6bf4b5c9]
2025-06-13 11:37:56 -04:00
Jason Bonnell da6bf4b5c9 Move pr template file (#746)
* updated documentation wording, added cherry pick option for PR type

* moved pull_request_template to base .github directory
2025-06-13 11:37:56 -04:00
GunaShekar, Ajay 57fccdf79c SWDEV-537473 - kernel path fix for windows (#286)
[ROCm/hip-tests commit: 797c104b4d]
2025-06-13 21:04:04 +05:30
GunaShekar, Ajay 797c104b4d SWDEV-537473 - kernel path fix for windows (#286) 2025-06-13 21:04:04 +05:30
Richard Barnes 2c0cc20a76 Enable -Wdeprecated-copy-with-user-provided-copy (#1643)
[ROCm/rccl commit: 4486d091b8]
2025-06-13 08:23:31 -07:00
Richard Barnes 4486d091b8 Enable -Wdeprecated-copy-with-user-provided-copy (#1643) 2025-06-13 08:23:31 -07:00
vedithal-amd 917634d332 fix test_gpu_specs.py (#752)
[ROCm/rocprofiler-compute commit: fa1e9965f8]
2025-06-13 10:01:59 -04:00
vedithal-amd fa1e9965f8 fix test_gpu_specs.py (#752) 2025-06-13 10:01:59 -04:00
Assiouras, Ioannis 079b490e64 SWDEV-537656 - Added c++11 include guard for constexpr HIP_vector_type operator== (#517)
[ROCm/clr commit: e88d9fabe0]
2025-06-13 12:05:41 +05:30
Assiouras, Ioannis e88d9fabe0 SWDEV-537656 - Added c++11 include guard for constexpr HIP_vector_type operator== (#517) 2025-06-13 12:05:41 +05:30
ywang103-amd dab2c49342 fix broken test with --cols options (#750)
[ROCm/rocprofiler-compute commit: bb0c417871]
2025-06-12 19:45:24 -04:00
ywang103-amd bb0c417871 fix broken test with --cols options (#750) 2025-06-12 19:45:24 -04:00
Maisam Arif 772b572913 Updated 6.4.2 Changelog
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
Change-Id: I975f5db0bde9ebccec3756415cb1e7dc47e78988
2025-06-12 17:17:13 -05:00
Maisam Arif 6688ae237f Updated 6.4.2 Changelog
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
Change-Id: I975f5db0bde9ebccec3756415cb1e7dc47e78988


[ROCm/amdsmi commit: 772b572913]
2025-06-12 17:17:13 -05:00
Arif, Maisam 9002bcc5a8 Revert "SWDEV-534264 - Add liboam.a to static package"
This reverts commit ae9bcb11e1.


[ROCm/rocm_smi_lib commit: 5cc6c1ca1c]
2025-06-12 16:26:19 -05:00
Arif, Maisam 5cc6c1ca1c Revert "SWDEV-534264 - Add liboam.a to static package"
This reverts commit ff7561607e.
2025-06-12 16:26:19 -05:00
jamessiddeley-amd 05aba003c9 Fix: Add explicit includes for assert.h and thread in sample files (#751)
* Fix: Add explicit includes for assert.h and thread in sample/vcopy.cpp

The HIP/CLR change e3cb5399c removed transitive inclusion  
of standard headers like assert.h from hip_runtime.h.  
This caused build failures in rocprof-compute samples.  

This commit explicitly includes <assert.h> and <thread>  
in vcopy.cpp to resolve potential missing definitions.  


Signed-off-by: jamessiddeley-amd <James.Siddeley@amd.com>

* Update vsequential_access.cpp

Added assert and thread imports

Signed-off-by: jamessiddeley-amd <James.Siddeley@amd.com>

* Update vrandom_access.cpp

Added assert import

Signed-off-by: jamessiddeley-amd <James.Siddeley@amd.com>

* Update vsequential_access.cpp

Signed-off-by: jamessiddeley-amd <James.Siddeley@amd.com>

---------

Signed-off-by: jamessiddeley-amd <James.Siddeley@amd.com>

[ROCm/rocprofiler-compute commit: 667128e3c7]
2025-06-12 17:03:48 -04:00
jamessiddeley-amd 667128e3c7 Fix: Add explicit includes for assert.h and thread in sample files (#751)
* Fix: Add explicit includes for assert.h and thread in sample/vcopy.cpp

The HIP/CLR change e3cb5399c removed transitive inclusion  
of standard headers like assert.h from hip_runtime.h.  
This caused build failures in rocprof-compute samples.  

This commit explicitly includes <assert.h> and <thread>  
in vcopy.cpp to resolve potential missing definitions.  


Signed-off-by: jamessiddeley-amd <James.Siddeley@amd.com>

* Update vsequential_access.cpp

Added assert and thread imports

Signed-off-by: jamessiddeley-amd <James.Siddeley@amd.com>

* Update vrandom_access.cpp

Added assert import

Signed-off-by: jamessiddeley-amd <James.Siddeley@amd.com>

* Update vsequential_access.cpp

Signed-off-by: jamessiddeley-amd <James.Siddeley@amd.com>

---------

Signed-off-by: jamessiddeley-amd <James.Siddeley@amd.com>
2025-06-12 17:03:48 -04:00
Jason Bonnell fe985ec077 add pull_request_template.md (#237)
* add pull_request_template.md

* Update .github/PULL_REQUEST_TEMPLATE/pull_request_template.md

Co-authored-by: David Galiffi <David.Galiffi@amd.com>

* fix markdown linting errors

* Update .github/PULL_REQUEST_TEMPLATE/pull_request_template.md

Co-authored-by: David Galiffi <David.Galiffi@amd.com>

* moved pull_request_template.md to base /.github/ directory

---------

Co-authored-by: David Galiffi <David.Galiffi@amd.com>

[ROCm/rocprofiler-systems commit: da326048b9]
2025-06-12 16:13:48 -04:00
Jason Bonnell da326048b9 add pull_request_template.md (#237)
* add pull_request_template.md

* Update .github/PULL_REQUEST_TEMPLATE/pull_request_template.md

Co-authored-by: David Galiffi <David.Galiffi@amd.com>

* fix markdown linting errors

* Update .github/PULL_REQUEST_TEMPLATE/pull_request_template.md

Co-authored-by: David Galiffi <David.Galiffi@amd.com>

* moved pull_request_template.md to base /.github/ directory

---------

Co-authored-by: David Galiffi <David.Galiffi@amd.com>
2025-06-12 16:13:48 -04:00
Vignesh Edithal 696c1407af Bugfix for PR #744
[ROCm/rocprofiler-compute commit: 6054b3b7fd]
2025-06-12 16:09:15 -04:00
Vignesh Edithal 6054b3b7fd Bugfix for PR #744 2025-06-12 16:09:15 -04:00
vedithal-amd 89bc1fc812 Change default rocprof to rocprofv3 (#748)
* Revert of https://github.com/ROCm/rocprofiler-compute/pull/738

* Change default rocprof backend interface to rocprofv3

* Add MI 350 support in documentation

* Added known issue that MI 100 profiling will not work unless rocprofv1
  is explicitly opted in

* Remove MI 50 soc gfx python class since MI 50 is not supported

[ROCm/rocprofiler-compute commit: d27ee69b52]
2025-06-12 15:45:11 -04:00
vedithal-amd d27ee69b52 Change default rocprof to rocprofv3 (#748)
* Revert of https://github.com/ROCm/rocprofiler-compute/pull/738

* Change default rocprof backend interface to rocprofv3

* Add MI 350 support in documentation

* Added known issue that MI 100 profiling will not work unless rocprofv1
  is explicitly opted in

* Remove MI 50 soc gfx python class since MI 50 is not supported
2025-06-12 15:45:11 -04:00
David Yat Sin 3c0af843e3 rocr: Remove scratch_backing_memory_byte_size
scratch_backing_memory_byte_size was originally removed, and then put
back in 02b38d0614. This was because it
was used by rocgdb. rocgdb code has been updated to not use this field.
Bumped _amdgpu_r_debug for the ABI change.
2025-06-12 15:33:47 -04:00
David Yat Sin b66b6991b0 rocr: Remove scratch_backing_memory_byte_size
scratch_backing_memory_byte_size was originally removed, and then put
back in e130172218. This was because it
was used by rocgdb. rocgdb code has been updated to not use this field.
Bumped _amdgpu_r_debug for the ABI change.


[ROCm/ROCR-Runtime commit: 3c0af843e3]
2025-06-12 15:33:47 -04:00