Gráfico de Commits

436 Commits

Autor SHA1 Mensagem Data
Sean Keely 16efad0cdc Correct inf loop defect in fast clock init.
Each time delay is grown we need to reset elapsed.  We want to take
the most accurate sample from the set at fixed delay.

Without this we will hang if there is ever an insufficiently accurate,
high unit clock read.

Change-Id: Ic65f364067789ac85a6572d67af2d77528e265bb


[ROCm/ROCR-Runtime commit: 4e9849034d]
2022-04-01 16:15:37 -04:00
Sean Keely cf3f441625 Release host buffers after segment freeze.
Release staging buffers after loading has completed.  The debugger
no longer uses this copy.

Change-Id: I46f36b50033bebe5a9ebc648b291d46f1d09b21d


[ROCm/ROCR-Runtime commit: 03a52655a8]
2022-03-23 23:53:02 -05:00
Sean Keely b7afebc27f Correct loader memory interfaces.
The loader must use internal interfaces to access page allocation
flags.  Code pages should also ensure use of cached memory.

Also relocate i-cache flush after code page copy.

Change-Id: I86d36243b6eebb1d46b991b372a5236baaf941ab


[ROCm/ROCR-Runtime commit: 048700f2e7]
2022-03-23 23:52:56 -05:00
Sean Keely f875298836 Correct queue error reporting.
VM faults should not report via the queue error handler.
The system event contains much more useful information.

Change-Id: I744d9b97b23334d7ed2c0f450111c1b8032567e3


[ROCm/ROCR-Runtime commit: fbc48521dc]
2022-03-23 23:37:53 -05:00
Sean Keely 60191a659b Ignore hive id for CPUs when selecting copy paths.
Hive ID is used during copy path selection to locate an optimal
pool of SDMA engines.  However, for CPU-GPU connections we always
want to use the host port facing engines, known generally as the
PCIe optimzed engines.  We want this selection even when the
connection is XGMI hence dropping the hive id for CPUs.

Change-Id: Iffe44174afecfc0bb3272b806fce549c930a49d9


[ROCm/ROCR-Runtime commit: af0f90800d]
2022-03-18 18:48:44 -05:00
Sean Keely 2be7abd7e1 Revert "add gfx1036 support"
Compiler is not promoted to mainline yet.

This reverts commit 7dcccdf452.

Change-Id: I7256aeb3698ee3ae640a9f457a929abe24d5ef17


[ROCm/ROCR-Runtime commit: 7e73760cd0]
2022-03-18 02:35:01 -05:00
Yifan Zhang 7dcccdf452 add gfx1036 support
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Change-Id: I075779b1369fde759c29572fa2027a3748d6ed4c


[ROCm/ROCR-Runtime commit: 2f97f17df9]
2022-03-05 13:16:19 +08:00
Sean Keely 47e1632188 Do not allow occupancy restriction on cooperative groups.
Excessive scratch allocations can normally trigger occupancy
reduction.  This breaks cooperative groups so if occupancy
reduction is required on a cooperative dispatch fail with OOM.

Change-Id: I64612a2e38bf1286f3b74c1c2a68ab0c85452771


[ROCm/ROCR-Runtime commit: 8a6954c63c]
2022-03-02 19:59:30 -06:00
Sean Keely c58913a8c8 Correct scratch allocation logic to account for asymmetric harvest.
With asym. harvest hw does not issue groups equally to each SE,
occasionally hw will skip an SE so that the distribution reflects
each SE's CU count.  Scratch resources must be allocated to reflect
this asymmetric distribution of groups.

Change-Id: I65e26206500483ea18e6e8796e65ecba5354b029


[ROCm/ROCR-Runtime commit: 552dcead93]
2022-03-02 19:59:30 -06:00
Sean Keely c196acd677 Do not bump up total scratch size for large cached allocations.
HW does not ignore low bits of the scratch wave count and will
stride beyond the end of the allocation if the wave count is
ever indivisible by SE count.  Rather than returning the allocation
size for cached large scratch allocations, use the requested
scratch size in scratch setup.  Scratch cache will retain the
cached allocation's size.

Change-Id: I0129ddc99a8940d01d8fbcd0b02d5061f31f456d


[ROCm/ROCR-Runtime commit: cedc3e80a8]
2022-03-02 20:48:19 -05:00
Sean Keely 523e6e883a Do not discard fragment allocator blocks multiple times.
discardBlock may be called multiple times on the same block.
We must not discard the block multiple times or we will corrupt
in-use memory accounting.

Change-Id: Ife9f3162785965a795dcf81887d4d447cc096e62


[ROCm/ROCR-Runtime commit: b9a0c1d313]
2022-02-10 18:39:46 -06:00
Sean Keely 305b7394b3 Add fallback case for cache line size.
KFD sometimes returns 0 for cache line sizes.

Change-Id: If82de0068318bbc138f0d1d4692ff908359174ad


[ROCm/ROCR-Runtime commit: 266cd68524]
2022-02-10 18:39:46 -06:00
Sean Keely ab97440eba Retrieve cache line size from KFD topology.
Change-Id: I16ddd9d9888bb973eccf3c562619894c88c7df15


[ROCm/ROCR-Runtime commit: 21291b48c6]
2022-01-16 08:44:44 -06:00
Sean Keely 0e96cb895f Correct queue minimum size enforcement.
Minimum queue size was not enforced at the Agent level.  Minimum
size should be one page to give unifority across all asics.

Change-Id: I26394f79458d09fbceb79fc8aaf495e2c26a8ff3


[ROCm/ROCR-Runtime commit: a6742209f7]
2022-01-16 08:28:34 -06:00
Sean Keely 92f675889c Improve scratch error detection in debug mode.
Adds asserts for invalid dispatch dims and scratch requests that
don't actually use scratch.

Change-Id: I6e6eef3f17dc38adaf96550fa55bd8625868efa3


[ROCm/ROCR-Runtime commit: a65f3f5b71]
2022-01-31 20:53:24 -05:00
Sean Keely e2e10173d2 Add HSA_AMD_AGENT_INFO_COOPERATIVE_COMPUTE_UNIT_COUNT.
On gfx90a only a reduced number of CUs must be used for cooperative
dispatches due to CWSR and launcher interactions with asymetric
harvest.  We must use one fewer CUs per SE than the lowest count of
CUs on any SE.

Also adds env var HSA_COOP_CU_COUNT which enables the cooperative
CU count computation.  Set to 1 to enable the new computation.
This is an opt-in feature that will become enabled by default (opt-out)
in a future release.

Change-Id: Ifbb75ced3bbc15876eef44922c6a4f6fde8c4c28


[ROCm/ROCR-Runtime commit: 37942c982a]
2022-01-31 15:22:07 -05:00
David Yat Sin 4fb019555b Fix for segfault after removing PrefetchRange from map
The start iterator becomes invalid after it is removed from
std::map prefetch_map_. This was causing a segfault when the iterator is
incremented afterwards.

Signed-off-by: David Yat Sin <david.yatsin@amd.com>
Change-Id: I4b0b763d2cb4ee99c0b8571c2c526b834e74077a


[ROCm/ROCR-Runtime commit: 86164fbfec]
2022-01-10 17:47:02 -05:00
Sean Keely ef1f4724c3 Correct documentation typo.
ROCM_VISIBLE_DEVICES was used where ROCR_VISIBLE_DEVICES was
intended.

Change-Id: I644a546f3c9dd0b50898ef8a21dbb8f5c3a36926


[ROCm/ROCR-Runtime commit: fce6ba052e]
2021-12-10 16:19:30 -06:00
Sean Keely 3227859ff2 Rework memory locks to allow device parallelism in alloc/free.
Prior solution used a single global lock to protect the memory tracking structures.
This change protects the memory tracking structure with a shared mutex (rw lock) in
shared (r) mode for memory allocations and frees so that long duration processes,
calling to kfd, can be done in parallel.  Operations which must modify the memory map
take the mutex in exclusive mode (w) and must not call to the thunk while holding
the mutex.

The fragment allocator now requires separate protection and is protected with a
mutex at the device level.  Protecting at the device level, rather than pool,
allows retention of the current recursive design and allows calling Trim from
withing Allocate.  This could be made finer (pool level locks) but would
require backing out of Allocate entirely to call Trim.  Trim and any retried
Allocation must be done in isolation (per device) or we may report OOM when
memory is actually available in some pool's fragment cache.  So some device
level serialization is required in at least some paths.

Change-Id: I7c1e94d6965ffcc602b12fefdd3a6e97b84b5e00


[ROCm/ROCR-Runtime commit: df55cb0450]
2021-11-24 19:22:05 -06:00
Sean Keely e462118b6e Add comments to GetPcieBlit.
Comments call out the specific operation being selected since the
ternary nest is a bit hard to read.

Change-Id: If033dbaa6cba132e96196ad3fc6d5572042041f4


[ROCm/ROCR-Runtime commit: fc75731034]
2021-11-15 19:34:03 -06:00
Sean Keely 01c7c9856c Fix leak in hsa_amd_interop_map_buffer.
Agent temp array could have leaked if one of the given agent
handles was invalid.

Change-Id: I9e638b3a4f6bb917a4e3209ad81a1253bb603365


[ROCm/ROCR-Runtime commit: b198016949]
2021-11-15 19:22:20 -06:00
Sean Keely 289cc7b6b4 Correct order of argument check and default assignment in lock APIs.
Argument must be checked for nullptr before being dereferenced and
filled with the default return value.

Change-Id: I9ff366f066a5e18c78129bf59cc3ba00fca3ef18


[ROCm/ROCR-Runtime commit: f48a786662]
2021-11-15 19:22:02 -06:00
Sean Keely a7dc6d7802 Add missing return in ScopeGuard::operator=.
This omission did not cause problems earlier due to having not been
instanced.

Change-Id: I7a54f82e06c299902f3bf6b4d3737cc5e30961ad


[ROCm/ROCR-Runtime commit: 322588a60e]
2021-11-15 18:50:46 -06:00
Sean Keely c8bb2905d3 Correct node id assertion in pointer info.
Size of the node map was used as the max node id previously.  This
is wrong when RVD is used.

Change-Id: Ic632ec96891b92186e5b68cd53f81414db34f59f


[ROCm/ROCR-Runtime commit: 19454fcf26]
2021-11-10 22:09:24 -06:00
Sean Keely 0ed7eac560 Correct size of SVM node array.
Was size of the map.  Needs to be size of the node id range.

Change-Id: I92501ea7adca5c30dbb0fdabd2c421dea58f8d6f


[ROCm/ROCR-Runtime commit: c9eb85e205]
2021-11-10 21:23:42 -06:00
Sean Keely 847df17afe Include event_id in SDMA interrupt payload.
The event id assists KFD in locating the proper event associated
with the interrupt.

Change-Id: I75d58b6be74dd5b1edb0c5fe2b9d01538a649ba1


[ROCm/ROCR-Runtime commit: d65e00bcc5]
2021-11-10 20:57:11 -06:00
Sean Keely f5fcc610b7 Silence Clang warning.
Clang warns about bitwise operators on bools.  Cast to int silences
the warning without introducing short circut logic.

Change-Id: I6e25138e1acf4a5562d3925ea5b2fcef3addb783


[ROCm/ROCR-Runtime commit: 4b0c94cfe8]
2021-10-14 23:56:58 -05:00
Sean Keely 0116378a99 Skip inital CU mask setup unless HSA_CU_MASK is defined for the GPU.
Limits CU masking application to cases where it is explicitly requested.

Change-Id: Ib65ad0ac98f86d840c0328fa15ce40c05cd4bfae


[ROCm/ROCR-Runtime commit: 5e8d261352]
2021-10-12 20:31:56 -05:00
Sean Keely f19e8c43d2 Remove io_link workarounds.
KFD topology has been corrected and the defaults used by this
workaround are no longer true for all chips.

Change-Id: I0242d8077e9666ed1cf0dc3985244258ae5c0924


[ROCm/ROCR-Runtime commit: 19c1e92b4c]
2021-10-11 19:15:07 -05:00
Sean Keely 1d060cbb9e Correct GetSvmAttrib coherency query.
Early exit if the range is found to be fine grain.  Indeterminate
should only apply if the range is neither coarse nor fine.

Change-Id: I54133e14f4e8cfa53e2d612f6112cdcdb5a47dfa


[ROCm/ROCR-Runtime commit: a2fb1cbfbc]
2021-10-03 12:29:12 -04:00
Sean Keely 94352f3e24 Close KFD when failing due to debugger state.
Change-Id: I6a6890fd9e86d27f87ae96de1c47c89d40a4e010


[ROCm/ROCR-Runtime commit: 234ef77e32]
2021-10-03 12:27:49 -04:00
Sean Keely e0ebcb9cc3 Workaround gfx90a SDMA0 quirk.
Because of sharing ports with other engines, the
hardware design team has advised that SDMA0 on gfx90a
should only be used for host-to-device data transfers.
The recommendation is to use SDMA1 for any device-to-device
or device-to-host data transfers.

A driver change will ensure that, for each gfx90a
device, only the first PCIe SDMA queue a process
requests will possibly be from SDMA0. This patch ensures
that the first PCIe queue requested (which may be from
SDMA0) is always set up for host-to-device.

Change-Id: I6793ca95596dedaed9d5be1dbd9469ceef2a5c33


[ROCm/ROCR-Runtime commit: 280a458d0c]
2021-09-30 05:53:49 -04:00
Sean Keely 10a8c8b556 Add debug option to skip setting the initial cu mask.
Adds debug variable HSA_CU_MASK_SKIP_INIT.

Change-Id: I5c742d1184a36fdef818bc50c3b780b859b68560


[ROCm/ROCR-Runtime commit: a8c3ea82a4]
2021-09-16 23:43:49 -05:00
Sean Keely a02b318a7e Correct fast f16 capability reporting.
Was hard coded to false.  Updated to reflect f16 availablity since
gfx8.

Change-Id: I7d5b9792c8e0163199c421a61b5d49b25cd98645


[ROCm/ROCR-Runtime commit: 5535b1f86f]
2021-09-16 21:15:52 -05:00
Oak Zeng f590465aa3 Add gfx1013 support
Change-Id: I7122caea3ef2254b50bde25ec545116685452116
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>


[ROCm/ROCR-Runtime commit: 80206af91e]
2021-09-15 01:10:20 -04:00
Sean Keely 2537a8b1c2 Place GPU local resources in nearest NUMA node.
For minimal latency we should place command queues and blit code
in the nearest numa node to each GPU.  Add an allocator matching
the current runtime default allocator interface to each GpuAgent
that allocates on the closest numa node as represented by kfd
topology.  Use this allocator for queue ring buffers and blit
objects.

Change-Id: I181127f9c27bafe68976312963146616e3f58369


[ROCm/ROCR-Runtime commit: 5af558f739]
2021-09-14 17:49:24 -04:00
Sean Keely f6dcfa4246 Register the default queue error handler for all internal queues.
Also make failure to handle queue errors fatal.

Motivation is to improve detection of queue error conditions
that currently appear as application hangs.

Change-Id: I655643616dc0bd303d7df3ce8aca2c099bec3d46


[ROCm/ROCR-Runtime commit: 907679c989]
2021-08-27 20:11:58 -04:00
Sean Keely 9870e8b576 Correct queue exception hander termination.
Set handler state to terminated before exiting.
Also simplify scratch handler exit loop.

Change-Id: I0a80c8a1899e8b60a6e7aa6989ba28de42ba31e7


[ROCm/ROCR-Runtime commit: e06dd39d89]
2021-08-27 20:06:44 -04:00
Sean Keely 07103a6b97 Allow passing zero bits into hsa_amd_queue_cu_set_mask.
Passing 0 into num_cu_mask_count used to be an implicit error.
This has been repurposed as a short hand for enabling all CUs.
Enabling all CUs when HSA_CU_MASK is set will cause the CU mask to
reset to whatever was set by HSA_CU_MASK which may then be queried.

Change-Id: I1d6bb2034595a78ee48fa72aa05563e8ea6c0fff


[ROCm/ROCR-Runtime commit: 02666ec0f1]
2021-08-27 20:05:24 -04:00
Sean Keely dbba14f823 Improve HSA_CU_MASK parsing efficiency.
Delay parsing until after GPU discovery.  Use the surfaced
GPU count and maximum phyiscal CU count to limit parsed bit masks.

This prevents pathological input such as
HSA_CU_MASK=0-8000000:0-8000000 from attempting to consume 7TiB.

Change-Id: I3773d2db3740c2023b0f6275d1818b69119b0495


[ROCm/ROCR-Runtime commit: 2aa0795b33]
2021-08-27 20:05:18 -04:00
Sean Keely e4b3eb87e2 Minor interface improvement to pointer info.
Take in const void* rather than void*.  This does not break the
abi or existing code.  Existing code would need to cast away any
const which is unnecessary and annoying.

Change-Id: I28787e8fab1b600bf6871ea82835e10a4f475c5b


[ROCm/ROCR-Runtime commit: 270d042ef8]
2021-08-04 16:43:23 -04:00
Sean Keely 951ec33ae0 Correct hsa_status_string strings.
Some strings were missing the human readable form of the error code.
Also unifying source formatting via clang-format.

Change-Id: I0bcc2ab77dda476904c684cc2c584a5c7e8230d4


[ROCm/ROCR-Runtime commit: 081ab00f8e]
2021-07-30 16:30:31 -04:00
Sean Keely c549aa71c3 Add missing HSA_STATUS_ERROR_INVALID_MEMORY_POOL string.
HSA_STATUS_ERROR_INVALID_MEMORY_POOL was missing from
hsa_status_string.

Change-Id: I9a9121d54a61f966d87081a55638397473bddbe4


[ROCm/ROCR-Runtime commit: 62b7c0ed3b]
2021-07-30 16:30:25 -04:00
Sean Keely 4fb0096393 Minor correction to debug messages.
Added missing \n.

Change-Id: I6e17459390c2c18819fc1decd8a6c91b7d7409cf


[ROCm/ROCR-Runtime commit: a0069904c8]
2021-07-30 16:30:18 -04:00
Sean Keely dd7c30ec6b Correct data race in GpuAgent::GetXgmiBlit.
Threads may race against xgmi_peer_list_ when dynamically assigning
peers to sdma engines.

Change-Id: I300c10f0cfa0ff7d6a5515364070a0895e2f4644


[ROCm/ROCR-Runtime commit: bb4dfbba1e]
2021-07-30 16:10:59 -04:00
Sean Keely b10954c185 Add global_flags reporting to pointer info.
global_flags reporting allows discovery of an allocation's memory
model (coarse, fine, kernarg).  This is critical on gfx90a and
also allows discovery of the memory model of IPC imports.

Change-Id: Icbc3c243ca20e264af5e1931becd2419f762c7ad


[ROCm/ROCR-Runtime commit: e3a01690a5]
2021-07-29 15:37:47 -05:00
Sean Keely 08cb823d21 Report SVM range queries with both coarse and fine grain as indeterminate.
Previously ranges were reported as fine if and only if they were
entirely fine.  Coarse and mixed ranges were reported as coarse.
For gfx90a it is critical to know if a range is coarse or fine as
fp atomics targeting fine do not function.  Range queried reporting
coarse must be able to be trusted so must only report coarse if the
entire region is coarse.

Change-Id: I29c654a2afcd6943961eb2455e3654dfdb1283b5


[ROCm/ROCR-Runtime commit: e6e66e8a05]
2021-07-29 15:34:58 -05:00
Sean Keely 4c6ea88cf5 Add HSA_CU_MASK
New environment variable HSA_CU_MASK allows users to
specify a cu mask to every queue allocated from any
GPU.  hsa_amd_queue_cu_set_mask is restricted from
escaping this mask.

A new API hsa_amd_queue_cu_get_mask is added to query
the current cu mask.

Change-Id: I846c03a5faaca9b95067c31db84b59cc9fce2f03


[ROCm/ROCR-Runtime commit: 4455250be1]
2021-07-29 02:23:34 -05:00
Aaron Liu eb72821574 Add gfx1035 for yellow carp
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Change-Id: I1e3e44352b5825fc0f249c39aed703d4990995ca


[ROCm/ROCR-Runtime commit: 4032070c3e]
2021-07-22 13:48:31 +08:00
Sean Keely 32766de851 Add support for reporting vm faults through the queue error handler.
Under xnack we can now identify the queue which generated a vm fault.
This allows users to identify which queue, and therefore which
dispatch, a vm fault came from.

Change-Id: If72ff3de05800f2b811aa7842a15eedff8b5e45a


[ROCm/ROCR-Runtime commit: 59ee761f81]
2021-07-16 18:03:26 -05:00