Commit-Graf

389 Incheckningar

Upphovsman SHA1 Meddelande Datum
Sean Keely 4c6ea88cf5 Add HSA_CU_MASK
New environment variable HSA_CU_MASK allows users to
specify a cu mask to every queue allocated from any
GPU.  hsa_amd_queue_cu_set_mask is restricted from
escaping this mask.

A new API hsa_amd_queue_cu_get_mask is added to query
the current cu mask.

Change-Id: I846c03a5faaca9b95067c31db84b59cc9fce2f03


[ROCm/ROCR-Runtime commit: 4455250be1]
2021-07-29 02:23:34 -05:00
Aaron Liu eb72821574 Add gfx1035 for yellow carp
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Change-Id: I1e3e44352b5825fc0f249c39aed703d4990995ca


[ROCm/ROCR-Runtime commit: 4032070c3e]
2021-07-22 13:48:31 +08:00
Sean Keely 32766de851 Add support for reporting vm faults through the queue error handler.
Under xnack we can now identify the queue which generated a vm fault.
This allows users to identify which queue, and therefore which
dispatch, a vm fault came from.

Change-Id: If72ff3de05800f2b811aa7842a15eedff8b5e45a


[ROCm/ROCR-Runtime commit: 59ee761f81]
2021-07-16 18:03:26 -05:00
Laurent Morichetti 0a2ad007a4 Fix incorrect packet index in ttmp6
ttmp6.packet_index is reported as 0 for all waves, regardless of the
dispatch packet position in the queue, due to an issue in the clearing
of the previous trap_id and saved status.halt bit.

Fixed TTMP6_SAVED_STATUS_HALT_MASK to only be one bit, 1<<29.

Change-Id: Ia4934e51123a40d71de658efc387a1f3a6344f05


[ROCm/ROCR-Runtime commit: ef1955ad42]
2021-07-16 18:03:26 -05:00
Jay Cornwall b65eb065c3 Report union of wave errors as a bitmask in trap handler
Also fix incorrect PC increment on host trap.

Change-Id: Ic8bbf2b90f9f879ba62b558b909d010a8939a663


[ROCm/ROCR-Runtime commit: f3d942b67f]
2021-07-16 18:03:26 -05:00
Jay Cornwall 690aef5c9e Clear queue error code when not handling exceptions
If left non-zero the event loop will keep reinvoking the callback,
preventing AqlQueue::ExceptionHandler from running.

Change-Id: If85fbaf62f04ffd327ecf9d649aa23afad4442ce


[ROCm/ROCR-Runtime commit: 8d4608ed0e]
2021-07-16 18:03:26 -05:00
Jay Cornwall 06cc198b57 Add new trap handler, bump debug API version
Also fix hsaKmtRuntimeEnable error handling. Continue if ioctl fails.

Change-Id: I754ccba5910ccfef6f1ada1415593ef89ce33aba


[ROCm/ROCR-Runtime commit: 7e4088309d]
2021-07-16 18:03:26 -05:00
Sean Keely 0bb9344674 Initialize new exception handler state.
Change-Id: Ibcb699760837b9ec1508d6af948a272a81ddcd02


[ROCm/ROCR-Runtime commit: 0159aea4c9]
2021-07-16 18:03:26 -05:00
Sean Keely 5c9500d50b Support debugging hw exceptions.
Change-Id: I9780147294af2e9457fa54693580735452ee2ae6


[ROCm/ROCR-Runtime commit: 206e87d28b]
2021-07-16 18:03:26 -05:00
Sean Keely 183531963c Always execute the first satisfied async signal handler.
Certain special signals do not carry their updates via their signal
value.  These signals are wrappers around special KFD events, of
which the only current instance informs about VM faults.  We either
need to check each signal for this special event type or rely on
the checking done in hsa_amd_signal_wait_any.  Since there will always
be a small number of these signals it doesn't make much since to
penalize the performance path with this check.  Additionally we know
that the signal indicated by hsa_amd_signal_wait_any is satisfied so
don't need to recheck it's conditions.

Change-Id: I9fc6298300ad543d823ecd28ca8fab4ad26c23ef


[ROCm/ROCR-Runtime commit: 3d6a18b67c]
2021-06-24 02:45:31 -05:00
Sean Keely b8533eec6d Add agent info query for HSA_AMD_AGENT_INFO_SVM_DIRECT_HOST_ACCESS.
Allows determining if the host can directly access HMM memory that
is physically resident in vram.

Change-Id: Ie452eedd0e27fe1b511afd416f5a1cd01b3d84e8


[ROCm/ROCR-Runtime commit: 9e53cab613]
2021-06-17 03:45:26 -04:00
Sean Keely 0100fa968c Allocate any size vram request through the fragment allocator.
Enables the fragment allocator to handle >2MB allocations, maintaining
good TLB alignment.  Prior code contained a bug that caused the effective
API granule for vram allocations >2MB to be bumped to 2MB.

Also adjusts the block cache's block retention heuristic to not
count discarded blocks as in use.  This will reduce block retention
when a significant amount of large blocks or IPC is in use.

Change-Id: I30bd85eb87951df822211f799d9cfe579ab109c6


[ROCm/ROCR-Runtime commit: 8adbda1c18]
2021-06-10 19:30:54 -05:00
Sean Keely 426a9f4df0 Remove unused GpuAgent.local_region_ member.
Change-Id: I99526e6b1f64e810f7fed5d922c540d252a46d80


[ROCm/ROCR-Runtime commit: 981c6bd8c3]
2021-06-07 19:59:58 -04:00
Sean Keely c35562e45b Add debugging checks for packet type in the scratch handler.
Change-Id: I84a6f18548ac39349595e3a1c8a5a9ff27d4e178


[ROCm/ROCR-Runtime commit: bd59789f0b]
2021-06-07 15:36:18 -04:00
Sean Keely 67029106d9 Limit reporting of GPU_ONLY signal waits from host.
Such waits must spin but are functionally correct.

Change-Id: I4992852f04da788495c6f566c46a3dffaf38397c


[ROCm/ROCR-Runtime commit: 3323e18f3e]
2021-06-03 15:26:40 -05:00
Sean Keely 2c4b216db6 Allow limiting debug warning messages.
Add macro debug_warning_n to stop printing a message after
N instances.

Change-Id: Id5f84b11eb63b3a20bd2bcb2ea8f10a066b457ef


[ROCm/ROCR-Runtime commit: ca8387768e]
2021-06-03 15:25:55 -05:00
Sean Keely 76c8067786 Improve async handler performance.
Under high async handler load signal retention and event sorting
become bottlenecks.  This change processes more handlers in a
single pass to amortize wait_any overheads.

Change-Id: I8b276e102db647e3858e120547aa0c6fca85ab4c


[ROCm/ROCR-Runtime commit: 6b398eb72c]
2021-06-02 23:52:07 -05:00
Sean Keely 530385e8e8 Add Read Mostly attribute support.
Change-Id: Ia7c60edacb892cbf14bdb50350c0a0a627e53964


[ROCm/ROCR-Runtime commit: f6c2aa1c78]
2021-06-01 23:39:12 -05:00
Chris Freehill 75190cb229 Add gfx1034 support
Change-Id: I2d4bfcb9012704daf7de10739c966827bd2a09e2


[ROCm/ROCR-Runtime commit: 8cb686fdc5]
2021-05-25 16:43:16 -05:00
Mike (Tianxin) Li f60550207c Revert "Get the size of VGPR and SGPR register file"
This reverts commit 2ae10ae479.

Change-Id: I9988218ad1d2b6182d92aad09d18a95e77e46c01


[ROCm/ROCR-Runtime commit: 36c54c63f7]
2021-05-18 15:01:30 -04:00
Mike Li 2ae10ae479 Get the size of VGPR and SGPR register file
Signed-off-by: Mike Li <Tianxinmike.Li@amd.com>
Change-Id: Ifa515ad7e1df1dd27f25f1e919b0053049531063


[ROCm/ROCR-Runtime commit: 344ed757e0]
2021-05-13 11:54:41 -04:00
Sean Keely 4cad5320c9 Correct merge error.
Old memory properties info name used after removing branches.
This caused the CPU coarse grain pool to initialize with random
bits.

Change-Id: I397bc5ecf09fab69bdf1d7fafadcf54d71b64070


[ROCm/ROCR-Runtime commit: 0439dc90cd]
2021-05-06 18:40:56 -05:00
Sean Keely aff2056789 Add exception forwarding to tools API callbacks.
Prevents poorly written tools which throw in tools interface
callbacks from causing ROCr to catch and return a generic error
code.

Change-Id: I2f5bf7104dc7d4ee688eb48423c7ffdb06bd7702


[ROCm/ROCR-Runtime commit: c9ce27a640]
2021-05-04 02:14:20 -05:00
Sean Keely ed740bfebc Correct scratch in use computation.
Old logic did not consider memory held in the scratch cache to be
free when deciding whether or not to reclaim.

Change-Id: I7f7c7549c72d743edbf7c53489fe9a453dc4177a


[ROCm/ROCR-Runtime commit: 0b7d9db964]
2021-04-22 20:07:25 -04:00
Sean Keely 13c8e534d3 Report HMM driver support status.
Implements HSA_AMD_SYSTEM_INFO_SVM_SUPPORTED.

Change-Id: If5182edcc1fa067fa514aa2c1bd326c4c42d1b64


[ROCm/ROCR-Runtime commit: ee8b1b64ad]
2021-04-21 21:44:42 -05:00
Sean Keely 1aae64e251 Revert "Revert SVM and XNACK support."
This reverts commit da41352a93.

Conflicts:
	opensrc/hsa-runtime/core/util/flag.h

Change-Id: I16daf41588e6139126d66af54b0693de2e7e39f3


[ROCm/ROCR-Runtime commit: 77046a1aaa]
2021-04-21 14:49:43 -05:00
Sean Keely 58813ab760 Ensure ROCr created threads have no CPU affinity.
Change-Id: I53828dbaf055b65b61bdd11f0eadfcc806596821


[ROCm/ROCR-Runtime commit: 3127d1ffdc]
2021-04-19 19:47:06 -05:00
Konstantin Zhuravlyov b095fec147 Expose iterator for executables
Change-Id: I0c5d39fc33c15a6eb8ee10ff181c2dcf2e042675


[ROCm/ROCR-Runtime commit: 15e54d684d]
2021-04-16 20:51:48 -04:00
Mike Li 3258d72d3b Get GPU cache information from KFD
Signed-off-by: Mike Li <Tianxinmike.Li@amd.com>
Change-Id: I8dc8c97ae81c3747b7cd88cf2cdb7a9e4694a88d


[ROCm/ROCR-Runtime commit: d077606e22]
2021-04-13 10:29:34 -04:00
Tony Tye e20cccb6e4 Add support for gfx909 and gfx90c
Change-Id: I88158789cdda44a173e3ca26d2c96b8e0ea0e221


[ROCm/ROCR-Runtime commit: a97c14abea]
2021-04-08 22:37:30 +00:00
Sean Keely 2b25548eb0 Remove emulator SRAMECC override controls.
Change-Id: Iea9e7870dbf517032f34cebec673c90226b96960


[ROCm/ROCR-Runtime commit: 243e29ba8e]
2021-04-02 02:11:05 -04:00
Sean Keely da41352a93 Revert SVM and XNACK support.
KFD is not ready yet.

Change-Id: I61deb292ddb92185d33504c2115169888d56e211


[ROCm/ROCR-Runtime commit: 5bd153974d]
2021-04-02 02:10:59 -04:00
Ramesh Errabolu 29fa097a82 Override Cpu-Gpu link-weight for Alebaran until a proper fix is available
Change-Id: I1fbc38b788f71cc9c9fc62295223286004689bf9


[ROCm/ROCR-Runtime commit: 25f3dc305f]
2021-04-02 02:10:54 -04:00
Sean Keely dd42ca6dbe Squash merge of cfreehil/amd-temp-gfx90a onto amd-staging.
Includes some workarounds and HMM.
Conflicts:
	opensrc/hsa-runtime/core/runtime/amd_topology.cpp
	opensrc/hsa-runtime/core/util/flag.h

Change-Id: I22976f07964a43dbb228a6231777dbd599112b8d


[ROCm/ROCR-Runtime commit: 7333c77e22]
2021-04-02 02:10:15 -04:00
Sean Keely ea1f545fcc Correct hsa_agent_iterate_isas return code for CPUs.
When no isa's are available no callbacks should be invoked.  This
is not an error and should return success.

Change-Id: Ie4048aa8cbe5c3fdf5431f6a865021549ecf8a13


[ROCm/ROCR-Runtime commit: 4197461b7f]
2021-04-01 00:08:22 -04:00
Sean Keely 465ada0234 Block ROCm 4.1+ running against 4.0 and prior kfd.
Sramecc is misreported in kfd 4.0 and prior.  To prevent possible
corruption due to d16 instructions, deny use of gfx906 with older
kfds and correct misreport for gfx908.  Denial of gfx906 may be
overridden by setting HSA_IGNORE_SRAMECC_MISREPORT=1.

Change-Id: I7d5c3a716fad01c348f8b88cd508cedbf914c989


[ROCm/ROCR-Runtime commit: 45fbe5b192]
2021-04-01 00:03:32 -04:00
Laurent Morichetti 023947a6de New trap handler ABI (v5)
Park the wave, if it is stopped, to avoid halting it at an s_endpgm
instruction if the architecture does not support it.

Free ttmp6 by converting the dispatch_ptr into a queue packet index
(25-bit) and storing it in ttmp7[24:0].

Save the exception PC in ttmp11[22:7] ttmp6[31:0].

Change-Id: Iaa3c5baf5b488c0b534044d338f12bffa63ddce2


[ROCm/ROCR-Runtime commit: ea6ee0aa81]
2021-03-04 21:44:14 -05:00
Laurent Morichetti 188570928f Correct the trap handler
ttmp11 no longer has an "excp_raised" field.

Change-Id: I8e673ca404c2b802470bbc9f76e7925782076c5a


[ROCm/ROCR-Runtime commit: 7e0f391a08]
2021-03-04 21:21:26 -05:00
Sean Keely e2aca270b7 Insert scratch memory into scratch cache on full profile systems.
Scratch cache was not updated for IOMMUv2 systems previously.
This both negates the cache and causes segfault during scratch
release.

Change-Id: I71e81d6b642d65ca135868ff7225ea173529d458


[ROCm/ROCR-Runtime commit: 191664cd20]
2021-03-03 21:30:16 -05:00
Jason Tang 562258ec93 Correct GetIsa() typo
Change-Id: Ia6b5a86bd035fb077f0da9d52160ec8d12987b87


[ROCm/ROCR-Runtime commit: ec22afb8a8]
2021-02-17 11:57:58 -05:00
Sean Keely 622dc89e98 Correct legacy copy path.
Legacy p2p copy path incorrectly transfered in whole pages rather than
the requested size.

Change-Id: I9aa7337754f9e32f587a0cc5305f8ffeb6196f10


[ROCm/ROCR-Runtime commit: 34ac62274a]
2021-02-10 19:53:02 -05:00
Sean Keely 4047b1c3a8 Add hsa_amd_signal_value_pointer.
Enables partial signal interop with non-HSA devices.

Change-Id: Ic39bca84ed1709cbd2cc24b1eb0f4fc6cccb39cf


[ROCm/ROCR-Runtime commit: 01f42dbe46]
2021-02-10 18:47:54 -05:00
Laurent Morichetti b3dc12024b New trap handler ABI (v4)
Replace the stop reasons ttmp11.trap_raised and ttmp11.excp_raised
with ttmp11.wave_stopped which indicates that the trap handler has
halted the wave as the result of an event (trap, single-step or
exception).

If the wave is stopped because of a trap, also record the trap_id in
ttmp11.saved_trap_id[7:0].

Save status.halt in ttmp11.saved_status_halt, so that it can be
restored when resuming a wave (changing a wave's state from stopped to
running or single-stepping).

Change-Id: I7322f59b60e8cc1b92bf5f067dba606a3109ef49


[ROCm/ROCR-Runtime commit: 9ca79d072a]
2021-02-05 09:56:01 -08:00
Huang Rui cb0f788b9b Add gfx10.3.3 ISA support for Van Gogh
This patch is to let ROCr recognize new gfx10.3.3 ISA.

Change-Id: Ied23eee2752e14c19c8c0a6d7789fded9940e31e
Signed-off-by: Huang Rui <ray.huang@amd.com>


[ROCm/ROCR-Runtime commit: feeb2f62e2]
2021-01-22 04:22:15 -05:00
Laurent Morichetti 062d313530 Don't terminate waves halted at s_endpgm
To support single stepping the instruction preceding an s_endpgm,
unwind the PC by 8 bytes and set ttmp11[9] to notify the debugger
that the wave is halted with a modified PC.

Bump the debug r_version for this new trap handler ABI.

Change-Id: I55e4e0d65576f92da14a336266c31c513baab547


[ROCm/ROCR-Runtime commit: 8aec53969f]
2021-01-21 20:51:38 -08:00
Laurent Morichetti 3eaae50cc6 Correct gfx10.3+ trap handler.
Change-Id: I77d2b41c8882014a430d741ecd777718a1f61561


[ROCm/ROCR-Runtime commit: 8808ed3177]
2021-01-21 09:24:20 -08:00
Tony Tye 0aa0ebe2ee Correct isa lookup for targets that do not support a target feature
Change-Id: I130070a53162e5d9fcc6a64a4bdda7869179be82


[ROCm/ROCR-Runtime commit: 26fe26e415]
2021-01-18 15:47:19 +00:00
Chris Freehill 33438e7adc Correct some target ID strings for gfx908
Change-Id: I7833b561447b9928447cf49472cfe1ca1867e71d


[ROCm/ROCR-Runtime commit: 09bc75bf0d]
2021-01-15 14:56:38 -06:00
Sean Keely 343684f84d Correct computation of scratch slot requirements.
Each SE must be assigned equal numbers of slots and slots
must be assigned in units of whole groups.

Change-Id: I8f3677237fa6f2e2d25e3e78210c5a7a0ad792f3


[ROCm/ROCR-Runtime commit: 7bc6aac5d2]
2021-01-13 15:09:00 -05:00
Sean Keely ddfed66eec Revert "Revert "Cache scratch allocations.""
This reverts commit 4502bb94c9.

Change-Id: I3f3c257270016559f8b2e70151664f0931db28d2


[ROCm/ROCR-Runtime commit: 9fe8ccc3ee]
2021-01-13 15:08:53 -05:00