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Author SHA1 Message Date
vedithal-amd f9aa7be97c Support MI 350 profiling (#632) 
* Add MI 350 hardware information

* Refactor MI GPU YAML file and corresponding interface

* Add SoC file for gfx950 architecture

* Add analysis report configs for MI 350 containing existing metrics

* Add placeholder None valued metrics for previous architectures to make
  baseline comparison work

* Enable testing on MI 350

* Analysis config metric changes
    - SPI changes
        - Update metric formula for default SPI pipe counter
             - Use efficiently collected pipe wise SPI counters
        - Add SPI Wave Occupancy
        - Add Scheduler-Pipe Wave Utilization
        - Update formula for VGPR Writes
        - Add Scheduler-Pipe FIFO Full Rate
   - CPC changes
	- Add CPC SYNC FIFO Full Rate
	- Add CPC CANE Stall Rate
        - Add CPC ADC Utilization
   - SQ changes
        - Add VALU co-issue efficiency
        - Add F6F4 datatype metrics
        - Update formula for total FLOPs by adding F6F4 counters
        - Add LDS STORE / LOAD / ATOMIC metrics
        - Add LDS STORE / LOAD / ATOMIC bandwidth
        - Add LDS FIFO and TA ADDR / CMD / DATA FIFO full rates

* Collect TCP_TCP_LATENCY_sum only for gfx950 (MI 350)

* Do not inject SQ_ACCUM_PREV_HIRES unnecesarily

* Do not hardcode memory and shader clock speeds

* Write num_hbm_channels to sysinfo.csv instead of hbm_bw while profiling

* Move generate sysinfo.csv to pre processing step of profiling

* Add warnings to use --specs-correction for missing sysinfo.csv values during analysis phase

* Update CHANGELOG

* Analysis phase warning to use --specs-correction when needed
 2025-04-03 02:21:18 -04:00
xuchen-amd 1273a5e2a9 Add mi350 ta td tcp tcc counters (#653) 
* Add mi350 TA and TD metrics.

* Add mi350 TCC metrics, and separate write and atomic metrics.

* Add mi350 TCP metrics.

* Add none values for non-gfx950 socs, remove missing metrics in rocprofv3.

---------

Signed-off-by: xuchen-amd <xuchen@amd.com>

[ROCm/rocprofiler-compute commit: f3736778f4]
 2025-04-02 21:25:47 -04:00
xuchen-amd f3736778f4 Add mi350 ta td tcp tcc counters (#653) 
* Add mi350 TA and TD metrics.

* Add mi350 TCC metrics, and separate write and atomic metrics.

* Add mi350 TCP metrics.

* Add none values for non-gfx950 socs, remove missing metrics in rocprofv3.

---------

Signed-off-by: xuchen-amd <xuchen@amd.com>
 2025-04-02 21:25:47 -04:00
xuchen-amd 08e083cc25 Add mi300 TCP counter tests (#644) 
* Add new sample applications.

* Generalize py test launcher for additional apps.

* Add TCP pytest, and add to ctest.

* Update licensing.

* Disable for non-mi300 machines.

[ROCm/rocprofiler-compute commit: 591632dd69]
 2025-04-02 20:32:13 -04:00
xuchen-amd 591632dd69 Add mi300 TCP counter tests (#644) 
* Add new sample applications.

* Generalize py test launcher for additional apps.

* Add TCP pytest, and add to ctest.

* Update licensing.

* Disable for non-mi300 machines.
 2025-04-02 20:32:13 -04:00
xuchen-amd 35acf4c410 remove flask debug msg (#655) 
* Suppress Flask warning message in quiet mode.

* Init args.gui if dne.

[ROCm/rocprofiler-compute commit: c7202923b0]
 2025-04-02 20:29:39 -04:00
xuchen-amd c7202923b0 remove flask debug msg (#655) 
* Suppress Flask warning message in quiet mode.

* Init args.gui if dne.
 2025-04-02 20:29:39 -04:00
xuchen-amd b21384ca60 Enable tuned performance counters for gfx950 (#652) 
* Enable non-functional performance counters for gfx950.

* Update changelog.

* Add none value metrics for non-gfx950 socs

* Remove rocprofv3 missing metrics.

[ROCm/rocprofiler-compute commit: dce75f4afa]
 2025-04-02 14:43:12 -04:00
xuchen-amd dce75f4afa Enable tuned performance counters for gfx950 (#652) 
* Enable non-functional performance counters for gfx950.

* Update changelog.

* Add none value metrics for non-gfx950 socs

* Remove rocprofv3 missing metrics.
 2025-04-02 14:43:12 -04:00
Kandula, Venkateshwar reddy f75e7bc674 SWDEV-524130: add missing mi355 counters and derived counters (#323) 
* add missing counters from public doc.
;

* add reduce sum counter for mi355 tcc, tcp, ta.

---------

Co-authored-by: Venkateshwar Reddy Kandula <vkandula@amd.com>

[ROCm/rocprofiler-sdk commit: a7f96dde29]
 2025-04-02 09:44:57 -07:00
Kandula, Venkateshwar reddy a7f96dde29 SWDEV-524130: add missing mi355 counters and derived counters (#323) 
* add missing counters from public doc.
;

* add reduce sum counter for mi355 tcc, tcp, ta.

---------

Co-authored-by: Venkateshwar Reddy Kandula <vkandula@amd.com>
 2025-04-02 09:44:57 -07:00
raramakr 7bfc49e9f8 SWDEV-521636 - Add dependent script path to system path in rocprof-compute (#651) 
In wheel environment, rocprof-compute in bin folder is not a soft link. For executing rocprof-compute from bin folder, the system path should also have the dependency script paths. Added the same

[ROCm/rocprofiler-compute commit: df2296529b]
 2025-04-02 09:41:02 -07:00
raramakr df2296529b SWDEV-521636 - Add dependent script path to system path in rocprof-compute (#651) 
In wheel environment, rocprof-compute in bin folder is not a soft link. For executing rocprof-compute from bin folder, the system path should also have the dependency script paths. Added the same
 2025-04-02 09:41:02 -07:00
Luu, Jonathan e12743fe19 SWDEV-521313 - Streamline Version Management: Retain Only version-roc… (#4) 
SWDEV-521313 Streamline Version Management: Retain Only version-rocm
File

[ROCm/rocm-core commit: cf867754b7]
 2025-04-02 11:31:48 -04:00
Luu, Jonathan cf867754b7 SWDEV-521313 - Streamline Version Management: Retain Only version-roc… (#4) 
SWDEV-521313 Streamline Version Management: Retain Only version-rocm
File
 2025-04-02 11:31:48 -04:00
Patel, Jaydeepkumar b217d3a4e6 SWDEV-508632 - Align address to 2 MBs for hidden heap allocation. (#29) 
[ROCm/clr commit: b5c9cbc236]
 2025-04-02 16:33:29 +05:30
Patel, Jaydeepkumar b5c9cbc236 SWDEV-508632 - Align address to 2 MBs for hidden heap allocation. (#29) 2025-04-02 16:33:29 +05:30
Kanangot Balakrishnan, Bindhiya af9afacfbd [SWDEV-524528] Modify the amd-smi monitor to use drm VRAM API (#228) 
Updated the amd-smi monitor to use VRAM drm API.

Signed-off-by: Bindhiya Kanangot Balakrishnan <Bindhiya.KanangotBalakrishnan@amd.com>
 2025-04-01 17:05:14 -05:00
Kanangot Balakrishnan, Bindhiya 17ed406553 [SWDEV-524528] Modify the amd-smi monitor to use drm VRAM API (#228) 
Updated the amd-smi monitor to use VRAM drm API.

Signed-off-by: Bindhiya Kanangot Balakrishnan <Bindhiya.KanangotBalakrishnan@amd.com>

[ROCm/amdsmi commit: af9afacfbd]
 2025-04-01 17:05:14 -05:00
Arif, Maisam 35fbe2cbf1 [SWDEV-521408] Fixed call to amdsmi_get_gpu_virtualization_mode (#230) 
Change-Id: I29c86f8982b53cc139004ebc06b26a5d8f430091

Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
 2025-04-01 16:57:23 -05:00
Arif, Maisam 237334ef65 [SWDEV-521408] Fixed call to amdsmi_get_gpu_virtualization_mode (#230) 
Change-Id: I29c86f8982b53cc139004ebc06b26a5d8f430091

Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>

[ROCm/amdsmi commit: 35fbe2cbf1]
 2025-04-01 16:57:23 -05:00
Jonathan Luu 6ad28c72a8 SWDEV-521313 - Streamline Version Management: Retain Only version-rocm File 
[ROCm/rocm-core commit: ab95ccf1a3]
 2025-04-01 16:46:04 -04:00
Jonathan Luu ab95ccf1a3 SWDEV-521313 - Streamline Version Management: Retain Only version-rocm File 2025-04-01 16:46:04 -04:00
David Yat Sin 2a433e2b96 rocr: Fix PC Sampling PRED_EXEC num dwords count 
Fix incorrect value for number of dwords in the PRED_EXEC command.
 2025-04-01 15:53:45 -04:00
David Yat Sin f46bc26cff rocr: Fix PC Sampling PRED_EXEC num dwords count 
Fix incorrect value for number of dwords in the PRED_EXEC command.


[ROCm/ROCR-Runtime commit: 2a433e2b96]
 2025-04-01 15:53:45 -04:00
vedithal-amd ab290f250d Weekly rebase liangdin-test on top of amd-mainline (#650) 
[ROCm/rocprofiler-compute commit: a7ebbbd41e]
 2025-04-01 14:18:29 -04:00
vedithal-amd a7ebbbd41e Weekly rebase liangdin-test on top of amd-mainline (#650) 2025-04-01 14:18:29 -04:00
Mallya, Ameya Keshava 935cf1bf60 fixed syntax to mainline 
[ROCm/rocprofiler-sdk commit: 342223cb81]
 2025-04-01 09:52:55 -07:00
Mallya, Ameya Keshava 342223cb81 fixed syntax to mainline 2025-04-01 09:52:55 -07:00
Mallya, Ameya Keshava 5fa2a43222 fixed syntax to mainline 
[ROCm/hip-tests commit: d6f98eb109]
 2025-04-01 09:52:08 -07:00
Mallya, Ameya Keshava d6f98eb109 fixed syntax to mainline 2025-04-01 09:52:08 -07:00
Mallya, Ameya Keshava 29be7230eb fixed syntax to mainline 
[ROCm/clr commit: 98f1db181c]
 2025-04-01 09:51:41 -07:00
Mallya, Ameya Keshava 98f1db181c fixed syntax to mainline 2025-04-01 09:51:41 -07:00
Mallya, Ameya Keshava 7aa37c3f93 fixed syntax to mainline 
[ROCm/hip commit: e4f1c126ad]
 2025-04-01 09:51:18 -07:00
Mallya, Ameya Keshava e4f1c126ad fixed syntax to mainline 2025-04-01 09:51:18 -07:00
Mallya, Ameya Keshava e9a978e671 fixed syntax to mainline 
[ROCm/hipother commit: 0dbfdc4182]
 2025-04-01 09:50:48 -07:00
Mallya, Ameya Keshava 0dbfdc4182 fixed syntax to mainline 2025-04-01 09:50:48 -07:00
Mallya, Ameya Keshava 19a5f25829 Fix syntax to mainline 
Signed-off-by: Mallya, Ameya Keshava <AmeyaKeshava.Mallya@amd.com>
 2025-04-01 09:47:57 -07:00
Mallya, Ameya Keshava e4d8950a0e Fix syntax to mainline 
Signed-off-by: Mallya, Ameya Keshava <AmeyaKeshava.Mallya@amd.com>

[ROCm/amdsmi commit: 19a5f25829]
 2025-04-01 09:47:57 -07:00
Mallya, Ameya Keshava b209c43419 Fix to mainline 
[ROCm/rocprofiler-register commit: b96aab5b36]
 2025-04-01 09:47:28 -07:00
Mallya, Ameya Keshava b96aab5b36 Fix to mainline 2025-04-01 09:47:28 -07:00
Arif, Maisam 307de69149 [SWDEV-520754] Fixed unboundLocalError for Mulit-VF (#225) 
Change-Id: Ib1c0826342a5882fde6ddd4f06f058462226b82d

Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
 2025-04-01 11:21:56 -05:00
Arif, Maisam 2ea49b6b33 [SWDEV-520754] Fixed unboundLocalError for Mulit-VF (#225) 
Change-Id: Ib1c0826342a5882fde6ddd4f06f058462226b82d

Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>

[ROCm/amdsmi commit: 307de69149]
 2025-04-01 11:21:56 -05:00
xuchen-amd abc1c336f6 Improve chip id logic (#648) 
* Improve chip id logic, add missing physical and virtual chip ids.

[ROCm/rocprofiler-compute commit: e77dd1a1ab]
 2025-04-01 12:18:07 -04:00
xuchen-amd e77dd1a1ab Improve chip id logic (#648) 
* Improve chip id logic, add missing physical and virtual chip ids.
 2025-04-01 12:18:07 -04:00
Mallya, Ameya Keshava 2a39be043e Removing NPI 
[ROCm/hipother commit: f9ee9b6eaa]
 2025-04-01 09:04:06 -07:00
Mallya, Ameya Keshava f9ee9b6eaa Removing NPI 2025-04-01 09:04:06 -07:00
Mallya, Ameya Keshava 2f9ca8deb2 !verify functionality 
[ROCm/hipother commit: 0b4ce00f83]
 2025-04-01 09:03:43 -07:00
Mallya, Ameya Keshava 0b4ce00f83 !verify functionality 2025-04-01 09:03:43 -07:00
Mallya, Ameya Keshava 9122c05c35 !verify functionality 
[ROCm/hip commit: b8c158d0b0]
 2025-04-01 09:01:39 -07:00