Commit Graph

281 Commits

Author SHA1 Message Date
kjayapra-amd 712987ed08 SWDEV-509280 - Combine multiple definitions of callbackQueue into a single function.
Change-Id: Ibbb56136bec2beed71c202d75e8aec9e82640a4e


[ROCm/clr commit: 0324014710]
2025-01-30 15:58:11 -05:00
German Andryeyev ae379965dd SWDEV-459826 - Add a crash dump for a failed queue
The logic can analyze the AQL queue state and
find a failed AQL packet with the kernel's name

Change-Id: I1a478fa2c25462cd07a194784958bdf22454b897


[ROCm/clr commit: ea0b092af8]
2025-01-28 14:27:46 -05:00
taosang2 590465543d SWDEV-507969 - Fix wrong VGPRs for some devices
Change-Id: Ia8fc19564272e2c7171d991376bf896a99085a97


[ROCm/clr commit: 799e54aa0d]
2025-01-22 10:11:47 -05:00
Evgenii Averin ef2a812d0a SWDEV-505769 - Fix typo
Change-Id: I2d3f65ed68157718c4439a9da7d2dcdfcbb9f93d


[ROCm/clr commit: b62995ce1a]
2025-01-08 21:31:17 -05:00
taosang2 da613fbbeb SWDEV-479958 - Support different address mode
Support different address modes in X, Y, Z directions

Change-Id: If1db5a8af33c92dd14b48968c3e8eceb97daea6c


[ROCm/clr commit: d82d6a78cf]
2024-12-23 16:39:54 -05:00
Saleel Kudchadker 7d7aa8b69c SWDEV-497145 - Use rocr copyOnEngine API for staged copies
- Refactor blit code and clean ASAN instrumentation
- Use unified function for rocr copy
- Enable shader copy path for unpinned writeBuffer/readBuffer paths
- Set GPU_FORCE_BLIT_COPY_SIZE=16 which means we will use BLIT copy for
  pinned copies or unpinned H2D/D2H copies < 16KB

Change-Id: I42045cca79234b340dbf53dafb93044199736ae4


[ROCm/clr commit: 7863eb92dc]
2024-12-04 13:38:13 -05:00
Satyanvesh Dittakavi 01c73b561f SWDEV-491967 - Add the right VGPRs per SIMD and VGPR Granularity for gfx12
- Default values are being assigned causing occupancy calculation to go
wrong without the right values defined for gfx12 ASICs
- Also added the these values for gfx1105

Change-Id: I611cc3a8ed8c57f2def637310ce1c3a48c16a574


[ROCm/clr commit: a26dc29eb9]
2024-11-01 12:47:23 -04:00
Konstantin Zhuravlyov 04628d2d1f SWDEV-428601 - Don't enforce 1 isa per device in rocm backend
- Device can have multiple isas as per HSA spec
  - First isa is most specific one, so this change is sort of a NOP

Change-Id: Ib332af21745f2e6a7c25db8986bf7717501059bc


[ROCm/clr commit: 3387f48b56]
2024-11-01 11:01:02 -04:00
Anusha GodavarthySurya 2dccb30f6f SWDEV-485904 - propagate hsa_amd_vmem_address_free error to hip API
Unit_hipMemSetAccess_GrowVMM test fails with
HSA_STATUS_ERROR_RESOURCE_FREE silently

Change-Id: I7a78410e432de4a2e877062782abf8761645f392


[ROCm/clr commit: b498103f9b]
2024-10-21 10:12:32 -04:00
Saleel Kudchadker b9497ea70e SWDEV-301667 - Enable ROCr logging
- Use AMD_LOG_LEVEL=5 to dump AQL packets in ROCr

Change-Id: I2c044a5304c4eaf3d3af20e62d1f54c98d4fbaa4


[ROCm/clr commit: e36666e536]
2024-10-04 19:22:12 -04:00
German Andryeyev f8fc11c2d8 SWDEV-483586 - Unblock staging H2D transfers
Although unpinned copies require synchronizations
in HIP, runtime can avoid syncs for H2D copies with
a staging buffer

Change-Id: If2203c6bc0cbd89742823688dc8e89e9acd873b2


[ROCm/clr commit: 29cc678d8d]
2024-09-21 10:25:27 -04:00
Maneesh Gupta e87bf2096d SWDEV-485179 - Revert "SWDEV-459254 - Overwrite cacheline size to 256 for gfx12, as it is used for kernarg alignment."
This reverts commit 1f63650bf96e01e48f879aa58b80e2130dd4a567.

Reason for revert: <INSERT REASONING HERE>

Change-Id: I6d7ed87c09d9b77116548dce1f30ac4711c2c09d


[ROCm/clr commit: 2d1c6ee23e]
2024-09-20 11:33:34 -04:00
kjayapra-amd f19260d568 SWDEV-480772 - Remove name variable from amd::Monitor class.
Change-Id: Ie2a4fa44f485786227230f8a892e090e718aa30e


[ROCm/clr commit: 12a39fbf22]
2024-09-19 11:55:01 -04:00
kjayapra-amd eecbcddaf3 SWDEV-439234 - Access check before memcpy and kernel operations.
Change-Id: I7057125c03460db205409e19980145298c190fe2


[ROCm/clr commit: 6211037f63]
2024-09-06 14:30:00 -04:00
Rahul Manocha c430e1c44d SWDEV-478921 - Destroy Queue created by Coop Launch
Change-Id: I7f31ce05421479ff1de138cae26aafa071e956e2


[ROCm/clr commit: ddbd7039b0]
2024-09-02 02:35:08 -04:00
kjayapra-amd a064de92b8 SWDEV-464828 - Initial implementation of VMM IPC on PAL/Windows.
Change-Id: I3d5e148fad9105704db6724b00df06bef4fc9d2f


[ROCm/clr commit: e7a7feb273]
2024-07-16 10:38:35 -04:00
Satyanvesh Dittakavi da5bff9464 SWDEV-471935 - Destroy hsa queues with cumask set
Fixes the memory leak with hipExtStreamCreateWithCUMask API.
hsa queues with cumask set are not being reused and created
everytime the API is called, But these queues were not being
destroyed during hipStreamDestroy causing memory leak.

Change-Id: Ibfbe019bbd73604e98eca80461efe53fa64bb701


[ROCm/clr commit: 191869b252]
2024-07-16 10:02:42 -04:00
Julia Jiang 3c7ae28776 SWDEV-472710 - Adding gitattributes and remove trailing spaces
Change-Id: Ic8ad2071745f0ffe6a2e120bfebb6d90bf270f87


[ROCm/clr commit: dd30e0e893]
2024-07-15 12:39:56 -04:00
Ioannis Assiouras f3a77127b4 SWDEV-472309 - Check if vmm support exists before enabling vm in mempool
Change-Id: I6ae2fb18a306595e0f3a56e144658a4a720e7a37


[ROCm/clr commit: 0053584aac]
2024-07-12 10:11:03 -04:00
taosang2 20417d5b0f SWDEV-467540 - Fix reference of freed locks
1.Move global amd::monitor listenerLock before global
class runtime_tear_down as it will be referenced in
~RuntimeTearDown() after main(). It should be freed
later than runtime_tear_down.

2.Update  Device::~Device() to SVM free coopHostcallBuffer_
before context_ is released and freed.

Change-Id: I1d21378ff463477d3238d71e5e2a1a7d6b9147ad


[ROCm/clr commit: 544c45364f]
2024-06-18 13:58:36 -04:00
Anusha GodavarthySurya 291f079669 SWDEV-467102 - Hidden heap init for graph capture
If the graph has kernels that does device side allocation,  during packet capture, heap is
allocated because heap pointer has to be added to the AQL packet, and initialized during
graph launch.

Handle race with wait when 2 kernels with device heap are enqueued on multiple streams.

Change-Id: I45933b77fcaf7bc8fdf1bc906462e32b5d8d3688


[ROCm/clr commit: 57156c524d]
2024-06-17 02:07:25 -04:00
Satyanvesh Dittakavi 30c4d5805e SWDEV-464927 - Update the Get by PCI BusId logic and Hop count
- Update the intra socket weight for partitions within single socket as
it is changed to 13 by the driver.
- Use the PCIe function to distinguish the partitions of the same device
such as TPX mode in gfx942.

Change-Id: I8e64023d44e37c2dbb105cbb343441a48021ba7b


[ROCm/clr commit: 1815fc808d]
2024-06-10 04:46:50 -04:00
Ioannis Assiouras 75104df3b2 SWDEV-464648 - code and comment cleanups
Change-Id: I5ba3f1bff500b3cd5903c2f441017735e688f83f


[ROCm/clr commit: 8f42ad6aa3]
2024-06-07 22:38:09 +01:00
Ioannis Assiouras 407d1346f2 SWDEV-463865 - changed device,roc and pal namespaces to be nested under amd
Change-Id: Icad342843c039c634e249a13a7aa31400730b1dd


[ROCm/clr commit: 775dc204aa]
2024-06-07 12:23:06 -04:00
kjayapra-amd ea36bc11ce SWDEV-464455 - Init Segment flags and check for valid segment before passing to hsa APIs for allocation.
Change-Id: Ibe640093acdb7856115b6a4109bcf010adf20353


[ROCm/clr commit: 1590b39f9e]
2024-06-07 10:40:57 -04:00
Ioannis Assiouras 0e023d1a0a SWDEV-463865 - symbol renamings to prevent conflicts in static build
Change-Id: Id7fbb638c1088c23df52fee877cd790d637b1ffb


[ROCm/clr commit: b8c2ac4de4]
2024-06-06 04:05:55 -04:00
Lang Yu efc7e66c29 SWDEV-461525 - Add vgprAllocGranularity_ and vgprsPerSimd_ for gfx1150/1
These are missed for gfx1150/1.

Change-Id: I03d997e451d15a01a961e6597f805f634e5c3ae7
Signed-off-by: Lang Yu <lang.yu@amd.com>


[ROCm/clr commit: a0127c9eea]
2024-05-31 21:53:25 -04:00
Alex Xie b1cd519cc9 SWDEV-462635 - 256 byte image memory alignment
Change-Id: I1d21368ff460477d3238d71e4e2a0a7d6b9167ac


[ROCm/clr commit: 80011685b2]
2024-05-29 10:37:27 -04:00
Ajay 5b731168ca SWDEV-439581 - hip event flags clean up
Change-Id: I2197762d912da41a8b53b32b3446f0a958c988a6


[ROCm/clr commit: 6ec5074d74]
2024-05-28 06:31:10 +00:00
Ajay cea4f4290a SWDEV-439581 - hipEventBlockingSync flag for hip events
Change-Id: I0d7785a568f8007f82f999776a7ad23d0acc81b7


[ROCm/clr commit: a5a4b78606]
2024-05-28 06:31:10 +00:00
Vladana Stojiljkovic c05056e695 SWDEV-452364 - Check if no GPUs are available when hsa_init fails
* When no GPUs are available, hsa_init fails with HSA_STATUS_ERROR_OUT_OF_RESOURCES, and device and runtime initialization fails. In order for NoGpu tests to pass, true needs to be returned which will cause HIP_INIT_API to return proper error hipErrorNoDevice instead of hipErrorInvalidDevice.

Change-Id: I982d4416c92ed1b36893354d8b10d73df34f2478


[ROCm/clr commit: fdaa7141af]
2024-05-28 06:31:10 +00:00
kjayapra-amd 04ed74552f SWDEV-459254 - Overwrite cacheline size to 256 for gfx12, as it is used for kernarg alignment.
Change-Id: Ia6acf312ee84f6dde1c830fc21f10d3a8a9de5ee


[ROCm/clr commit: dd1dd86fd7]
2024-05-28 06:28:17 +00:00
Jaydeep Patel ab70925687 SWDEV-456279 - Adding new hip flag to access contiguous memory and pass the flag to HSA API.
Change-Id: I1bafeaa3096395c729723af958d609bc41e7845c


[ROCm/clr commit: 1d48f2a1ab]
2024-04-30 05:25:38 -04:00
Ioannis Assiouras 2f430138c5 SWDEV-451594 - Implement Readback and Avoid HDP Flush workaround for device kernel args
Change-Id: I6d41a089a17f55306e7ff402588a1e831b20a7a7


[ROCm/clr commit: bf74ef4025]
2024-04-19 09:29:20 -04:00
kjayapra-amd 71aa6ff3a0 SWDEV-413997 - VMM IPC implementation for Linux.
Change-Id: Icfeb83ca51e96be35abb67a94d6e3e1a1ca5a934


[ROCm/clr commit: 56ebf5157a]
2024-04-18 11:28:13 -04:00
German Andryeyev 7f195e2996 SWDEV-444670 - Enable teardown class
Force implicit runtime teardown with a global destructor.

Change-Id: Iabe63dedf5b94fefc98668585c45a61607120669


[ROCm/clr commit: c95a75a2bf]
2024-04-16 12:00:06 -04:00
Rakesh Roy f7dc86bdf4 SWDEV-453180 - Add UUID support for HIP_VISIBLE_DEVICES on Linux
- UUID is Ascii string with a maximum of 21 chars which uniquely identifies a GPU
- Convert set UUID in HIP_VISIBLE_DEVICES to device index internally
- Then use existing device index logic for HIP_VISIBLE_DEVICES

Change-Id: I8cab4fe42459f8209b97f909300789e6e687b9ac


[ROCm/clr commit: 52db98edd9]
2024-04-13 22:07:19 -04:00
kjayapra-amd 765e6f5d2f SWDEV-413997 - Fixing multiple device cases.
Change-Id: I10ad3fbfca887e92cd81f68392fa1acf753cbd2b


[ROCm/clr commit: d52d16c8e6]
2024-04-13 06:14:03 -04:00
kjayapra-amd ed9c629ad6 SWDEV-446298 - Adding error code to the logs on p2p hsa api failure.
Change-Id: Ic41b1ad1b64cca0e31986337a83a5146d52a7328


[ROCm/clr commit: 2b8634bada]
2024-04-10 06:00:00 -04:00
Saleel Kudchadker 4285981222 SWDEV-301667 - Fix SDMA mask reuse
If we are using the mask returned by getLastUsedSdmaEngine() then we
need to apply the SDMA Read/Write mask to it before using with HSA
copy_on_engine API.

Change-Id: I6e5dc6c187eeb3c61ee159e9d2a0fa7b4737c06e


[ROCm/clr commit: 3f0bcf7834]
2024-04-08 15:42:52 -04:00
Sourabh Betigeri 7cc5dd56ab SWDEV-451964 - Limit gpu single allocation percentage for gfx940 only
Change-Id: Iadcdadd734e7aeeb23742e426353defa972d3ad5


[ROCm/clr commit: dbac2976e4]
2024-04-05 09:43:42 -04:00
kjayapra-amd 0f8a9567e6 SWDEV-413997 - Save hsa_handle as ptr in hipMemCreate path.
Change-Id: Ica32017ef7b00326dfb6d1f604e126d40ad5b786


[ROCm/clr commit: 5cbd74b554]
2024-03-26 10:24:29 -04:00
Ioannis Assiouras b46d3c0f8d SWDEV-451166 - Disable kernel args for non-XGMI if HDP flush register is invalid
Change-Id: I227e046e2b9cb25476a50240f5d070adbd558f21


[ROCm/clr commit: 96f5c44851]
2024-03-15 05:27:52 -04:00
kjayapra-amd 8947420e41 SWDEV-423835 - Fixing kernel launch issues on Virtual Memory Management path.
Change-Id: I9f5e8a3d83af3809b2c50b21a10697e26113dd23


[ROCm/clr commit: f5ca620baa]
2024-03-12 17:22:07 -04:00
Saleel Kudchadker 4ff5ec0a02 SWDEV-301667 - Better log
- Print SWq for AQL packets, this helps correlating a stream to the HWq
mapped

Change-Id: I610430c0872a1abc6636027c00163ec46983cd65


[ROCm/clr commit: 984c86f407]
2024-03-01 16:43:06 -05:00
Ioannis Assiouras 80ddb8e4eb SWDEV-446399 - Fixed segfault in hipMemSetAccess
Change-Id: Ia1200d9bee03e8abade211287505f081e635ceec


[ROCm/clr commit: 1f6d416684]
2024-02-20 18:51:05 -05:00
kjayapra-amd bef39a9369 SWDEV-437832 - Changes to update host unified memory and iommuv2 flags.
Change-Id: I88998cf57c21fc446fa28e250f826c607923670b


[ROCm/clr commit: 7d5b4a8f7a]
2024-02-07 06:27:47 -05:00
Saleel Kudchadker 423887c6f6 SWDEV-301667 - Better log
Display queue base pointer in the log. This can be co-related with AQL
packets

Change-Id: I544f9b6db6ae01c85e57e4b3f0b3fffefcd7c2ed


[ROCm/clr commit: 0567c3b720]
2024-02-05 05:08:11 +00:00
kjayapra-amd 9bff044c87 SWDEV-437832 - Adding device property to check if the device is accelerator.
Change-Id: I8349e99c03422c268bbb60a8c143bd492d9cec09


[ROCm/clr commit: b366a7c992]
2024-02-05 05:08:11 +00:00
Satyanvesh Dittakavi d1901f2017 SWDEV-434846 - Limit the gpu single allocation percentage for all MI300 versions
Change-Id: I33dea3eaab249ce3f9a624d38267489f99cd530c


[ROCm/clr commit: 755eb2962c]
2024-01-03 23:47:44 -05:00