Remove targetId_, gfxipMajor_, gfxipMinor_ and gfxipStepping_ from
device::Info as they are now available in device::Isa.
Change-Id: I381b1d4798ebf50655740e004a01ac7f86dbf668
[ROCm/clr commit: c2308216dd]
- Correct GSL path to report targets using the TargetID syntax.
- Correct GSL path to check compatibility of code objects when
loading.
- Add concept of an device isa and create a registery used by ROCm,
PAL and GSL.
- Support XNACK and SRAMECC target features consistently for PAL and ROCm.
- Correct logic for NullDevices and asserts to avoid memory coruption.
- Allow all NullDevices to be created for HIP.
- Numerous other code improvements.
Change-Id: I40abf3d2b22249c1492d1af5919665f8184f4e0e
[ROCm/clr commit: c7e8d91e14]
Use strncpy instead of strcpy to ensure the arrays will not be
overflowered. Only copy one less than size of char array to leave a
NUL character at the end even if the copy is truncated provided the
original object is zeroed memory.
Change-Id: I00f7679630cf28dcb9a51cb0aba2810a4f4c72b9
[ROCm/clr commit: e0448535a3]
roc:Settings and pal::Settings are derivations. Allocate them as their
derived class then assign that to the base class member to avoid the
need for a static_cast.
Use device::settings to access the Settings consistently.
Change-Id: I0f85157962fbf6fed176da0caf83b723bcbe1452
[ROCm/clr commit: 583dddf6b6]
A device's offset in Pal::AsicRevision could be changed from time to time, while the current implementation assume the offset never changes.
Change-Id: Id993512aa0da6e0b2356f594d5e58f76d1f97f16
[ROCm/clr commit: b1d75637bd]
This is helpfull to do when debugging issues on lowend asics. Navi14 can be emulated as Navi10. So can Navi22 be emulated as Navi21.
Change-Id: I693ffd45a5b03657822afdc872781901bc69b65c
[ROCm/clr commit: 26d1b28b16]
SWDEV-245906
All asics will still be supported for developer builds.
Change-Id: I0eac2246162d133fe63449c200d996fe05bd51bd
[ROCm/clr commit: 24c1c48db7]
- Problem with CL_DEVICE_GLOBAL_FREE_MEMORY_AMD query.
Check if allocated memory exceeds the total size.
Change-Id: Ieed8829860663bac1acfa41d21309dff4d8772c7
[ROCm/clr commit: e289ebdf20]
Each WGP consists of 2 CU, so the number of available SIMD units is doubled.
Change-Id: I43978a8a9139c33f5f776b344a36bee927cc187d
[ROCm/clr commit: e76d867740]
Add MS HWS support. PAL reports just one compute engine
in that mode and runtime needs extra logic to detect RT queues.
Change-Id: I011f1f1b18dec6a7195a4f1fe939f8029bc269ae
[ROCm/clr commit: 622c714165]
hip_threadfence_system passes locally with this change. This also fixes
hipHostMalloc() failures when hipHostMallocMapped flag is used.
Change-Id: Id412efe502accc7c6e7676b52c05ccb9d8fbbe67
[ROCm/clr commit: 5de65ba4a0]
The last commit to replace the cl_* types with standard types
failed to correct issues introduced in the PAL and GPU backend.
Change-Id: I926997234dfbe346fc165a7bc4e1b8aabab7bac5
[ROCm/clr commit: b81816f482]
Tony Tye
Jason Tang
Vladislav Sytchenko
Rahul Garg
Jason Tang
German Andryeyev
kjayapra-amd
jujiang
Saleel Kudchadker
Laurent Morichetti