gfx9 has passed qualification. gfx8 stability is under investigation.
Change-Id: Ia72211d47756399ecdfceafeb67c2ab34ebda834
[ROCm/ROCR-Runtime commit: 5db53ceda1]
The trap protocol changed between gfx8 and gfx9. The return address
is in trap temporaries [0,1] on gfx9 rather than [4,5] on gfx8.
Unfortunately SP3 changes the meaning of the ttmp register aliases
in gfx9, further confusing the issue.
Clean up later when LLVM assembly build is introduced to the runtime.
Change-Id: I84ea9bf3736f060dd95d0361f9d5a0f9a3576178
[ROCm/ROCR-Runtime commit: f0a1c7c4c6]
Informs, in debug mode only, that a signal wait violated the HSA
spec with regard to the consuming agents list. This list is used
for optimized signal type selection.
Change-Id: I5879f8f822d01af504ab913482b2532feb00be98
[ROCm/ROCR-Runtime commit: 2824786b3b]
When a new enough microcode build is running use a vendor AQL packet
to submit the PM4 IB.
Change-Id: Icd3e2b322c418477420ba4a29f4455ce340ef0d2
[ROCm/ROCR-Runtime commit: 4d62b9482a]
Should point directly to amd_queue_t.write_dispatch_id. Only noticeable
with HWS enabled which is not yet stable.
Change-Id: I169906d45225379a3ca2729ff04d298fdbb9a9fb
[ROCm/ROCR-Runtime commit: 28f51d5808]
- Build system fixes
- No user-mode high-precision timer by default, use clock_gettime
- Use C11 aligned_alloc pending C++17 std::aligned_alloc
Change-Id: I268365bdfd11d1e817a89584b9e086ee5b86e1dc
[ROCm/ROCR-Runtime commit: 9e575ea96a]
Gfx9 requires monotonic write pointer and doorbell.
Cound fields are 1-based compared with 0-based pre-Gfx9.
- Restructure implementation to use monotonic ring indices
- Remove redundant submission size checks (handled by AcquireWriteAddress)
- Unify copy/fill per-command limit (documentation is unclear)
Change-Id: I57c1675221d2e63aa319fee700d9951671e1bd65
[ROCm/ROCR-Runtime commit: 1cd46afe6d]
Note: Implementation same as 1.0 APIs for now.
The followup change will have the complete implementation.
Change-Id: Ife633f74ff27eee0bb9b0c46952cf5233b0114e8
[ROCm/ROCR-Runtime commit: a324f21a46]
Currently HSA HW Profiler is failing to build due to this patch
This reverts commit 91866d4bbb.
Change-Id: Iabb2b958f33ba614a24b61bb370905b3b7362708
[ROCm/ROCR-Runtime commit: 5162a76616]
Initial work to import the latest (1.1) hsa_ext_image extension.
Change-Id: I4d55adb09ba4d4dbd43d47a4bc54077d4bc531d2
[ROCm/ROCR-Runtime commit: e0ce8855dd]
Also emit error messages to stderr if no async queue error callback was registered and queue fault messages are enabled (on by default).
Queue fault messages are controlled with env key HSA_ENABLE_QUEUE_FAULT_MESSAGE.
Change-Id: I496487b8d048b83aa95b9784e92928211f167b17
[ROCm/ROCR-Runtime commit: 0e17cc2887]
Uncommented HSA IPC code.
Changed hsa_amd_ipc_memory_t to be 8 uint32_t's instead of 9 to
match spec
Change-Id: Id1523125e9b876a23c3743df1be29c98b47f6725
[ROCm/ROCR-Runtime commit: 160f8c5880]
Ensure that the write index and ring buffer contents are visible
to the HW before sending the doorbell. The latter is a write-combined
MMIO store and must be ordered with prior cacehable non-MMIO stores.
Also be more explicit about memory semantics for doorbell stores.
Change-Id: Ie4d96a7ee2a507237a8dbe7705fdf234d62ce9ba
[ROCm/ROCR-Runtime commit: d5b4078072]
If we issue too many copy commands without syncing and wrapping happens,
we need to wait for the blits to be done before moving forward otherwise
we will overwrite the kernel args of the blits in flight.
Change-Id: I9a21e31ce07f8e8157ca38e96dc264ff47fd3639
[ROCm/ROCR-Runtime commit: 5519c96b74]
Konstantin Zhuravlyov
hthangir
Jay Cornwall
Sean Keely
Christophe Paquot
Konstantin Zhuravlyov
Ramesh Errabolu
Kent Russell
James Edwards
Chris Freehill