The "optimized" version of memcpy is outdated and
was used in win32 only.
Change-Id: I7f2e0e9051e37cec95438266824b5b0025c324c6
[ROCm/clr commit: 7448113cfc]
- UUID needs to be specified in the format GPU-<body>, <body> encodes UUID as a 16 chars
- Convert set UUID in HIP_VISIBLE_DEVICES to device index internally
- Then use existing device index logic for HIP_VISIBLE_DEVICES
Change-Id: I654f492a49cd4d7a9b7339360ab558165240caa5
[ROCm/clr commit: fb217fa9e0]
Avoid a deadlock on the host call buffer creation. Since the buffer will be
allocated in the queue thread, then use direct device memory allocation
skipping the global context lock.
Change-Id: I09b55ee03bb42ab5d320c152b52a8c842c5fdcc1
[ROCm/clr commit: 62559a6e5a]
When large bar is enabled, persistent memory leads to overallocation for 32 bit architecture.
Change-Id: Iae39359d8128588de02e42d77fe58e868b8e71fd
[ROCm/clr commit: bc80802c1a]
The new logic has a lock for PAL call and doesn't require the lock for queues.
Change-Id: I61b67c3c4abd2ede44809de1d6beed756766032e
[ROCm/clr commit: 2f3ad43c4a]
alwaysResident setting doesn't require per queue residency tracking.
Thus, the logic can be skipped to avoid the lock of queues.
Change-Id: Ib5cff5b79d3ecb8c2f2eb2565cf069f9a69438b0
[ROCm/clr commit: 95e3958748]
- Create a vector to allow multiple TS to be stored in Command.
- This would mean we dont wait for entire batch in Accumulate command
to finish when we exhaust signals.
- Reduce the number of signals created at init to 64. This min value
may still need to be tuned but the KFD allows max of 4094 interrupt
signals per device.
- Store kernel names whenever they are available and not just when
profiling. If we dynamically enable profiling like for Torch, a crash
can happen if hipGraphInstantiate wasnt included in Torch profile scope
beacuse we previously entered kernel names only when profiler is
attached.
Change-Id: I34e7881a25bbc763f82fdeb3408a8ea58e1ec006
[ROCm/clr commit: c157bfb202]
PAL optimized the logic for the barriers, which caused failures with CP DMA on Navi4x.
Change barrier's code to match the most recent PAL optimizations.
Change-Id: I55eeab20f51eb8e920bcbb4b55fbe3c7f77fd3fa
[ROCm/clr commit: 1239309c90]
- Sometimes we want to mask out kernel names, use right level for kernel
logging
Change-Id: Ideae9647c57b86ae390ff2f4131f6d8c6df5c086
[ROCm/clr commit: f1adecd186]
OpenCL printf handling did not process vector of half precision floats properly
(mainly because compiler packs 2 halfs into a dword and runtime failed to extract the
individual parts).
This patch fixes the issue.
Change-Id: Ia1f15ccfb5db52b71c43cfd588dd38f551ee5277
[ROCm/clr commit: 6f390f5af9]
__amd_streamOpsWrite blitkernel in device-libs has only 3 args.
so getting rid of the 4th unused arg (sizeBytes)
Change-Id: I81cc1107f8b424bf58558c93a2495a1b878aef91
[ROCm/clr commit: e643406caa]
With multiple HIP streams it's possible to have a race condition when
one thread stops the traces, but another still performs submisisons.
That may cause a crash on the barrier callback.
Change-Id: Ic56f8277fcfd2c2142a4821d927b938b9f313add
[ROCm/clr commit: e2d2fad56c]
Latest VidMM can provide free memory available on the system.
Use PAL interface to report free memory on the system instead
of per process.
Change-Id: I0e78b9d340299c16829177a8c5182d21cc353384
[ROCm/clr commit: bfa469ddc4]
This reverts commit 1b05247a03.
Reason for revert: Waiting for staging results before finally merging it.
Change-Id: Iaabb510325f50147f368108e98531291217627c0
[ROCm/clr commit: 77be355fd9]
Extension allows to execute the kernels without a wait barrier and L1
invalidation.
Change-Id: I96c485204303f54a0240b93134f4560673e4bd17
[ROCm/clr commit: 13c6f56ca9]
Recently some unused compiler options for HSAIL path were removed,
but it affected blit kernels compilation. Hence, remove those options.
Also delete assert for device to device copy in SDMA path for now.
Change-Id: Ib5d7f063af2ab4a3fc5d73d426e39c391b1011ac
[ROCm/clr commit: eaa61fc740]
Luxmark still uses HSAIL path and one subtest can benefit from the wave limit.
Change-Id: I16c94e09cd6e2afd6341cb76bf2e9ab7b7713214
[ROCm/clr commit: dec1158d04]
Single OCL context with multiple devices should use direct map
even with persistent memory, because cache coherency layer.
Change-Id: I02a48830440203a1dea176acd4dff4452b70f133
[ROCm/clr commit: 49037b9762]
- Make sure persistent memory from resource cache is properly adjusted
in free memory calculation.
Change-Id: I74ef68975ccde4694fb1cb904617c418e85dfc9f
[ROCm/clr commit: 85c15d720d]
Add GPU_DEBUG_ENABLE to control ttpm behavior. If enabled,
then HW will collect more debug info at some perf cost
Change-Id: Icee0686b903a7b1bd483710b9d611877cd43c6aa
[ROCm/clr commit: 7d661bc7df]
Extra CPU read back will be performed before every submission to make sure
previous writes over PCIE reached GPU. HDP flush is done by CP.
Change-Id: I402d28ca26c8cee4a3920feb3599af8c285d0889
[ROCm/clr commit: cfc07c88ee]
Persistent memory should use direct access for write map and
indirect for read map.
Change-Id: I9fc84836d60088b24012ed25f7ef8c16e33796a3
[ROCm/clr commit: c8b3253a24]
German Andryeyev
kjayapra-amd
Payam Ghafari
Konstantin Zhuravlyov
Rakesh Roy
Ioannis Assiouras
taosang2
Jaydeep Patel
Sourabh Betigeri
cadolphe
Saleel Kudchadker
Vikram
Ajay
Anusha GodavarthySurya
ksankisa