Possibly because of moving to gart table for vram access from Kernel.
This test failure shouldn't be a blocker. Temporarily blacklist till a
solution is found.
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I99725f368aced863188e30f619288ad4d033b9a6
[ROCm/ROCR-Runtime commit: e35778ed4d]
Set the KFD_IOC_ALLOC_MEM_FLAGS_COHERENT flag and
KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED flag to allocate
uncached coherent memory when HSA_DISABLE_CACHE
environment variable is set. At KFD driver,
Single KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED flag is
not sufficient to allocate uncached memory. We
have to use both two flags to allocate uncached
memory.
Change-Id: Ie490f37b2e696314e60048f5b1b57442431696e9
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
[ROCm/ROCR-Runtime commit: ae0e74095e]
Three kfd subtests are added to verify new XGMI connection with
cache coherence HW link on A+A.
Signed-off-by: Eric Huang <JinhuiEric.Huang@amd.com>
Change-Id: I6960ec91cbfb696c4e6acb3b79fd83107003acdd
[ROCm/ROCR-Runtime commit: 9aa521d1ff]
In A+A all system memory is mapped as NC. So add a new function
gfx9_PollNCMemory which will support NC memory.
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I097b95fb156f73d6f480cd4fd262cc6fa5933f69
[ROCm/ROCR-Runtime commit: 085005f07b]
destBuf is mapped as cached, the intruction flat_atomic_add
operates on cache that cause test failed. Adding scc modifier
in the instruction will fix the issue.
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Change-Id: I8e138f93ae4f5e23020e3ac1549ef924968a74c5
[ROCm/ROCR-Runtime commit: f7759df6e0]
The three kfdtests have been fixed, so remove them from
filter list.
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Change-Id: I101a72476970a9d105e8c0b5c022847757fdd316
[ROCm/ROCR-Runtime commit: 3a378fcf0b]
Before gfx90a, coherent memory is uncached. So it was reasonable
when environment variable HSA_DISABLE_CACHE is set, memory is mapped
as coherent. On gfx90a, coherent memory can be cached, so mapping
memory as coherent can't guarantee memory is uncached. When
HSA_DISABLE_CACHE is set, we have to map memory as uncached.
Change-Id: Ia5ed4cf0ad6aef5644dc8c9e6632b52d606f06f4
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
[ROCm/ROCR-Runtime commit: f132fb2cd0]
Refer to commit "Mark buffers accessed by CP as UC"
A+A buffers are mapped as NC. CP (PM4Writes) need ReleaseMem function to
ensure the write go through to the memory
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I4ee55a6e40fba078f5950d95c8fee7ee076260bf
[ROCm/ROCR-Runtime commit: 57f46b53ec]
Refer to commit: " Mark buffers accessed by CP as UC"
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I1816e035dbb3178f28f5e34b050c20ecca282060
[ROCm/ROCR-Runtime commit: 0e8500b886]
This change might be redundant if ROCr takes care of it
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I7b67143a8ad21baa61b7eda7b8e5fe0ac1e33830
[ROCm/ROCR-Runtime commit: 10674916e4]
This change is for the A+A bring-up branch as it needs to made more
generic to handle all ASICs.
For A+A all the system buffers are mapped as NC (non coherent) unless
explicitly marked as UC (uncached). The coherency is then expected to be
handled by shader by explicitly using acquire/release instructions.
However, CP doesn't have same feature. The buffers used by CP thus have
to UC. For now queue buffer and Signal handler memory is marked as UC.
This change shouldn't affect other ASICs since Uncached flag is not used
in those. However, this change still need to be made more generic.
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I56c37a809913f7f08c94d01b0572d0f4864939aa
[ROCm/ROCR-Runtime commit: 7c05c5240f]
On gfx9, the maximum number of wavefronts per queue is the minimum of
40 waves per compute units, or 512 waves per shader engine. On gfx10,
there can only be 32 waves per compute units.
Signed-off-by: Laurent Morichetti <laurent.morichetti@amd.com>
Change-Id: I148d1a4fe6c07cdbfaa1f77939eb29311c81c008
[ROCm/ROCR-Runtime commit: 4cf11c3a7e]
Reserve some space in the context save area for the debugger's
use. There should be 32 bytes per wave for a given queue.
Change-Id: I65ddb6123d0f6afd3149844617ad19023009101d
[ROCm/ROCR-Runtime commit: a83f9b67ce]
Temporarily blacklist some tests on gfx90a until they are solved.
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Change-Id: I87cc3a996ea7d55ed8f20f5b4eecfd8bb691effd
[ROCm/ROCR-Runtime commit: e342c9c890]
On every new asic with new stepping, we need to manually relax this
checking. This check is not very helpful. Delete it.
Change-Id: I11f813023ca2566d82f6d11121d4be38c296674b
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
[ROCm/ROCR-Runtime commit: 1f05b54dc9]
Due to cache coherence change, the remote vram mapping is changed
to cached, the written value by remote shader will not be read by
local shader. So the test will fail.
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Change-Id: I2b64e8a30bed0066e159bad9bb7febae5ebe84aa
[ROCm/ROCR-Runtime commit: ec7ba38b23]
XNACK API for GPUs that support this mode. This API
makes calls to amdgpu driver to configure xnack mode.
It supports set xnack mode and query the current mode used.
Change-Id: If865fd0e3f900f008243dc49504e1a0694e1791a
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
[ROCm/ROCR-Runtime commit: 3f45f602d4]
Add function definitions to support SVM (shared virtual memory)
and xnack set.
Change-Id: Ia97ad9d0c449d8d500d799f702e1a58e87d65a56
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
[ROCm/ROCR-Runtime commit: a352639df5]
Add svm (shared virtual memory) range and xnack mode
APIs.
Change-Id: Ibd8d7fe566dc200730da0c892caa71aad7589ebd
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
[ROCm/ROCR-Runtime commit: 5ae49f2321]
strlen(src) should not be used as the length in strncpy. Use memcpy
since we know the length of the string, and ensure that we
NULL-terminate regardless of length
Signed-off-by: Kent Russell <kent.russell@amd.com>
Change-Id: I21cc6d106510c69464e7ac9d3fc7da3a1e6d1a68
[ROCm/ROCR-Runtime commit: 731a06c704]
The largebar check will exit exceptionally from test
when destination node is not set.
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Change-Id: I8bf0fed613250cc71468208e645fc562fb1a8757
[ROCm/ROCR-Runtime commit: 18ead8815c]
Update build script and CMakeLists_sp3.txt file as SP3 directory
structure has changed.
The SP3 source code with gfx90a suport is merged into a
new branch mukjoshi/sp3_gfx90a.
Please make sure to checkout this branch before using the
build script to generate the static library.
Change-Id: I2bf0ade8b2d254cd7648cc8a6d69a83ee51344cd
[ROCm/ROCR-Runtime commit: da3abfb0f8]
Add updated SP3 static library with support for gfx90a and
also add initial corresponding changes in kfdtest.
Change-Id: I71bc6404ace7f9bf0dd74e712287136aa2b8a03d
[ROCm/ROCR-Runtime commit: c861873dae]
Given the chance of local memory breakage is so high on emulators, we
should use this simple test to check the local memory function.
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Change-Id: Ifc48c12e11d75cc777ed7ea13e03bf54c2458e12
[ROCm/ROCR-Runtime commit: 690a148427]
PKG_CONFIG_PATH environment variable should be set to
<rocm_path>/lib/pkgconfig, because the *.pc file is located there.
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Change-Id: Iec503b1c2409987e52fd88fea160c70762686a28
[ROCm/ROCR-Runtime commit: 33c34506fa]
It is to provide an option to map specific memory as
uncached on A+A HW platform.
Signed-off-by: Eric Huang <JinhuiEric.Huang@amd.com>
Change-Id: Ib665cb306a0e78aba3ea5ee2f0e46cb62ae139f8
[ROCm/ROCR-Runtime commit: 2464bfc714]
This will give out more info.
Change-Id: I407422b84bebdf39a886c57736093a035ff02118
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
[ROCm/ROCR-Runtime commit: 8881075ab2]
Test for HQD preemption during stalled context restore. Added for
regression testing against new microcode.
Change-Id: I13eb7d1c598062390e12cf8a5237e53b6489f232
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
[ROCm/ROCR-Runtime commit: 526afa8394]
The purpose of this patch is to add a missing device ID for gfx1030.
The missing ID "0x73A1" is now added to the "topology.c" file.
Signed-off-by: Ori Messinger <Ori.Messinger@amd.com>
Change-Id: I05a8a55e2c46f941a039fa72a6a5e76bf2a52736
[ROCm/ROCR-Runtime commit: 46c94662b7]
Inside Docker, when limit GPU number to one, it may cause node
numIOLinks bigger than total node number.
Signed-off-by: Gang Ba <gaba@amd.com>
Change-Id: Ib84f2f05f8e0c70e48b9043b79aec02b5a214bbe
[ROCm/ROCR-Runtime commit: 7652932c38]
The MMBench issue has fixed by patch:
kfdtest: Take vram size into account when calculate buffer number
So it can remove it from kfdtest blacklist now.
Change-Id: Ib918bca72adf28f4082248fae1e3287d395c32bf
Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
[ROCm/ROCR-Runtime commit: 18d9cca879]
This patch is to add Cezanne/Lucienne support on thunk.
Change-Id: Icd9b9913fa87bbfe6c71b36a2892d6ddb73e3ddd
Signed-off-by: Prike.Liang <Prike.Liang@amd.com>
[ROCm/ROCR-Runtime commit: 7e184ebb3a]
Merge in topic branch to enable address sanitizer and CLANG compilation
support into amd-staging branch
Change-Id: I3fcd24c6fac83d0619bef4cbbc56fd95e9fb009d
Signed-off-by: Kent Russell <kent.russell@amd.com>
[ROCm/ROCR-Runtime commit: c742764d01]
The %{dist} suffix is part of the package name due to
CPACK_RPM_PACKAGE_RELEASE_DIST, but the string provided to the
"REQUIRES" field lacks it. Add it in here so the devel package can
reference the thunk package correctly. Use a nice function suggested by
Cole since CPACK_RPM_PACKAGE_RELEASE_DIST has caused some infra issues
in the past
This works for packages build in both Ubuntu and CentOS
Also fix a mistake in the naming for DEBIAN packages, which should be a
no-op since both the DEBIAN and RPM PACKAGE_RELEASE variables are the
same right now
Change-Id: I70659d2e1b6ff9027b8564ca4366d81b0c164760
Signed-off-by: Kent Russell <kent.russell@amd.com>
[ROCm/ROCR-Runtime commit: 1290d4d56c]
Harish Kasiviswanathan
Kent Russell
Oak Zeng
Chengming Gui
Eric Huang
Laurent Morichetti
Amber Lin
Alex Sierra
Philip Yang
Jonathan Kim
Mukul Joshi
Yong Zhao
Jay Cornwall
Ori Messinger
Gang Ba
changzhu
Prike.Liang