b38317cb3c
Add COMGR_DYN_DLL to device/rocm/CMakeLists.txt
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Now rocm/rocdevice.cpp also includes comgrctx.hpp, and we don't want to statically link against comgr when buidling shared libs.
Change-Id: Ic330bd860559b3e07b776c951afe6126b0f43f7d
2020-10-14 09:28:37 -04:00
26d1b28b16
[PAL] Allow overriding reported asic revision
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This is helpfull to do when debugging issues on lowend asics. Navi14 can be emulated as Navi10. So can Navi22 be emulated as Navi21.
Change-Id: I693ffd45a5b03657822afdc872781901bc69b65c
2020-10-13 09:36:15 -04:00
92f1ce41dc
SWDEV-254185 : hiprtc headers - handle empty headerIncludeNames
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Change-Id: Ie06278c18b62cef1bdfbb8ac82728ed5667b2047
2020-10-13 09:23:43 -04:00
c05de4f2f9
Add ROCr queries for HMM support
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Change-Id: I2b5508bf0faf8f48dd7348d6a5202fb28de09876
2020-10-13 09:12:00 -04:00
ac72e50adc
SWDEV-254185 - Added support to pass include headers to hipRTC
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Change-Id: Ic7f2957b04e518c57e2fd3fc9d839de07232405e
2020-10-12 03:46:04 -04:00
fd09a7a23c
[PAL] Skip extra calls to MakeResident
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With the PAL_ALWAYS_RESIDENT flag memory objects are resident at allocation time, no need to make them resident again before submit.
Also we should never evict anything with this setting, or we'll generate a VM fault.
Change-Id: Ieacc6af88ab4e09c20efd94100e148b2502e1d70
2020-10-09 14:13:32 -04:00
d9397590de
Add option to skip AQL barrier
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The change reuses HSA signals for dispatches as a wait signal.
Skipping the barrier requires to disable L2 cache for sysmem
allocations and extra tracking for HDP access with the large bar.
ROC_BARRIER_SYNC=0 activates the new logic. Barrier sync is
still used by default.
ROC_ACTIVE_WAIT=1 enables unconditional active wait in ROCr.
The change also consolidated ROCr wait logic under single function.
Change-Id: I6bd1be30aa88258da1b1f9de319ef5a45852afd8
2020-10-06 08:37:12 -04:00
4a025e1a87
[perf]hipMalloc performance optimization
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Change-Id: I6e8a918cc1c4cafad197b09e10755cd180e11ead
2020-10-06 03:19:41 -04:00
8ab8fac173
SWDEV-253548 : clean up gfx-arch macros
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Change-Id: I8deb2ea44f556260bb78d24f68b04b0c730ed4d8
2020-10-06 03:17:09 -04:00
df63547906
Add support for CPU device in advise
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Change-Id: I7250e0183580c14cd3d6050ef85f9ce26e36f4a8
2020-10-05 12:52:46 -04:00
bc7291e85c
Fix empty cpu agent on raven system
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Change-Id: I30f5e65367613152ce96b80b13e1c9f2a28da807
2020-10-05 10:54:57 -04:00
f26bb1d76d
[PAL] Add entry for unannounced device
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Change-Id: I323f240068ee1eff6981e69b7a2837f06157e44b
2020-10-02 13:52:25 -04:00
11bdf0005f
[PAL] Detect if resizable bar is enabled
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Change-Id: I54b2e878d1cf7235a848a4b243f878538e226702
2020-10-02 12:25:00 -04:00
af8426b0e4
Revert "Reduce the default size of the signal pool"
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This reverts commit e68d671a51
2020-10-01 09:56:05 -04:00
1183455755
Fix Windows build
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Change-Id: Icdc723843541a5c13503670b5f972b78db0cccbf
2020-09-30 14:40:07 -04:00
d0f009a0ee
Adding and populating available registers per cu value
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Change-Id: Ide012038a9d74b20166ce1e69a9f2c0cbdce0d73
2020-09-28 05:30:23 -04:00
4071cf1a16
SWDEV-241896 - Remove extern support in ROCclr/HIP since compiler added Texture Reference support.
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Change-Id: I2cf27e13a53860fe11e9245c9cbdcb8bd88a7872
2020-09-25 10:20:16 -04:00
40b432f992
Avoid using sdma engine if there's none
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Change-Id: Id8d373683f3e1667ab461b4c5b8b490377b64cc0
2020-09-25 09:48:10 -04:00
2e199bd492
Fix a crash when printf used in a kernel launched on a stream with custom CU mask
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SWDEV-249719 - root cause: queues with custom CU mask are not inserted
into queuePool_ (i.e., queue of reusable HSA queues) of ROC device class
causing a crash when creating hostcall buffers for printf
Change-Id: Ieee7005d9a5a30b3113394ce23ee65927126d0d6
2020-09-25 09:25:19 -04:00
18352d189b
SWDEV-253063 - Code changes to make Image Buffer Workaround only for targets gfx 10.1
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Change-Id: I17044a1c0775f427b9ba712eb3fd5ab21ed88b0e
2020-09-23 11:07:15 -04:00
7462e39954
SWDEV-252542 - Fixing Win Compilation on SWDEV-241902.
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Change-Id: If76f79002b265dccf6da4acef1ff9372d8b0a2ff
2020-09-18 12:11:56 -04:00
90c694988b
set free mem to zero avoding underflow
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Change-Id: I964b41695fb41712624146c5959a35b37eacf52d
2020-09-18 11:56:57 -04:00
a66c56d641
SWDEV-241902 - Changes to pass file descriptor and offset to load code object.
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Change-Id: I0243cccdeaa533b2a56fde42f12d5424c3b63a3b
2020-09-15 07:54:24 -04:00
11b723a605
SWDEV-251941 - Adding gfx1030,gfx1031 support to mainline
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Change-Id: I752dff86651a55f4fbf719e84ee7d3ec49f5f207
2020-09-14 09:07:44 -04:00
be0d98b433
Fix typo
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Change-Id: I571e84cab9258dfd5e94b70865505f452ed89016
2020-09-12 20:16:27 -04:00
740f1ba0aa
SWDEV-252095 - Fix progvar_prog_scope_misc test Aborted (core dumped)
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The progvar_prog_scope_misc test expects CL_DEVICE_MAX_MEM_ALLOC_SIZE to be multiple of integer.
Change-Id: Ic0690f5ab06ffa3feafb718beabbcf83ab53978c
2020-09-11 12:36:39 -04:00
677208f2de
Fix for memory leak detected in hipModule*load [SWDEV:250740]
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Change-Id: I8c4930b64764620a896079b14b27f6f87fbad292
2020-09-10 10:50:46 -04:00
5d4b6f74d3
Use std::atomic
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Replace amd::Atomic with std::atomic. Remove make_atomic uses by
converting the variable to std::atomic and making sure the memory
order is relaxed when synchronizes-with is not needed.
Delete utils/atomic.hpp.
Change-Id: I0b36db8d604a8510ac6e36b32885fd16a1b8ccfa
2020-09-09 14:55:29 -04:00
e68d671a51
Reduce the default size of the signal pool
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Implement dynamic signal pool grow per allocated queue
Change-Id: Ie8b17937d72c29cc49e59639c4b2023ea984b14c
2020-09-09 09:53:52 -04:00
65075e72f1
Fix compiling issue exposed by opencl TC build
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1.Some files are not built in rocclr so the issues are
not found in rocclr build. But the issues are exposed
in TC build.
2.Clear unused codes in test cmake file.
Change-Id: I1ad4decdf4df5237b93e1ea2547eb39a19f7dc4a
2020-09-08 12:40:22 -04:00
5ecce5c287
Remove gfxipVersion_ from device level
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Change-Id: I11485beffdb9371a20d7abcaa1d1774c102db574
2020-09-07 11:33:49 -04:00
2c2665665d
SWDEV-250136 - [LNX][Navi21][OCL over ROCr] OpenCL-GL sharing failed
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Change-Id: Id61f649f035964d14f6399dbea03137c11f8eaea
2020-09-06 10:40:56 -04:00
0163d8acc0
SWDEV-240800 - P2P device attributes support
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Change-Id: I2b060a66715f676dfb7136940e69e21288f509d8
2020-09-03 14:41:53 -04:00
d6e89ec371
Navi21 support
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Change-Id: I7263556fdb85dc0152a2a72cc0ec4d7cd5e978a6
2020-09-03 11:14:37 -04:00
8ac8384aea
Fix for HIP_VISIBLE_DEVICE [SWDEV-247751]
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Change-Id: Iff0ca6646f9d97b1ffa378c3cdc44159b6bf8ad0
2020-09-02 02:08:56 -04:00
7e8f7b5927
SWDEV-249516 - [Lnx][Navi][rocm]conformance image read write tests data error
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Change-Id: Ie1c4fda953198b49ed66fea9da23e62c686d9cea
2020-09-01 17:20:58 -04:00
9c5465f9e1
Fix OpenCL test crash on some devices
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Replace constexpr with const in kernel source
codes because some kernel compiler doesn't
support constexpr.
Replace scheduler with __amd_rocclr_scheduler
due to name change.
Change-Id: I1ad4ddcdf1df5237b83e1ea2447eb39a19f7dc4a
2020-08-29 12:29:07 -04:00
e986f5c820
Replace private libelf with elfio
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Change-Id: I4c630d78f7bf23dda85ec8480bb2790864405657
2020-08-26 12:32:13 -04:00
19d1497fa2
SWDEV-239502 - fix interop regression
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When header==0, the legitimate packet->header is wiped out, so also add an assert.
Change-Id: I6b3037d4618719262b0d7c1792bd54f768a63660
2020-08-25 18:11:18 -04:00
d2b9d267b2
SWDEV-248499 Fix a crash when printf is used with cooperative kernels
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root cause - cooperative queue is not inserted into queuePool_ (HSA queues) of ROC device calss causing a crash when creating hostcall buffers for printf
Change-Id: I3f9aceb4e5fe6a7c7a2a549a4bb0a3511fe02799
2020-08-25 16:51:34 -04:00
c33470ab4d
SWDEV-239502 - Create copyImageBuffer_ without flags
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Change-Id: Ifcb5992d58f3419635d2aca2d51f2dacd7cd466d
2020-08-14 17:25:58 -04:00
e914f281ff
SWDEV-245503 - Improve hipModuleLoad performance
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Change-Id: Icbcd37d9b4e6d79f296cc8693edf25689b19fa11
2020-08-14 05:24:52 -04:00
6780a9ac66
Remove unnecessary SVM commit
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Change-Id: I5cb887ead166401a59b0c980f29fd615b19745be
2020-08-13 13:21:03 -04:00
db5a2d4c2d
SWDEV-239502 - Fix image test regression
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Change-Id: Iea35fb0f1964d09a35131b4a20ac8f6f82850a8e
2020-08-13 11:58:20 -04:00
6e69258b69
Enable prefetch async functionality
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Fix a typo with the name define, when compilation wasn't enabled.
Force CPU prefetch if system was forced in runtime
Change-Id: Id4b578f9fa44a45426fdb5d8ecb1da803aa42313
2020-08-13 11:09:10 -04:00
152a2dfb5a
SWDEV-247463 - Fix regression: ocltst segfaults
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Change-Id: Iadb55ba45d6c8ade0757fd970ac4c6cde1805de3
2020-08-09 11:28:09 -04:00
7bb671fa55
Fix HSAIL build
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Change-Id: I34209b3ae0ce0eefc30e464fd7f081a0b62449b0
2020-08-07 17:18:38 -04:00
0dc47d55d2
Sync the current queue for P2P staging
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P2P staging uses device queues for transfer, hence the current
queue must be in sync
Change-Id: I8372a60590eed9dde62cb4c67ef4df5df82a8e8d
2020-08-07 14:36:50 -04:00
6f8eaff4df
Use ARCTURUS
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Change-Id: Ib25d150c9314180178d5cf00835a06e47c02c2a9
2020-08-07 11:14:24 -04:00
f8f6bc16a1
SWDEV-246565 - Remove passing -msram-ecc to Comgr
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Change-Id: I1604a0014186a5779561da3ec3eefec65aff5c37
2020-08-06 12:48:53 -04:00
Jason Tang
Vladislav Sytchenko
agodavar
German Andryeyev
Sarbojit Sarkar
Tao Sang
Jatin Chaudhary
kjayapra-amd
Jason Tang
Aryan Salmanpour
Satyanvesh Dittakavi
Laurent Morichetti
Alex Xie