Граф коммитов

284 Коммитов

Автор SHA1 Сообщение Дата
German Andryeyev d17108e8d0 SWDEV-303560 - Remove coarse grain setup by default
The original logic was left after initial testing when HMM
couldn't handle xnack properly

Change-Id: I0abf01805704171e931dfba8b6d95bfe87d5fab1
2021-10-05 17:20:59 -04:00
kjayapra-amd 3081f7ca53 SWDEV-295277 - Report max waves per cu from ROCr backend.
Change-Id: Ie170b26b53f1cc2da851034c96b21de38ce7b563
2021-10-05 12:38:44 -04:00
Tao Sang 10abe8ab37 SWDEV-305884 - Clear up codes
Fix a log typo error
Change-Id: I887ecbdcfe414c2119247228bdd1255b8308da1d
2021-10-04 18:11:32 -04:00
Sarbojit Sarkar 22a847f3ce SWDEV-301823 - Optimize hipMemset2D/3D
Change-Id: Ibe560149a263c2ac6b08e4eb1a1d331d2aeac78c
2021-09-27 14:10:06 -04:00
Sourabh cbb8d82bdb SWDEV-292525 - [vdi] Path to streamOps shaders
Implementation to use a blit kernel to perform
a hipStreamWait/write instead of an AQL packet.

Change-Id: I462671ed5cec37144dfe97ff66439249196117c1
2021-09-27 13:59:35 -04:00
Jason Tang f212fc91ca SWDEV-1 - More 'delete' clean up
info_.extensions_ and settings_ are deleted at amd::Device()::~Device().

Change-Id: I06f240a42e5c131dbd4e61a759f905bcdf84b45a
2021-09-21 11:17:24 -04:00
German Andryeyev f116959b54 SWDEV-302383 - Get active state from device
The queue can be destroyed at the time the app will request
the event status. Hence just get the active state from the device.

Change-Id: I887ecb0cfe414c2119247228b0d1255b8308da1e
2021-09-14 19:01:44 -04:00
German Andryeyev d8a86e4870 SWDEV-282419 - Use HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE for unset
When unsetting runtime should use HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE
for the agent and not HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE

Change-Id: I3814802d1fb3b72c54e7566defafafed6b0d5cee
2021-09-13 15:05:20 -04:00
German Andryeyev 65ddfcc6a8 SWDEV-294669 - Keep one more slot for HW processing
The original logic left only one slot for HW processing in the queue.
For some reason there is a race condition on CPU overwrite of the slot
before the current active. The workaround is to avoid the previous to
the current active slot for possible unfinished HW processing.

Change-Id: I565495a8feeaedffc9fc8a505edbee5ff5816975
2021-09-13 13:56:05 -04:00
Jason Tang 73967c3b17 SWDEV-1 - Some 'delete' clean up
Change-Id: I02564f0f0e349375bde1471e9f82df268703367b
2021-09-09 12:12:40 -04:00
Saleel Kudchadker 21ba34d0fe SWDEV-297448 - Add 64bit and 16bit write support
For the fillBuffer shader, if there are two 32bit writes to a MMIO
register, it can get dropped. It has to be a single 64bit write.
Add optimization to fillBuffer to write 64bit and 16bit writes.

Change-Id: I3aa78e027898f8ae01e9c8f09004615673720c2b
2021-09-08 12:30:04 -04:00
Sarbojit Sarkar 42d33029dc SWDEV-300655 - Added thread ID to hip trace
Change-Id: I9234d4ec93e7687cd0a5d1bd930bd4f80936311b
2021-09-06 00:22:42 -04:00
Saleel Kudchadker e29b9c00ee SWDEV-301667 - Kern arg placement
Add a env var ROC_USE_FGS_KERNARG to toggle kernel arg placement
By default its in Fine Grain Kernel arg segment for supported asics.

Change-Id: I3d57ed69a1a4db2b392b0438ead499f3ddca4716
2021-09-02 12:36:49 -04:00
jujiang f63115cec6 SWDEV-286322 - clean up trailing white space
Change-Id: I01f3a559cbd1835aa2fdad7abe2bd685d90fc6a8
2021-09-01 11:45:47 -04:00
Jason Tang 7f83bcdb45 SWDEV-1 - Disable OpenCL support for gfx8 in ROCm path
Change-Id: Ie1e0c0d6273edf6b734909447c2a08252cba305b
2021-08-31 12:48:47 -04:00
Satyanvesh Dittakavi 169cc857fd SWDEV-298985 - hipMemPrefetchAsync should prefetch the data to the specified destination device
Pass the device agent specified by the user to the ROCr api instead of passing the device agent attached to the specified stream

Change-Id: I86c98935b9dc404eaa6d47ccdd082a8c3678fb36
2021-08-27 05:12:07 -04:00
Satyanvesh Dittakavi 48c1b895c0 SWDEV-299491 - Update data index in GetSvmAttributes appropriately
Fixes Seg fault caused when the attribute hipMemRangeAttributeAccessedBy
is queried using hipMemRangeGetAttribute

Change-Id: I2ceb2267d89bfc31a55d9eae2685610c7ad89b1f
2021-08-26 13:36:35 -04:00
Saleel Kudchadker 75fea4dca6 SWDEV-297448 - Improve logging
Print non pointer kernel args
Change-Id: Ice0dbc894aae1430ac085df319f4b91dfa21665a
2021-08-25 15:46:06 -07:00
Saleel Kudchadker 24442be35a SWDEV-297448 - Refactor streamOperations code
Reuse FillMemory function, that should fix the cache syncs from the host

Change-Id: Ieebec5fc3ed3a322b88d5187c8dca4805ec6f84b
2021-08-25 12:33:02 -04:00
Saleel Kudchadker 3a7008cf07 SWDEV-297448 - Fix typo in debug print
Change-Id: Idc94d5fcd7eabf1e9c0a9617b987c58f507813a7
2021-08-22 23:56:08 -07:00
Saleel Kudchadker 2e26ed1cbb SWDEV-297448 - Add debug log print
Change-Id: Ieba1b2e5d766e3fbe84dfc875dde8268166b3f99
2021-08-22 23:56:08 -07:00
Satyanvesh Dittakavi b46ffd5fe0 SWDEV-274145 - Fix to return correct data when queried for hipMemRangeAttributeReadMostly attribute
Change-Id: I9041c974b61e7a9c8fbdc748a407bbd04c060876
2021-08-22 23:56:08 -07:00
Vladislav Sytchenko f167136918 SWDEV-297808 - Don't update free memory counter when creating views
Current logic when creating a buffer view will end up going into the
allocation block. Even though no memory will be allocated, since
owner()->getSvmPtr() is already allocated, we'll still end up
calling updateFreeMemory().

Checking if we're creating a view, will skip the SVM allocation logic
and let us fall into the actual view creation logic. This won't end up
updating the free memory counter.

Change-Id: I1c260a9ef57895130b272ea1246e06e812b25b37
2021-08-22 23:56:08 -07:00
German Andryeyev 992830bab7 SWDEV-295555 - Add SVM mode query
The new query MemRangeAttribute::CoherencyMode can return current
coherency mode for the provided memory region. Coherency mode can
be one of the following types: FineGrain, CoarseGrain and
Indeterminate

Change-Id: Ib66feeeb14f57a8b1cc731c65bb3d0276d297ff7
2021-08-22 23:56:08 -07:00
German Andryeyev ec89348291 SWDEV-296329 - Add lock protection for Timestamp update
There is a possible race condition when signal reuse can have
access to a destroyed Timestamp object, because the callback
was running asynchronously. Use reference counter and lock
to allow asynchronous timestamp update

Change-Id: I6224f7c62cb0a03a7466fcc512e5e5afb06736fa
2021-08-22 23:56:08 -07:00
anusha GodavarthySurya 1884e4ca77 SWDEV-297215 - Set image descriptor as per the HSA specification for hsa_ext_image_descriptor_t
Change-Id: I0af0f09120f15a42349ec4de491df8aee7bfd46d
2021-08-22 23:56:08 -07:00
Rahul Garg e9c115ad78 SWDEV-293742 - Remove external refs
Change-Id: Ib9e25a6beb97cc042bb3cc50338686a8dd09e21c
2021-08-22 23:56:08 -07:00
Jason Tang f165737096 SWDEV-296911 - Enable clgl interop for both MesaGL and OrcaGL
Change-Id: Ie3ad85a8335b1fc751812c09bb0cd30aad38dcae
2021-08-22 23:56:08 -07:00
Satyanvesh Dittakavi 924695fb5e SWDEV-292021 - Fix Device Reset
- Device Reset should not purge the allocations that were not by the user
- Addresses QMCPack Test abort due to the removal of all the mem objects during reset

Change-Id: I7b7a123e72bcc985d7e51d17c2382bc618d3e041
2021-08-22 23:56:08 -07:00
German Andryeyev 2babcfbdbb SWDEV-290384 - Enable active wait on CPU if HIP requested
Change-Id: Idea5adf7a4705cb999da6785e6229fe3200dce17
2021-08-22 23:56:08 -07:00
German Andryeyev c144383971 SWDEV-290384 - Disable HSA callback for any host wait
Change-Id: Ie876deb62859f5551f4ed69eb8187ac3fa35f42a
2021-08-22 23:56:08 -07:00
German Andryeyev ff15c0893e SWDEV-292018 - Switch to internal signals for markers
Add ref counting to ProfilingSignal class to track the last release.
If a signal was used in the marker, then don't reuse it,
but create a new one for internal usage.
Don't rely on HSA callback for the command status update if there
are no pending dispatches.

Change-Id: I19f14ed9d80acfe79993b343b2187635f8428a20
2021-08-22 23:56:07 -07:00
Sourabh Betigeri 6408b9b906 SWDEV-290685 - Relacing release fence instead of acquire for hipStreamWrite()
Change-Id: Ic2946b68c427d3e058948c0813863a27c21b903d
2021-08-22 23:56:07 -07:00
German Andryeyev e4dae85ade SWDEV-290495 - Add HSA_AMD_AGENT_INFO_SVM_DIRECT_HOST_ACCESS query
Change-Id: Ib18a53a9016eb5c5ffd51bf6835cba7299ec8421
2021-08-22 23:56:07 -07:00
Sourabh Betigeri e4ddb5e08a SWDEV-290685 - Dispatch a barrier packet with acquire system scope to ensure ordering before a hipStreamWrite()
Change-Id: I8853ad86a6634d55a98173ca3f79d93b85c08f85
2021-08-22 23:56:07 -07:00
agunashe d96481fb36 SWDEV-293742 - Update copyright end year VDI repo
Change-Id: I69d2fea4a7a43adf96ccea794270e4af991c5261
2021-08-22 23:56:07 -07:00
Saleel Kudchadker cd21af757e SWDEV-260448 - Honor NUMACTL for Direct Dispatch
Setting AMD_CPU_AFFINITY=1 will keep Async Handler thread within the
bounds set by numactl.

Change-Id: Id01b30df5127d65c29ac072bf74a04986b7128de
2021-08-22 23:56:07 -07:00
German Andryeyev f4032401cf SWDEV-289378 - Avoid CPU TS overwrite if GPU TS is available
Change-Id: I444ec284669b6a6fff31182e213b47c562c90192
2021-08-22 23:56:07 -07:00
German Andryeyev 4fd506cfe1 SWDEV-289378 - Avoid CPU TS overwrite if GPU TS is available
Change-Id: I2fc1a43c048b4fa1e42f27c4cf5c72fc7ae84e9c
2021-08-22 23:56:07 -07:00
pvellien c11c02f2c7 SWDEV-285333 - Introduce Address sanitizer hostcall service
Change-Id: Id29aacd09d0a9934a027446c57c7095804e1a454
2021-08-22 23:56:07 -07:00
German Andryeyev ce8dad2ecc SWDEV-290160 - Switch to global HSA signals
Runtime can't assign internal HSA signals for HIP events, because
HIP application can destroy the HIP stream or signal reuse may
occur internally. Switch to global HSA signals for HIP events.

Change-Id: Ieaea2d6b039e492b2e7c5112782a8f4e601e50a1
2021-08-22 23:56:07 -07:00
Saleel Kudchadker 8e08880cc3 SWDEV-247372 - Add logging for debug
Change-Id: Id5a27034005a7deba37072d8a4c6f250104a96c8
2021-08-22 23:56:07 -07:00
German Andryeyev c49f1069ab SWDEV-290160 - Don't send notification for batch markers
Batch marker already has a barrier with HSA signal callback

Change-Id: I69fc63d72320c2e9cc2d2e59ebd3f07c0bd0e3b5
2021-08-22 23:56:07 -07:00
Sourabh Betigeri b2a1dc26ba SWDEV-286446 - This patch enables stream operations on vega10, vega20, MI100 and MI200
Change-Id: I6f07036d8ee6e4c6b55196a13288f8107488d824
2021-08-22 23:56:07 -07:00
Saleel Kudchadker d3213eca90 SWDEV-247372 - Reset hasPendingDispatch
Reset hasPendingDispatch_ if we insert barrier for time marker.

Change-Id: Id038fd4e1c910c0a657978fee00630e49c372321
2021-08-22 23:56:07 -07:00
German Andryeyev a1629cad26 SWDEV-290371 - Add lock protection for signal
Add lock protection for signal processing
If signal is reused, then disable reference to it from HIP
Increase the pool signal size to 32

Change-Id: I7d529b35910f83ce577c9eca6d3386759611ccc0
2021-08-22 23:56:07 -07:00
Saleel Kudchadker 0af6ba9428 SWDEV-286092 - Use Barrier Header for event
Change-Id: I9701fbab587e2ea31e58449e8c8b07341a7aa161
2021-08-22 23:56:07 -07:00
Saleel Kudchadker b416ad7b9d SWDEV-247372 - Active wait timeout env var
- Create an env var ROC_ACTIVE_WAIT_TIMEOUT to set active wait timeout
- Record profiling informaion if marker_ts_ property is valid.

Change-Id: If0d8aec8d9b0715027cf0f7c3dc8a4c722a6bae6
2021-08-22 23:56:07 -07:00
German Andryeyev 85c70a7495 SWDEV-284671 - Add HW event wait to improve hipDeviceSynchronize
If AMD event contains a reference to a HW event, then runtime
could check/wait for HW event. CPU status update will occur later
after HSA signal callback, but it's not important for the result.

Change-Id: I591391a953bbdba6a25ac07e2cd98aeb17cd4596
2021-08-22 23:56:07 -07:00
German Andryeyev 89b69638d1 SWDEV-240804 - Update ReadMostly attribute
Switch HSA_AMD_SVM_ATTRIB_READ_ONLY to
HSA_AMD_SVM_ATTRIB_READ_MOSTLY to match Cuda. The new attribute
was just exposed in ROCr/KFD.

Change-Id: I2ee522d33c347ba52a4e272d2cd7f67960490cf7
2021-08-22 23:56:07 -07:00