fcae92ce47
[PAL] Allow overriding reported asic revision
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This is helpfull to do when debugging issues on lowend asics. Navi14 can be emulated as Navi10. So can Navi22 be emulated as Navi21.
Change-Id: I693ffd45a5b03657822afdc872781901bc69b65c
[ROCm/clr commit: 26d1b28b16
2020-10-13 09:36:15 -04:00
622d3f286c
[PAL] Detect if resizable bar is enabled
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Change-Id: I54b2e878d1cf7235a848a4b243f878538e226702
[ROCm/clr commit: 11bdf0005f
2020-10-02 12:25:00 -04:00
eaf65e59ae
Remove gfxipVersion_ from device level
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Change-Id: I11485beffdb9371a20d7abcaa1d1774c102db574
[ROCm/clr commit: 5ecce5c287
2020-09-07 11:33:49 -04:00
618619e903
Navi21 support
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Change-Id: I7263556fdb85dc0152a2a72cc0ec4d7cd5e978a6
[ROCm/clr commit: d6e89ec371
2020-09-03 11:14:37 -04:00
04054e9b60
SWDEV-246565 - Remove passing -msram-ecc to Comgr
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Change-Id: I1604a0014186a5779561da3ec3eefec65aff5c37
[ROCm/clr commit: f8f6bc16a1
2020-08-06 12:48:53 -04:00
9d72bf6523
Fix typo
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Change-Id: I8b659508f567afa126aeb7749b536b443935e3df
[ROCm/clr commit: 9d0b0c32a9
2020-08-04 11:15:21 -04:00
c98a71dc9e
Only enable HIP for Vega20 on non-ROCm platforms
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SWDEV-245906
All asics will still be supported for developer builds.
Change-Id: I0eac2246162d133fe63449c200d996fe05bd51bd
[ROCm/clr commit: 24c1c48db7
2020-07-27 13:09:58 -04:00
fdf3ebad76
SWDEV-232197 - Use TargetID for action_info_set_isa_name()
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Change-Id: I6661a2bbc2e55586c1b5029694d67cb54a4f23a6
[ROCm/clr commit: 65f4230494
2020-07-22 13:47:17 -04:00
b2e264b2c1
For apu: call commitSvmMemory() from Device::svmAlloc()
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Change-Id: Ic6e9b2ad4624e7e1c50835d3825254c76e764bf0
[ROCm/clr commit: 532083f87c
2020-06-22 10:09:32 -04:00
a1974c06e9
Switch PAL to interface 610
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Change-Id: Ida563f38513789f5ba105ac92a9737c59cd5d90d
[ROCm/clr commit: 01fcf82448
2020-06-19 11:40:12 -04:00
d6a2b2247a
FEAT-30761 - Adding defaults to all Switch cases in PalDevice gfx detection.
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Change-Id: Ic998dba44d3287484d6b0da4f07f320de8e6d92b
[ROCm/clr commit: 1982c16e46
2020-06-04 20:49:58 -04:00
e44ec607ef
FEAT-30761 - Fixing fall through in gfxip major/minor detection.
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Change-Id: Ib97b3dbe993e01df3360cbeda6bd0d9d366535b6
[ROCm/clr commit: ea0137fb22
2020-05-23 12:42:44 -04:00
f94e958680
Add major/minor/stepping to device layer
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Change-Id: If82ea55a46b166b243a98089a6e9c40ccfdb479f
[ROCm/clr commit: cd2a713d63
2020-05-17 12:57:34 -04:00
5101aa9867
Correct the way to get subtarget
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Change-Id: I47805424c0bd69547cff0ab71c369552016052b5
[ROCm/clr commit: 9b5e1fec6c
2020-05-15 17:18:39 -04:00
a646af408f
Add entry for another unannounced asic
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Change-Id: I63c6ce6221e812a33e9427841be49840a8f48154
[ROCm/clr commit: 2963d0d454
2020-04-28 14:23:57 -04:00
dae0d59594
Add entry for new device id
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This is accomodate upcoming Pal::AsicRevision changes.
Change-Id: Ic108b647f3548d34b7aa83d6077fb88452768998
[ROCm/clr commit: 63b90a32c4
2020-04-28 14:23:49 -04:00
25f9a11766
SWDEV-231691
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- Problem with CL_DEVICE_GLOBAL_FREE_MEMORY_AMD query.
Check if allocated memory exceeds the total size.
Change-Id: Ieed8829860663bac1acfa41d21309dff4d8772c7
[ROCm/clr commit: e289ebdf20
2020-04-17 09:03:04 -04:00
3ee3f4e045
SWDEV-223160, SWDEV-227911- Fix Memory Copy Peer failure on Navi10 MGPU configuration
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Change-Id: I2bf559b87cba638b5af858c2d4fe5a252d16a5d9
[ROCm/clr commit: d392082a30
2020-03-26 10:13:19 -04:00
3f66311210
SWDEV-224023
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Correct typo.
Change-Id: I72131a6e0210e7b961e586cd0ae18608d21fc529
[ROCm/clr commit: 52046e41b2
2020-03-15 16:37:25 -04:00
c650d026d8
SWDEV-79445 - Fix a regression in Linux
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PAL doesn't report queue priorities under Linux
Change-Id: I3e1632ee2bcbbbaf52b45565f6b6aec24c559922
[ROCm/clr commit: c6d3aea572
2020-03-10 12:39:56 -04:00
ab1c00cee9
SWDEV-224023
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Each WGP consists of 2 CU, so the number of available SIMD units is doubled.
Change-Id: I43978a8a9139c33f5f776b344a36bee927cc187d
[ROCm/clr commit: e76d867740
2020-03-06 13:43:36 -05:00
d4e8dd876b
SWDEV-79445
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Add MS HWS support. PAL reports just one compute engine
in that mode and runtime needs extra logic to detect RT queues.
Change-Id: I011f1f1b18dec6a7195a4f1fe939f8029bc269ae
[ROCm/clr commit: 622c714165
2020-02-28 19:05:17 -05:00
93d797f9a0
Enable SVM atomics for HIP/Win
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hip_threadfence_system passes locally with this change. This also fixes
hipHostMalloc() failures when hipHostMallocMapped flag is used.
Change-Id: Id412efe502accc7c6e7676b52c05ccb9d8fbbe67
[ROCm/clr commit: 5de65ba4a0
2020-02-19 23:22:37 -05:00
801fe99636
SWDEV-222307 - Add CMake support for PAL
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Remove dependency on COMGR headers from backends.
Remove GFX103 PAL defines.
Change-Id: I6ff76dca2a0c84bc191e8fc8b639f2f5872d2085
[ROCm/clr commit: 1be1e69f2a
2020-02-18 10:56:31 -05:00
0ddfa04517
Implement HIP_HIDDEN_FREE_MEM env var
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Set value to 256Mb to reflect what HIP/HCC reserves
Change-Id: Icaadf79f60d3916965ac168da237d15b975b1fe4
[ROCm/clr commit: 0730b39adb
2020-02-14 12:57:11 -05:00
7de346234a
Fix build errors for PAL and GSL
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The last commit to replace the cl_* types with standard types
failed to correct issues introduced in the PAL and GPU backend.
Change-Id: I926997234dfbe346fc165a7bc4e1b8aabab7bac5
[ROCm/clr commit: b81816f482
2020-02-13 16:52:32 -05:00
b3297f189d
Replace cl_* integral types with standard types.
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cl_bool -> bool
cl_int -> int32_t
cl_uint -> uint32_t
cl_long -> int64_t
cl_ulong -> uint64_t
cl_float -> float
cl_double -> double
cl_bitfield -> uint64_t
Change-Id: I840c8993b55f98f5b745d21e27f5f28233647a58
[ROCm/clr commit: d9d9c69399
2020-02-12 13:16:06 -08:00
aaf154b30b
Add CMake support for PAL backend
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Change-Id: Id0673d43217be305aa4ca7a612c416baee3fb23c
[ROCm/clr commit: da5f4c554e
2020-02-10 11:18:24 -05:00
e284923583
Update copyright info
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Change-Id: Ia4f9ff0f5f873b4223a8cca154188bb0d2f1abba
[ROCm/clr commit: b4c6143a2f
2020-02-04 09:26:14 -08:00
011f3e945b
Merge branch 'origin/pghafari/vdi-prototype' into lmoriche/amd-master
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Change-Id: Id3b833d405596735becb3346f3b08c6da57033fe
[ROCm/clr commit: 20c7173849
2020-01-30 20:12:13 -08:00
Vladislav Sytchenko
Jason Tang
Jason Tang
German Andryeyev
kjayapra-amd
jujiang
Saleel Kudchadker
Laurent Morichetti