d49fa8d06b
SWDEV-413997 - Handling cases where multiple phys_mem is mapped into a single virtual address.
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Change-Id: Ie678e607a64f2e5c35a10b9083185f041c5527ac
[ROCm/clr commit: 49b4aef8c9
2024-04-28 08:28:12 -04:00
b1c0f73229
SWDEV-353281 - Corret VA unmap
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Make sure graph mempool unmaps VA on release
Change-Id: Id3f1bd8d0115b533ae60aa5ba3676b8bf7e5b961
[ROCm/clr commit: 5c1804aa14
2024-04-26 09:37:01 -04:00
32e94ef1cc
SWDEV-457859 - Initialize isWGPMode_ in WorkGroupInfo
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Change-Id: Ie3f3c0bcea84368c1b0607fd52b4bc7cae41c512
[ROCm/clr commit: cffff4e1cb
2024-04-25 16:36:55 -04:00
15b8dc404c
SWDEV-420016 - Add more driver side graph APIs
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Signed-off-by: shadi <shadi.dashmiz@amd.com >
Change-Id: Iff3ee7dcbcd24836f227fdc9bd5ff4b554ac914f
[ROCm/clr commit: f2b01782ac
2024-04-25 12:50:43 -04:00
08e7942cf8
SWDEV-447691 - Correct handle type for DX12 semaphore
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Change-Id: Id23882286cb2a0d0472964ffc501ab27b7dc7f00
[ROCm/clr commit: 9fdddb7c5d
2024-04-25 11:24:56 -04:00
b052e90ea8
SWDEV-451099 - Added include for __half type definitions for non-HIP code on windows
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Change-Id: Id80cef5a36db8707276de052cbaf73b6826d222f
[ROCm/clr commit: 2841aab017
2024-04-24 15:31:31 -04:00
d1507ad475
SWDEV-353281 - Align VA size
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Lower layer ignores alignment
Change-Id: If16df951ecefddc804a6effe013058afc595d30f
[ROCm/clr commit: 5c23440199
2024-04-24 15:22:20 -04:00
a2b2a6752d
457619 - Fixed the broken link to build HIP instructions
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Change-Id: Ica87b4ab511d26e0372502f069afc0e3baaa3256
[ROCm/clr commit: 1761f1b7f5
2024-04-24 11:41:07 -04:00
85a372e4eb
[SWDEV-454661][SWDEV-454653] - GraphExecMemcpyNodeSetParam to return error on memcpy direction change
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Change-Id: I2c8f5ea394caeaaa6895003e63cd62a052c491f8
[ROCm/clr commit: 880963346d
2024-04-23 12:56:30 -04:00
99e538f29e
Switch luxmark to lightning compiler for all ASICs
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Change-Id: Idcd37628a2167f0bd2db2a83132a1862cbd051b0
[ROCm/clr commit: 5a715ed160
2024-04-23 10:00:39 -04:00
f613be3d81
SWDEV-413997 - Cleanup fixes for Virtual Memory Management.
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Change-Id: I9a4a4d9087b5daf15e3ba31e786d34db431212a1
[ROCm/clr commit: 74ffc5f0d5
2024-04-22 10:58:06 -04:00
a2ffb2ad40
SWDEV-440746 - Release last command on terminate
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Change-Id: Ib6a9b8fc9a8692eb17b39b854cefd92c6b59733f
[ROCm/clr commit: 0ccdb3e160
2024-04-22 09:57:38 -04:00
74d80fb509
SWDEV-440746 - Remove obsolete code
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The "optimized" version of memcpy is outdated and
was used in win32 only.
Change-Id: I7f2e0e9051e37cec95438266824b5b0025c324c6
[ROCm/clr commit: 7448113cfc
2024-04-22 09:56:42 -04:00
2335c92a1a
SWDEV-455041 - Continue processing fat binary even if other code object bundle processing fail.
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Change-Id: Iea553ab0265c08341f915644075ce2b6ed9b3200
[ROCm/clr commit: 863c56262e
2024-04-20 14:25:49 -04:00
cb1f02f4f7
SWDEV-453180 - Add UUID support for HIP_VISIBLE_DEVICES on Windows
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- UUID needs to be specified in the format GPU-<body>, <body> encodes UUID as a 16 chars
- Convert set UUID in HIP_VISIBLE_DEVICES to device index internally
- Then use existing device index logic for HIP_VISIBLE_DEVICES
Change-Id: I654f492a49cd4d7a9b7339360ab558165240caa5
[ROCm/clr commit: fb217fa9e0
2024-04-20 02:39:19 -04:00
02d949ec38
SWDEV-440746 - Wait for signal before release
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Change-Id: I9e2aefdbcbba153c7f1080d80aab7a345eaf1eb4
[ROCm/clr commit: 329ba271fa
2024-04-19 18:33:28 -04:00
00fb29aab6
SWDEV-353281 - Reuse timestamp on memory reuse
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Mempool may reuse memory without a wait. Hence, the timestamp has
to be preserved and can't be destroyed.
Change-Id: I6f095f44afa69887a4b7aeb3b329804aedd96f3e
[ROCm/clr commit: ffb516db3e
2024-04-19 18:00:29 -04:00
7eaba0bd33
SWDEV-440746 - Don't set CL_SUBMITTED twice
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Change-Id: I9ba34454f7487d6bc0d398b322a147cbac6c6443
[ROCm/clr commit: fd81490bb8
2024-04-19 17:36:51 -04:00
2e58154d80
SWDEV-446610 - Attribute HIP_POINTER_ATTRIBUTE_SYNC_MEMOPS should return the correct value
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Change-Id: Ieced2ee61bba28f2d1df96893a661287b0a5c7b7
[ROCm/clr commit: 8f7acbdadb
2024-04-19 14:40:09 -04:00
2f430138c5
SWDEV-451594 - Implement Readback and Avoid HDP Flush workaround for device kernel args
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Change-Id: I6d41a089a17f55306e7ff402588a1e831b20a7a7
[ROCm/clr commit: bf74ef4025
2024-04-19 09:29:20 -04:00
c7022ad6ce
SWDEV-455869 - Revert "SWDEV-410751 - Consider null amd::memory is invalid."
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This reverts commit 60a3077ed4e829ef68e4
2024-04-19 00:54:26 -04:00
71aa6ff3a0
SWDEV-413997 - VMM IPC implementation for Linux.
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Change-Id: Icfeb83ca51e96be35abb67a94d6e3e1a1ca5a934
[ROCm/clr commit: 56ebf5157a
2024-04-18 11:28:13 -04:00
b77908a819
SWDEV-450053 - Handle MemcpyNodeSetParamsTo/FromSymbol negative parameters
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For all windows allocation on SVM memory tagged with flag ROCCLR_MEM_INTERPROCESS.
hipHostMalloc validation is based on flag. So remove ROCCLR_MEM_INTERPROCESS before check.
Change-Id: I823bbf228d9a4a9acb4abffc01ac6b3f544c6e12
[ROCm/clr commit: 8179fa98a2
2024-04-18 05:39:35 -04:00
3dae883e73
SWDEV-453535 - Capture hipMemset3DAsync.
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Change-Id: I517c2557573db258b3e3e353f02f6a56652b0fde
[ROCm/clr commit: 12e0bdcd32
2024-04-18 00:05:45 -04:00
24bb38acb8
SWDEV-455346 - End wait if HostcallListener terminates.
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Change-Id: I21ec8eadb189147c579ec65acf68de40d604686b
[ROCm/clr commit: 8942939fac
2024-04-18 00:04:00 -04:00
562f3ef098
SWDEV-440746 - Fix the hostcall buffer creation
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Avoid a deadlock on the host call buffer creation. Since the buffer will be
allocated in the queue thread, then use direct device memory allocation
skipping the global context lock.
Change-Id: I09b55ee03bb42ab5d320c152b52a8c842c5fdcc1
[ROCm/clr commit: 62559a6e5a
2024-04-17 12:37:23 -04:00
d2b2b2c5fa
SWDEV-441603 - Correct dst device
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Signed-off-by: sdashmiz <shadi.dashmiz@amd.com >
Change-Id: Ie60aa598dd73df66cdf02c1d96daf2dfccba7a59
[ROCm/clr commit: d511e57257
2024-04-17 09:21:06 -04:00
5a7b0c50ad
SWDEV-379007 - fix bool check for fp8_fnuz
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for fnuz nums zero val is 0x00, -0 i.e. 0x80 would be a NaN
Change-Id: Ibdc4fb4b9fb307b5952434f08d45a8ddd6262db8
[ROCm/clr commit: d7b0d78fad
2024-04-17 05:31:21 -04:00
c44b565943
SWDEV-454959 - ignore the upper half of the mask in wave32 mode
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Change-Id: If027dd8cbe5cbe142fff353cb72c16f08e9aea8e
[ROCm/clr commit: 03562a2547
2024-04-17 10:12:57 +05:30
e3266682d0
SWDEV-455699 - removing HW_REG_TRAPSTS for gfx12
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Change-Id: I5f8b030eefdb37d3d51da3e135e5aa0f18ad9018
[ROCm/clr commit: 5ddca5854c
2024-04-16 19:46:21 -04:00
80f02a1534
SWDEV-379007 - use avx instruction for bf16 cvt
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AMD CPUs have had avx512_bf16 support for quite some time now (from
consumer Ryzen 7000 series to enterprise grade CPUs). This
patch should allow users to use the hardware bf16 unit when running the
__host__ variants of the function. This can be enabled via `hipcc ...
-mavx512vl -mavx512bf16`.
Change-Id: I67c377afc95ddfe8d45a048dce078a247d4a1878
[ROCm/clr commit: 49349f168c
2024-04-16 18:35:08 -04:00
7f195e2996
SWDEV-444670 - Enable teardown class
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Force implicit runtime teardown with a global destructor.
Change-Id: Iabe63dedf5b94fefc98668585c45a61607120669
[ROCm/clr commit: c95a75a2bf
2024-04-16 12:00:06 -04:00
854cbe1d24
SWDEV-422580 - Adding back the pcie.function to PCI address string in hipGetDevicePCIBusId.
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Change-Id: I932724cc872d7ae2643ce6ac2924901cb49cd7ad
[ROCm/clr commit: a1e0970d6d
2024-04-16 07:28:48 -04:00
5e42260071
SWDEV-379007 initial implementation of fp8 header
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Change-Id: Id9a5a85641882961e4d860a815217c641e6f3387
[ROCm/clr commit: ca07f59fb1
2024-04-16 05:37:59 -04:00
26b7b7b951
SWDEV-453577 - Fixes to account for right CU count based on WGP or CU mode
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Change-Id: Ib9739f9917bc6ff69cc76f444d909311922ebc1e
[ROCm/clr commit: fcfe2ec88b
2024-04-15 11:53:43 -04:00
867769b0ec
SWDEV-413997 - Fixing alignment validation check for power of 2 instead of granularity factor.
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Change-Id: I1e0db6e0628c09d26850e5a0339e2a4660442db8
[ROCm/clr commit: 00ddc3e284
2024-04-15 09:45:29 -04:00
79b3fc1fb8
SWDEV-413997 - Read Access can be valid now that ROCr takes care of access.
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Change-Id: Iecda74ca0207c95d3fbed8b4e15c8c4c5895d939
[ROCm/clr commit: 815e450cfd
2024-04-15 06:00:14 -04:00
f7dc86bdf4
SWDEV-453180 - Add UUID support for HIP_VISIBLE_DEVICES on Linux
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- UUID is Ascii string with a maximum of 21 chars which uniquely identifies a GPU
- Convert set UUID in HIP_VISIBLE_DEVICES to device index internally
- Then use existing device index logic for HIP_VISIBLE_DEVICES
Change-Id: I8cab4fe42459f8209b97f909300789e6e687b9ac
[ROCm/clr commit: 52db98edd9
2024-04-13 22:07:19 -04:00
765e6f5d2f
SWDEV-413997 - Fixing multiple device cases.
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Change-Id: I10ad3fbfca887e92cd81f68392fa1acf753cbd2b
[ROCm/clr commit: d52d16c8e6
2024-04-13 06:14:03 -04:00
27dec1c62d
SWDEV-455254 - Reduce blit kernels signature
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Remove offset from blit kernels, since it can be applied in setup.
Change-Id: I06b585068d68a0ee8e125ddf46a36fccb372f30d
[ROCm/clr commit: 7de7da4016
2024-04-12 14:45:55 -04:00
cbbf49f5e7
SWDEV-424956 - Fix half vector printf issue
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Refactor PrintfDbg::outputArgument() to remove potential risk.
Fix half vector printf issue on all devices.
Fix FEAT-56794 as well.
Change-Id: Iae39359d2128588def2e43d77fe58e868b8e71ff
[ROCm/clr commit: 35c80dd482
2024-04-12 14:25:44 -04:00
b855d3f1ed
SWDEV-436754 - Use glbctx instead so that ref count increments for multi devices and chunk decommit gets delayed.
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Change-Id: Ia4b0d5fbfa8f198776e52d14de8b22c6942f740d
[ROCm/clr commit: d52168b46d
2024-04-12 00:04:34 -04:00
f29d608ca3
SWDEV-455254 - Add kernel arg optimization
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Add kernel arguments optimization into blit path.
Enabled by default on MI300.
Change-Id: I2694a81b90d48ad07d86dfe4c0c64fe187bada8e
[ROCm/clr commit: f0c7ecf617
2024-04-10 18:08:37 -04:00
ed9c629ad6
SWDEV-446298 - Adding error code to the logs on p2p hsa api failure.
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Change-Id: Ic41b1ad1b64cca0e31986337a83a5146d52a7328
[ROCm/clr commit: 2b8634bada
2024-04-10 06:00:00 -04:00
565f915ebe
SWDEV-379007 - add __hip_bfloat16_raw types
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This also brings bfloat16 implementation closer to CUDA's.
Change-Id: I23f381141faacd6537923ae9b88ada4d661db496
[ROCm/clr commit: 481912a1fd
2024-04-09 05:32:13 -04:00
4285981222
SWDEV-301667 - Fix SDMA mask reuse
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If we are using the mask returned by getLastUsedSdmaEngine() then we
need to apply the SDMA Read/Write mask to it before using with HSA
copy_on_engine API.
Change-Id: I6e5dc6c187eeb3c61ee159e9d2a0fa7b4737c06e
[ROCm/clr commit: 3f0bcf7834
2024-04-08 15:42:52 -04:00
7cc5dd56ab
SWDEV-451964 - Limit gpu single allocation percentage for gfx940 only
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Change-Id: Iadcdadd734e7aeeb23742e426353defa972d3ad5
[ROCm/clr commit: dbac2976e4
2024-04-05 09:43:42 -04:00
78008c05c5
SWDEV-453301 - Remove the option to write multiple packets in dispatchGenericAqlPacket
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Dispatching multiple packets with ring the doorbell once is not supported by the lower layers
Change-Id: I7665a2dcdd4ef9e47dadfe410180fed64c5a4ee0
[ROCm/clr commit: d7f352dbed
2024-04-05 05:28:10 -04:00
9630492a1d
SWDEV-450361 - Add nullptr validation for waitStream
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- Application is passing null for parameter stream in API hipStreamWaitEvent
- When event stream isn't capturing and event is not recorded, causes segfault because we are accessing deviceId() from waitStream
Change-Id: I8b87ffd6f234677f68b66dcb7ef44b2ff04a7c91
[ROCm/clr commit: 880f1f0049
2024-04-04 02:07:18 -04:00
e89ea8577d
SWDEV-446726 - Disable large bar for 32 bit windows
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When large bar is enabled, persistent memory leads to overallocation for 32 bit architecture.
Change-Id: Iae39359d8128588de02e42d77fe58e868b8e71fd
[ROCm/clr commit: bc80802c1a
2024-04-03 15:36:41 -04:00
kjayapra-amd
German Andryeyev
Ioannis Assiouras
shadi
Julia Jiang
Rahul Manocha
Konstantin Zhuravlyov
Rakesh Roy
Satyanvesh Dittakavi
Anusha GodavarthySurya
Jaydeep Patel
Jatin Chaudhary
Sameer Sahasrabuddhe
pghafari
Sourabh Betigeri
taosang2
Saleel Kudchadker
cadolphe