Commit Graph

21 Commitit

Tekijä SHA1 Viesti Päivämäärä
Aryan Salmanpour d03ee6eff6 Add an environment variable for setting a global CU mask
Change-Id: I773b152023c7b8e1e679a42015748f9b23fd946d
2020-11-20 10:05:09 -05:00
German Andryeyev 532f0ae951 Add direct dispatch simple hack for testing
The hack dosn't really track the commands status. It may be not
necessary for HIP, but will cause early resource release.

Change-Id: I791ad36dd8abd3b6b3d2c9b16a210a555c08ca64
2020-11-13 10:36:23 -05:00
Vladislav Sytchenko 2ec5a47c88 [PAL] Allow for embedding debug info into IBs
Change-Id: I4473b9c5aa36370d9af37f22a78f4414eaa21e01
2020-10-14 15:54:48 -04:00
Vladislav Sytchenko 26d1b28b16 [PAL] Allow overriding reported asic revision
This is helpfull to do when debugging issues on lowend asics. Navi14 can be emulated as Navi10. So can Navi22 be emulated as Navi21.

Change-Id: I693ffd45a5b03657822afdc872781901bc69b65c
2020-10-13 09:36:15 -04:00
German Andryeyev d9397590de Add option to skip AQL barrier
The change reuses HSA signals for dispatches as a wait signal.
Skipping the barrier requires to  disable L2 cache for sysmem
allocations and extra tracking for HDP access with the large bar.
ROC_BARRIER_SYNC=0 activates the new logic. Barrier sync is
still used by default.
ROC_ACTIVE_WAIT=1 enables unconditional active wait in ROCr.
The change also consolidated ROCr wait logic under single function.

Change-Id: I6bd1be30aa88258da1b1f9de319ef5a45852afd8
2020-10-06 08:37:12 -04:00
Saleel Kudchadker ec73340348 Add Queue profling param and toggle for HIP
Use signal timestamps if NDRange command takes forceProfile flag.

Change-Id: Ib7f187d781fd78a7346818afb3344a9378f4c104
2020-08-06 03:09:53 -04:00
Vlad Sytchenko 20c24cae93 Revert "Added file logging for rocclr & HIP"
This reverts commit 5f055d227d.

This change broke the legacy-complib build in p4. It seems that we can't use any flags in debug.cpp.

Change-Id: I17bb83651b85d6f415d9074634b479658fd4c3f9
2020-06-23 16:46:56 -04:00
Sarbojit Sarkar 5f055d227d Added file logging for rocclr & HIP
Change-Id: Ic0a54f6ee82d010b011739e0059778ed31833518
2020-06-23 04:30:36 -04:00
German Andryeyev c5afd5d412 Initial HMM support
- Expose ROCclr interfaces for HIP usage
- ROCr interfaces aren't available in staging, thus control the
build with AMD_HMM_SUPPORT define

Change-Id: Iadc2bcc230e78d3b0dc22b235189c8cc80843446
2020-06-12 09:06:07 -04:00
Payam Ghafari ac8d1ba687 Revert "adding HIP_ENABLE_LAZY_KERNEL_LOADING flag"
This reverts commit a3b730b595.

Reason for revert: HIP_ENABLE_LAZY_KERNEL_LOADING is needed before the runtime is initialized, so this utility cannot be used

Change-Id: I49f8ddb98c9a85b9a77b8fd4b236d06b6b2b0f32
2020-05-29 21:26:25 -04:00
German Andryeyev fb401bfe6d Revert "Revert "Reenable cooperative groups""
This reverts commit abc115bda8.

Reason for revert: <INSERT REASONING HERE>

Change-Id: I93c45fae27e0a08b199542d44fb0d65fc74ea13c
2020-05-25 14:11:58 -04:00
Aakash Sudhanwa abc115bda8 Revert "Reenable cooperative groups"
This reverts commit 82dc1a6343.

Reason for revert: <INSERT REASONING HERE>

Change-Id: I8954b37c354382804a139d80e2551c381fd9b2ed
2020-05-19 18:21:48 -04:00
Jason Tang 49224d95c7 SWDEV-236894 - Rename LOG_LEVEL to AMD_LOG_LEVEL
Change-Id: Ibdfaf0fb615ac343c05d0fa3c3ace9cbb592ecf3
2020-05-19 17:32:24 -04:00
German Andryeyev 82dc1a6343 Reenable cooperative groups
Change-Id: Ia43049ef550bffa6d21704dbd306ddb9c1d56af0
2020-05-15 12:41:12 -04:00
Payam a3b730b595 adding HIP_ENABLE_LAZY_KERNEL_LOADING flag
Change-Id: Ia4425e00d97a25bcea656e2ade5cd3a5d92b4de6
2020-05-13 13:06:55 -04:00
Saleel Kudchadker d10d691e76 Add env var to toggle large bar support in runtime
Use ROC_ENABLE_LARGE_BAR (0/1) to toggle. The support is
enabled by default.

Change-Id: I6cb93a46594cb6f5e90bf6057738330225efb553
2020-05-12 13:20:06 -04:00
Saleel Kudchadker 5f64e6e7ad Add a threshold for forcing ROCr to take blit path
This workaround is to avoid performance penalty of SDMA engine
taking a while to clock up from a lower DPM state. Add env var
GPU_FORCE_BLIT_COPY_SIZE (1024 by default for HIP in KB). Forcing
Src and Dst agent to be amdgpu makes ROCr take blit copy path for
what otherwise should have been SDMA copy

Change-Id: I222f687155f86000d17d66d25182e490b6710463
2020-04-28 17:11:24 -04:00
German Andryeyev 374f612b7c SWDEV-193956
[hipclang-vdi-rocm][perf]~45% to 50% of Performance drop on
rocBLAS_int8 test

- Enable AMD_OPT_FLUSH optimization by default to match HCC
- Disable CPU writes to GPU memory on boards with large bar,
because it requires HDP flush tracking.
- Enable L2 cache on kernel arguments, because L2 will be
invalidated on memory reuse .

Change-Id: I124cf250bdd4d19c523ce542c163813828f8fbdc
2020-02-18 14:26:00 -05:00
Saleel Kudchadker 0730b39adb Implement HIP_HIDDEN_FREE_MEM env var
Set value to 256Mb to reflect what HIP/HCC reserves
Change-Id: Icaadf79f60d3916965ac168da237d15b975b1fe4
2020-02-14 12:57:11 -05:00
Laurent Morichetti b4c6143a2f Update copyright info
Change-Id: Ia4f9ff0f5f873b4223a8cca154188bb0d2f1abba
2020-02-04 09:26:14 -08:00
Laurent Morichetti 20c7173849 Merge branch 'origin/pghafari/vdi-prototype' into lmoriche/amd-master
Change-Id: Id3b833d405596735becb3346f3b08c6da57033fe
2020-01-30 20:12:13 -08:00