This test does not work if block size is greater than wave size
since it relies on lock-step execution of the kernel in the block.
If there are more than waves in the block, the threads in the block
miss synchronization since one wave may finish before another wave.
Due to this bug, the test fails on GFX10 wave32 mode.
This patch fixes that so that it works for block size greater than
wave size.
Change-Id: Ie0097066081df36cb6fe025a71d0ee5a83ec00a2
Now rocm/rocdevice.cpp also includes comgrctx.hpp, and we don't want to statically link against comgr when buidling shared libs.
Change-Id: Ic330bd860559b3e07b776c951afe6126b0f43f7d
also validate the flag argument passed to hipIpcOpenMemHandle API and return
error if it is not equal to "hipIpcMemLazyEnablePeerAccess" (defined to 0)
and it is the only supported flag currenlty for this API.
SWDEV-253462
Change-Id: Ie1c8b79c680a29dc72bf262cf53ae5e011fb1247
APIs: hipModuleLoad, hipModuleLoadData and hipModuleLoadDataEx,
hipModuleGetGlobal(), hipModuleGetFunction
Functional and negative tests
Repeated call to ModuleLoadXX/ModuleUnloadXX
Few tests are disabled now, will be enabled when functional
SWDEV-238517 for enhancing hip unit tests
Change-Id: I65c12027e32db80213468fdee1c5cc1aa3e60bfd
This is helpfull to do when debugging issues on lowend asics. Navi14 can be emulated as Navi10. So can Navi22 be emulated as Navi21.
Change-Id: I693ffd45a5b03657822afdc872781901bc69b65c
The device side assertion calls printf to write out a message. In the
device compiler, printf is expanded into a series of hostcalls that
transmit the printf payload to the host. This expansion increases the
length of the kernel, resulting in sub-optimal compilation. The
solution is to ensure that the assert() implementation is not inlined
into the kernel.
Change-Id: Ia3a075461a755cf007218f262b0863e1926c76aa
With the PAL_ALWAYS_RESIDENT flag memory objects are resident at allocation time, no need to make them resident again before submit.
Also we should never evict anything with this setting, or we'll generate a VM fault.
Change-Id: Ieacc6af88ab4e09c20efd94100e148b2502e1d70
1.Make directed_test apps linked against static libs
of hip, rocclr, rocr, roct and amd_comgr.
2.Remove custom_target amdhip64_static_combiner.
3.Support EXCLUDE_HIP_LIB_TYPE <static|shared>.
4.Simplify argument list parsing.
5.Fix hip_pch.o missing issue in samples' build.
6.Fix some original small bugs.
Change-Id: I30f5e65367613152ce86b80b13e1c9f2a28da803
Add extra API calls for managed memory: hipMemAdvise, hipMemPrefetchAsync,
hipMemRangeGetAttribute
Change-Id: Ifb09744acdf7582d278453707373c89c30e3ed03
Positive and negative test cases for atomicAdd and
AtomicAddnoRet device functions
SWDEV-238517 for enhancing hip unit tests
Change-Id: Id20ba2550d20f224004f105cdcd087002cb80e56
Additional tests for following APIs
- hipOccupancyMaxActiveBlocksPerMultiprocessor
- hipOccupancyMaxPotentialBlockSize
SWDEV-238517 for enhancing hip unit tests
Change-Id: Ib9441c1366f46a082e10eb1a572bc7d8ebe1ee37
Currently all the logic checks if __HIP_ENABLE_PCH is set, so setting it
to OFF will still enable PCH.
Switching __HIP_ENABLE_PCH to be a CMake option will enable correct
build behaviour.
Change-Id: I77a663589ffb5f2595c6ad3d144eb9466adcf250
The change reuses HSA signals for dispatches as a wait signal.
Skipping the barrier requires to disable L2 cache for sysmem
allocations and extra tracking for HDP access with the large bar.
ROC_BARRIER_SYNC=0 activates the new logic. Barrier sync is
still used by default.
ROC_ACTIVE_WAIT=1 enables unconditional active wait in ROCr.
The change also consolidated ROCr wait logic under single function.
Change-Id: I6bd1be30aa88258da1b1f9de319ef5a45852afd8
Yaxun (Sam) Liu
Jason Tang
Jason Tang
Sarbojit Sarkar
Chauncey Hui
agodavar
German Andryeyev
Rahul Garg
Aryan Salmanpour
Lakhan singh Thakur
Rupam Chetia
Julia Jiang
Vladislav Sytchenko
Freddy Paul
Tao Sang
Sameer Sahasrabuddhe
Payam
sumanthtg
Sourabh Betigeri
kjayapra-amd