foreman
8f7976d7af
SWDEV-79445 - OCL generic changes and code clean-up - Add a workaround for incorrect profiling results, when release_mem can occur later in the pipeline and breaking the timeline sequence with dispatches. Ucode can't process RM packets and cs_partial_flush at the same time, thus RM packets are delayed up to 2 cs_patial_flush calls. A workaround adds CS partial flush after dispatch and switches to write_reg_mem for TS updates Affected files ... ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/paltimestamp.cpp#4 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palvirtual.cpp#66 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palvirtual.hpp#37 edit
102 lines
3.1 KiB
C++
102 lines
3.1 KiB
C++
//
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// Copyright (c) 2015 Advanced Micro Devices, Inc. All rights reserved.
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//
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#include "os/os.hpp"
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#include "platform/perfctr.hpp"
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#include "device/pal/paldefs.hpp"
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#include "device/pal/paltimestamp.hpp"
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#include "device/pal/palvirtual.hpp"
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#include "device/pal/palcounters.hpp"
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namespace pal {
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TimeStamp::TimeStamp(const VirtualGPU& gpu, Pal::IGpuMemory* iMem, uint memOffset, address cpuAddr)
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: gpu_(gpu), iMem_(iMem), memOffset_(memOffset) {
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values_ = reinterpret_cast<volatile uint64_t*>(cpuAddr + memOffset);
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}
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TimeStamp::~TimeStamp() {}
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void TimeStamp::begin(bool sdma) {
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if (!flags_.beginIssued_) {
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gpu().iCmd()->CmdWriteTimestamp(Pal::HwPipePoint::HwPipeTop, *iMem_,
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memOffset_ + CommandStartTime * sizeof(uint64_t));
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flags_.beginIssued_ = true;
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}
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}
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void TimeStamp::end(bool sdma) {
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CondLog(!flags_.beginIssued_, "We didn't issue a begin operation!");
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gpu().iCmd()->CmdWriteTimestamp(Pal::HwPipePoint::HwPipeTop, *iMem_,
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memOffset_ + CommandEndTime * sizeof(uint64_t));
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flags_.endIssued_ = true;
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flags_.sdma_ = sdma;
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}
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inline void SetValue(uint64_t* time, uint64_t val, double nanos) {
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*time = static_cast<uint64_t>(static_cast<double>(val) * nanos);
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}
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void TimeStamp::value(uint64_t* startTime, uint64_t* endTime) {
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CondLog(!flags_.endIssued_, "We didn't send the counter end operation!");
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//! @todo optimize!
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const double NanoSecondsPerTick = 1000000000.0 / (gpu_.dev().properties().timestampFrequency);
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SetValue(startTime, values_[CommandStartTime], NanoSecondsPerTick);
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SetValue(endTime, values_[CommandEndTime], NanoSecondsPerTick);
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}
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TimeStampCache::~TimeStampCache() {
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// Release all time stamp objects from the cache
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for (uint i = 0; i < freedTS_.size(); ++i) {
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delete freedTS_[i];
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}
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freedTS_.clear();
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// Release all memory objects
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for (uint i = 0; i < tsBuf_.size(); ++i) {
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tsBuf_[i]->unmap(&gpu_);
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gpu_.queue(MainEngine).removeMemRef(tsBuf_[i]->iMem());
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gpu_.queue(SdmaEngine).removeMemRef(tsBuf_[i]->iMem());
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delete tsBuf_[i];
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}
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tsBuf_.clear();
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}
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TimeStamp* TimeStampCache::allocTimeStamp() {
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TimeStamp* ts = nullptr;
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if (0 != freedTS_.size()) {
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ts = freedTS_.back();
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freedTS_.pop_back();
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}
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if (nullptr == ts) {
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if ((tsBufCpu_ == nullptr) || ((tsOffset_ + TimerSlotSize) > TimerBufSize)) {
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Memory* buf = new Memory(gpu_.dev(), TimerBufSize);
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if (buf == nullptr || !buf->create(Resource::Remote)) {
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return nullptr;
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}
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gpu_.queue(MainEngine).addMemRef(buf->iMem());
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gpu_.queue(SdmaEngine).addMemRef(buf->iMem());
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tsBufCpu_ = reinterpret_cast<address>(buf->map(&gpu_));
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memset(tsBufCpu_, 0, TimerBufSize);
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tsOffset_ = 0;
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tsBuf_.push_back(buf);
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}
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// Allocate a TimeStamp object
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ts = new TimeStamp(gpu_, tsBuf_[(tsBuf_.size() - 1)]->iMem(), tsOffset_, tsBufCpu_);
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// Create a timestamp
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if (ts == nullptr) {
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return nullptr;
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}
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tsOffset_ += TimerSlotSize;
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}
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// Set this timestamp into DRM profile mode if it was requested
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ts->clearStates();
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return ts;
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}
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} // namespace pal
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